Stefan Hajnoczi [Tue, 4 Apr 2023 15:33:07 +0000 (11:33 -0400)]
aio-wait: avoid AioContext lock in aio_wait_bh_oneshot()
There is no need for the AioContext lock in aio_wait_bh_oneshot().
It's easy to remove the lock from existing callers and then switch from
AIO_WAIT_WHILE() to AIO_WAIT_WHILE_UNLOCKED() in aio_wait_bh_oneshot().
Document that the AioContext lock should not be held across
aio_wait_bh_oneshot(). Holding a lock across aio_poll() can cause
deadlock so we don't want callers to do that.
This is a step towards getting rid of the AioContext lock.
Cc: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Message-Id: <20230404153307.458883-1-stefanha@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Emanuele Giuseppe Esposito <eesposit@redhat.com> Reviewed-by: Kevin Wolf <kwolf@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Paolo Bonzini [Thu, 6 Apr 2023 10:17:52 +0000 (12:17 +0200)]
block: add missing coroutine_fn annotations
After the recent introduction of many new coroutine callbacks,
a couple calls from non-coroutine_fn to coroutine_fn have sneaked
in; fix them.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20230406101752.242125-1-pbonzini@redhat.com> Reviewed-by: Kevin Wolf <kwolf@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
block: add configure options for excluding vmdk, vhdx and vpc
Let's add --enable / --disable configure options for these formats,
so that those who don't need them may not build them.
Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@yandex-team.ru>
Message-Id: <20230421092758.814122-1-vsementsov@yandex-team.ru> Reviewed-by: Kevin Wolf <kwolf@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Merge tag 'vfio-updates-20230509.0' of https://gitlab.com/alex.williamson/qemu into staging
VFIO updates 2023-05-09
* Add vf-token device option allowing QEMU to assign VFs where the PF
is managed by a userspace driver. (Minwoo Im)
* Skip log_sync during migration setup as a potential source of failure
and likely source of redundancy. (Avihai Horon)
* Virtualize PCIe Resizable BAR capability rather than hiding it,
exposing only the current size as available. (Alex Williamson)
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# gpg: Signature made Tue 09 May 2023 09:15:54 PM BST
# gpg: using RSA key 42F6C04E540BD1A99E7B8A90239B9B6E3BB08B22
# gpg: issuer "alex.williamson@redhat.com"
# gpg: Good signature from "Alex Williamson <alex.williamson@redhat.com>" [undefined]
# gpg: aka "Alex Williamson <alex@shazbot.org>" [undefined]
# gpg: aka "Alex Williamson <alwillia@redhat.com>" [undefined]
# gpg: aka "Alex Williamson <alex.l.williamson@gmail.com>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 42F6 C04E 540B D1A9 9E7B 8A90 239B 9B6E 3BB0 8B22
* tag 'vfio-updates-20230509.0' of https://gitlab.com/alex.williamson/qemu:
vfio/pci: Static Resizable BAR capability
vfio/migration: Skip log_sync during migration SETUP state
vfio/pci: add support for VF token
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
target/loongarch: Terminate vmstate subsections list
This list requires a NULL terminator.
Fixes: 16f5396cec23 ("target/loongarch: Add LSX data type VReg") Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230510062405.127260-1-richard.henderson@linaro.org>
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
* target/i386: improved EPYC models
* more removal of mb_read/mb_set
* bump _WIN32_WINNT to the Windows 8 API
* fix for modular builds with --disable-system
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# gpg: Signature made Mon 08 May 2023 06:05:00 PM BST
# gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83
# gpg: issuer "pbonzini@redhat.com"
# gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [undefined]
# gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1
# Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83
* tag 'for-upstream' of https://gitlab.com/bonzini/qemu:
meson: leave unnecessary modules out of the build
docs: clarify --without-default-devices
target/i386: Add EPYC-Genoa model to support Zen 4 processor series
target/i386: Add VNMI and automatic IBRS feature bits
target/i386: Add missing feature bits in EPYC-Milan model
target/i386: Add feature bits for CPUID_Fn80000021_EAX
target/i386: Add a couple of feature bits in 8000_0008_EBX
target/i386: Add new EPYC CPU versions with updated cache_info
target/i386: allow versioned CPUs to specify new cache_info
include/qemu/osdep.h: Bump _WIN32_WINNT to the Windows 8 API
MAINTAINERS: add stanza for Kconfig files
tb-maint: do not use mb_read/mb_set
call_rcu: stop using mb_set/mb_read
test-aio-multithread: simplify test_multi_co_schedule
test-aio-multithread: do not use mb_read/mb_set for simple flags
rcu: remove qatomic_mb_set, expand comments
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Alex Williamson [Thu, 4 May 2023 20:42:48 +0000 (14:42 -0600)]
vfio/pci: Static Resizable BAR capability
The PCI Resizable BAR (ReBAR) capability is currently hidden from the
VM because the protocol for interacting with the capability does not
support a mechanism for the device to reject an advertised supported
BAR size. However, when assigned to a VM, the act of resizing the
BAR requires adjustment of host resources for the device, which
absolutely can fail. Linux does not currently allow us to reserve
resources for the device independent of the current usage.
The only writable field within the ReBAR capability is the BAR Size
register. The PCIe spec indicates that when written, the device
should immediately begin to operate with the provided BAR size. The
spec however also notes that software must only write values
corresponding to supported sizes as indicated in the capability and
control registers. Writing unsupported sizes produces undefined
results. Therefore, if the hypervisor were to virtualize the
capability and control registers such that the current size is the
only indicated available size, then a write of anything other than
the current size falls into the category of undefined behavior,
where we can essentially expose the modified ReBAR capability as
read-only.
This may seem pointless, but users have reported that virtualizing
the capability in this way not only allows guest software to expose
related features as available (even if only cosmetic), but in some
scenarios can resolve guest driver issues. Additionally, no
regressions in behavior have been reported for this change.
A caveat here is that the PCIe spec requires for compatibility that
devices report support for a size in the range of 1MB to 512GB,
therefore if the current BAR size falls outside that range we revert
to hiding the capability.
vfio/migration: Skip log_sync during migration SETUP state
Currently, VFIO log_sync can be issued while migration is in SETUP
state. However, doing this log_sync is at best redundant and at worst
can fail.
Redundant -- all RAM is marked dirty in migration SETUP state and is
transferred only after migration is set to ACTIVE state, so doing
log_sync during migration SETUP is pointless.
Can fail -- there is a time window, between setting migration state to
SETUP and starting dirty tracking by RAM save_live_setup handler, during
which dirty tracking is still not started. Any VFIO log_sync call that
is issued during this time window will fail. For example, this error can
be triggered by migrating a VM when a GUI is active, which constantly
calls log_sync.
Fix it by skipping VFIO log_sync while migration is in SETUP state.
Fixes: 758b96b61d5c ("vfio/migrate: Move switch of dirty tracking into vfio_memory_listener") Signed-off-by: Avihai Horon <avihaih@nvidia.com> Link: https://lore.kernel.org/r/20230403130000.6422-1-avihaih@nvidia.com Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Minwoo Im [Mon, 20 Mar 2023 07:35:22 +0000 (16:35 +0900)]
vfio/pci: add support for VF token
VF token was introduced [1] to kernel vfio-pci along with SR-IOV
support [2]. This patch adds support VF token among PF and VF(s). To
passthu PCIe VF to a VM, kernel >= v5.7 needs this.
This is just the compression bits of the Migration PULL request for 20230428. Only change is that we don't run the compression tests by
default.
The problem already exist with compression code. The test just show
that it don't work.
- Add migration tests for (old) compress migration code (lukas)
- Make compression code independent of ram.c (lukas)
- Move compression code into ram-compress.c (lukas)
Please apply, Juan.
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# gpg: Signature made Mon 08 May 2023 07:51:56 PM BST
# gpg: using RSA key 1899FF8EDEBF58CCEE034B82F487EF185872D723
# gpg: Good signature from "Juan Quintela <quintela@redhat.com>" [undefined]
# gpg: aka "Juan Quintela <quintela@trasno.org>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 1899 FF8E DEBF 58CC EE03 4B82 F487 EF18 5872 D723
* tag 'compression-code-pull-request' of https://gitlab.com/juan.quintela/qemu:
migration: Initialize and cleanup decompression in migration.c
ram-compress.c: Make target independent
ram compress: Assert that the file buffer matches the result
ram.c: Move core decompression code into its own file
ram.c: Move core compression code into its own file
ram.c: Remove last ram.c dependency from the core compress code
ram.c: Call update_compress_thread_counts from compress_send_queued_data
ram.c: Do not call save_page_header() from compress threads
ram.c: Reset result after sending queued data
ram.c: Dont change param->block in the compress thread
ram.c: Let the compress threads return a CompressResult enum
qtest/migration-test.c: Add postcopy tests with compress enabled
qtest/migration-test.c: Add tests with compress enabled
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Paolo Bonzini [Thu, 4 May 2023 08:20:46 +0000 (10:20 +0200)]
meson: leave unnecessary modules out of the build
meson.build files choose whether to build modules based on foo.found()
expressions. If a feature is enabled (e.g. --enable-gtk), these expressions
are true even if the code is not used by any emulator, and this results
in an unexpected difference between modular and non-modular builds.
For non-modular builds, the files are not included in any binary, and
therefore the source files are never processed. For modular builds,
however, all .so files are unconditionally built by default, and therefore
a normal "make" tries to build them. However, the corresponding trace-*.h
files are absent due to this conditional:
if have_system
trace_events_subdirs += [
...
'ui',
...
]
endif
which was added to avoid wasting time running tracetool on unused trace-events
files. This causes a compilation failure; fix it by skipping module builds
entirely if (depending on the module directory) have_block or have_system
are false.
Reported-by: Michael Tokarev <mjt@tls.msk.ru> Cc: qemu-stable@nongnu.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Babu Moger [Thu, 4 May 2023 20:53:12 +0000 (15:53 -0500)]
target/i386: Add EPYC-Genoa model to support Zen 4 processor series
Adds the support for AMD EPYC Genoa generation processors. The model
display for the new processor will be EPYC-Genoa.
Adds the following new feature bits on top of the feature bits from
the previous generation EPYC models.
avx512f : AVX-512 Foundation instruction
avx512dq : AVX-512 Doubleword & Quadword Instruction
avx512ifma : AVX-512 Integer Fused Multiply Add instruction
avx512cd : AVX-512 Conflict Detection instruction
avx512bw : AVX-512 Byte and Word Instructions
avx512vl : AVX-512 Vector Length Extension Instructions
avx512vbmi : AVX-512 Vector Byte Manipulation Instruction
avx512_vbmi2 : AVX-512 Additional Vector Byte Manipulation Instruction
gfni : AVX-512 Galois Field New Instructions
avx512_vnni : AVX-512 Vector Neural Network Instructions
avx512_bitalg : AVX-512 Bit Algorithms, add bit algorithms Instructions
avx512_vpopcntdq: AVX-512 AVX-512 Vector Population Count Doubleword and
Quadword Instructions
avx512_bf16 : AVX-512 BFLOAT16 instructions
la57 : 57-bit virtual address support (5-level Page Tables)
vnmi : Virtual NMI (VNMI) allows the hypervisor to inject the NMI
into the guest without using Event Injection mechanism
meaning not required to track the guest NMI and intercepting
the IRET.
auto-ibrs : The AMD Zen4 core supports a new feature called Automatic IBRS.
It is a "set-and-forget" feature that means that, unlike e.g.,
s/w-toggled SPEC_CTRL.IBRS, h/w manages its IBRS mitigation
resources automatically across CPL transitions.
Signed-off-by: Babu Moger <babu.moger@amd.com>
Message-Id: <20230504205313.225073-8-babu.moger@amd.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Babu Moger [Thu, 4 May 2023 20:53:11 +0000 (15:53 -0500)]
target/i386: Add VNMI and automatic IBRS feature bits
Add the following featute bits.
vnmi: Virtual NMI (VNMI) allows the hypervisor to inject the NMI into the
guest without using Event Injection mechanism meaning not required to
track the guest NMI and intercepting the IRET.
The presence of this feature is indicated via the CPUID function
0x8000000A_EDX[25].
automatic-ibrs :
The AMD Zen4 core supports a new feature called Automatic IBRS.
It is a "set-and-forget" feature that means that, unlike e.g.,
s/w-toggled SPEC_CTRL.IBRS, h/w manages its IBRS mitigation
resources automatically across CPL transitions.
The presence of this feature is indicated via the CPUID function
0x80000021_EAX[8].
The documention for the features are available in the links below.
a. Processor Programming Reference (PPR) for AMD Family 19h Model 01h,
Revision B1 Processors
b. AMD64 Architecture Programmer’s Manual Volumes 1–5 Publication No. Revision
40332 4.05 Date October 2022
Babu Moger [Thu, 4 May 2023 20:53:10 +0000 (15:53 -0500)]
target/i386: Add missing feature bits in EPYC-Milan model
Add the following feature bits for EPYC-Milan model and bump the version.
vaes : Vector VAES(ENC|DEC), VAES(ENC|DEC)LAST instruction support
vpclmulqdq : Vector VPCLMULQDQ instruction support
stibp-always-on : Single Thread Indirect Branch Prediction Mode has enhanced
performance and may be left Always on
amd-psfd : Predictive Store Forward Disable
no-nested-data-bp : Processor ignores nested data breakpoints
lfence-always-serializing : LFENCE instruction is always serializing
null-sel-clr-base : Null Selector Clears Base. When this bit is
set, a null segment load clears the segment base
These new features will be added in EPYC-Milan-v2. The "-cpu help" output
after the change will be.
x86 EPYC-Milan (alias configured by machine type)
x86 EPYC-Milan-v1 AMD EPYC-Milan Processor
x86 EPYC-Milan-v2 AMD EPYC-Milan Processor
The documentation for the features are available in the links below.
a. Processor Programming Reference (PPR) for AMD Family 19h Model 01h,
Revision B1 Processors
b. SECURITY ANALYSIS OF AMD PREDICTIVE STORE FORWARDING
c. AMD64 Architecture Programmer’s Manual Volumes 1–5 Publication No. Revision
40332 4.05 Date October 2022
Babu Moger [Thu, 4 May 2023 20:53:09 +0000 (15:53 -0500)]
target/i386: Add feature bits for CPUID_Fn80000021_EAX
Add the following feature bits.
no-nested-data-bp : Processor ignores nested data breakpoints.
lfence-always-serializing : LFENCE instruction is always serializing.
null-sel-cls-base : Null Selector Clears Base. When this bit is
set, a null segment load clears the segment base.
The documentation for the features are available in the links below.
a. Processor Programming Reference (PPR) for AMD Family 19h Model 01h,
Revision B1 Processors
b. AMD64 Architecture Programmer’s Manual Volumes 1–5 Publication No. Revision
40332 4.05 Date October 2022
Babu Moger [Thu, 4 May 2023 20:53:08 +0000 (15:53 -0500)]
target/i386: Add a couple of feature bits in 8000_0008_EBX
Add the following feature bits.
amd-psfd : Predictive Store Forwarding Disable:
PSF is a hardware-based micro-architectural optimization
designed to improve the performance of code execution by
predicting address dependencies between loads and stores.
While SSBD (Speculative Store Bypass Disable) disables both
PSF and speculative store bypass, PSFD only disables PSF.
PSFD may be desirable for the software which is concerned
with the speculative behavior of PSF but desires a smaller
performance impact than setting SSBD.
Depends on the following kernel commit: b73a54321ad8 ("KVM: x86: Expose Predictive Store Forwarding Disable")
stibp-always-on :
Single Thread Indirect Branch Prediction mode has enhanced
performance and may be left always on.
The documentation for the features are available in the links below.
a. Processor Programming Reference (PPR) for AMD Family 19h Model 01h,
Revision B1 Processors
b. SECURITY ANALYSIS OF AMD PREDICTIVE STORE FORWARDING
Michael Roth [Thu, 4 May 2023 20:53:07 +0000 (15:53 -0500)]
target/i386: Add new EPYC CPU versions with updated cache_info
Introduce new EPYC cpu versions: EPYC-v4 and EPYC-Rome-v3.
The only difference vs. older models is an updated cache_info with
the 'complex_indexing' bit unset, since this bit is not currently
defined for AMD and may cause problems should it be used for
something else in the future. Setting this bit will also cause
CPUID validation failures when running SEV-SNP guests.
Signed-off-by: Michael Roth <michael.roth@amd.com> Signed-off-by: Babu Moger <babu.moger@amd.com> Acked-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20230504205313.225073-3-babu.moger@amd.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Michael Roth [Thu, 4 May 2023 20:53:06 +0000 (15:53 -0500)]
target/i386: allow versioned CPUs to specify new cache_info
New EPYC CPUs versions require small changes to their cache_info's.
Because current QEMU x86 CPU definition does not support versioned
cach_info, we would have to declare a new CPU type for each such case.
To avoid the dup work, add "cache_info" in X86CPUVersionDefinition",
to allow new cache_info pointers to be specified for a new CPU version.
Co-developed-by: Wei Huang <wei.huang2@amd.com> Signed-off-by: Wei Huang <wei.huang2@amd.com> Signed-off-by: Michael Roth <michael.roth@amd.com> Signed-off-by: Babu Moger <babu.moger@amd.com> Acked-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20230504205313.225073-2-babu.moger@amd.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Thomas Huth [Thu, 4 May 2023 08:13:51 +0000 (10:13 +0200)]
include/qemu/osdep.h: Bump _WIN32_WINNT to the Windows 8 API
Commit cf60ccc330 ("cutils: Introduce bundle mechanism") abandoned
compatibility with Windows older than 8 - we should reflect this
in our _WIN32_WINNT and set it to the value that corresponds to
Windows 8.
Signed-off-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20230504081351.125140-1-thuth@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
And take the param->mutex lock for the whole section to ensure
thread-safety.
Now, it is explicitly clear if there is no queued data to send.
Before, this was handled by param->file stream being empty and thus
qemu_put_qemu_file() not sending anything.
This will be used in the next commits to move save_page_header()
out of compress code.
Signed-off-by: Lukas Straub <lukasstraub2@web.de> Reviewed-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com>
ram.c: Dont change param->block in the compress thread
Instead introduce a extra parameter to trigger the compress thread.
Now, when the compress thread is done, we know what RAMBlock and
offset it did compress.
This will be used in the next commits to move save_page_header()
out of compress code.
Signed-off-by: Lukas Straub <lukasstraub2@web.de> Reviewed-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com>
Paolo Bonzini [Fri, 3 Mar 2023 12:12:50 +0000 (13:12 +0100)]
tb-maint: do not use mb_read/mb_set
The load side can use a relaxed load, which will surely happen before
the work item is run by async_safe_run_on_cpu() or before double-checking
under mmap_lock. The store side can use an atomic RMW operation.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Paolo Bonzini [Fri, 3 Mar 2023 10:14:15 +0000 (11:14 +0100)]
call_rcu: stop using mb_set/mb_read
Use a store-release when enqueuing a new call_rcu, and a load-acquire
when dequeuing; and read the tail after checking that node->next is
consistent, which is the standard message passing pattern and it is
clearer than mb_read/mb_set.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Paolo Bonzini [Fri, 3 Mar 2023 10:57:06 +0000 (11:57 +0100)]
test-aio-multithread: do not use mb_read/mb_set for simple flags
The remaining use of mb_read/mb_set is just to force a thread to exit
eventually. It does not order two memory accesses and therefore can be
just read/set.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Merge tag 'pull-loongarch-20230506' of https://gitlab.com/gaosong/qemu into staging
Add LoongArch LSX instructions.
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# gpg: Signature made Sat 06 May 2023 07:18:03 AM BST
# gpg: using RSA key B8FF1DA0D2FDCB2DA09C6C2C40A2FFF239263EDF
# gpg: Good signature from "Song Gao <m17746591750@163.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: B8FF 1DA0 D2FD CB2D A09C 6C2C 40A2 FFF2 3926 3EDF
Alex Bennée [Tue, 4 Apr 2023 13:27:11 +0000 (14:27 +0100)]
hw/intc: don't use target_ulong for LoongArch ipi
The calling function is already working with hwaddr and uint64_t so
lets avoid bringing target_ulong in if we don't need to.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230404132711.2563638-1-alex.bennee@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn>
Song Gao [Thu, 4 May 2023 12:28:10 +0000 (20:28 +0800)]
target/loongarch: CPUCFG support LSX
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230504122810.4094787-45-gaosong@loongson.cn>
Song Gao [Thu, 4 May 2023 12:28:09 +0000 (20:28 +0800)]
target/loongarch: Use {set/get}_gpr replace to cpu_fpr
Introduce set_fpr() and get_fpr() and remove cpu_fpr.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230504122810.4094787-44-gaosong@loongson.cn>
Song Gao [Thu, 4 May 2023 12:28:08 +0000 (20:28 +0800)]
target/loongarch: Implement vldi
This patch includes:
- VLDI.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230504122810.4094787-43-gaosong@loongson.cn>
Song Gao [Thu, 4 May 2023 12:28:07 +0000 (20:28 +0800)]
target/loongarch: Implement vld vst
This patch includes:
- VLD[X], VST[X];
- VLDREPL.{B/H/W/D};
- VSTELM.{B/H/W/D}.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230504122810.4094787-42-gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230504122810.4094787-41-gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230504122810.4094787-40-gaosong@loongson.cn>
This patch includes:
- VINSGR2VR.{B/H/W/D};
- VPICKVE2GR.{B/H/W/D}[U];
- VREPLGR2VR.{B/H/W/D}.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230504122810.4094787-39-gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230504122810.4094787-38-gaosong@loongson.cn>
Song Gao [Thu, 4 May 2023 12:28:02 +0000 (20:28 +0800)]
target/loongarch: Implement vfcmp
This patch includes:
- VFCMP.cond.{S/D}.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230504122810.4094787-37-gaosong@loongson.cn>
Song Gao [Thu, 4 May 2023 12:28:01 +0000 (20:28 +0800)]
target/loongarch: Implement vseq vsle vslt
This patch includes:
- VSEQ[I].{B/H/W/D};
- VSLE[I].{B/H/W/D}[U];
- VSLT[I].{B/H/W/D/}[U].
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230504122810.4094787-36-gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230504122810.4094787-35-gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230504122810.4094787-34-gaosong@loongson.cn>
Song Gao [Thu, 4 May 2023 12:27:58 +0000 (20:27 +0800)]
target/loongarch: Implement vfrstp
This patch includes:
- VFRSTP[I].{B/H}.
Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230504122810.4094787-33-gaosong@loongson.cn>
This patch includes:
- VBITCLR[I].{B/H/W/D};
- VBITSET[I].{B/H/W/D};
- VBITREV[I].{B/H/W/D}.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230504122810.4094787-32-gaosong@loongson.cn>
Song Gao [Thu, 4 May 2023 12:27:56 +0000 (20:27 +0800)]
target/loongarch: Implement vpcnt
This patch includes:
- VPCNT.{B/H/W/D}.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230504122810.4094787-31-gaosong@loongson.cn>
Song Gao [Thu, 4 May 2023 12:27:55 +0000 (20:27 +0800)]
target/loongarch: Implement vclo vclz
This patch includes:
- VCLO.{B/H/W/D};
- VCLZ.{B/H/W/D}.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230504122810.4094787-30-gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230504122810.4094787-29-gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230504122810.4094787-28-gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230504122810.4094787-27-gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230504122810.4094787-26-gaosong@loongson.cn>
Song Gao [Thu, 4 May 2023 12:27:50 +0000 (20:27 +0800)]
target/loongarch: Implement vsrlr vsrar
This patch includes:
- VSRLR[I].{B/H/W/D};
- VSRAR[I].{B/H/W/D}.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230504122810.4094787-25-gaosong@loongson.cn>
Song Gao [Thu, 4 May 2023 12:27:49 +0000 (20:27 +0800)]
target/loongarch: Implement vsllwil vextl
This patch includes:
- VSLLWIL.{H.B/W.H/D.W};
- VSLLWIL.{HU.BU/WU.HU/DU.WU};
- VEXTL.Q.D, VEXTL.QU.DU.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230504122810.4094787-24-gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230504122810.4094787-23-gaosong@loongson.cn>
This patch includes:
- V{AND/OR/XOR/NOR/ANDN/ORN}.V;
- V{AND/OR/XOR/NOR}I.B.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230504122810.4094787-22-gaosong@loongson.cn>
This patch includes:
- VMSKLTZ.{B/H/W/D};
- VMSKGEZ.B;
- VMSKNZ.B.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230504122810.4094787-21-gaosong@loongson.cn>
Song Gao [Thu, 4 May 2023 12:27:45 +0000 (20:27 +0800)]
target/loongarch: Implement vsigncov
This patch includes:
- VSIGNCOV.{B/H/W/D}.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230504122810.4094787-20-gaosong@loongson.cn>
Song Gao [Thu, 4 May 2023 12:27:44 +0000 (20:27 +0800)]
target/loongarch: Implement vexth
This patch includes:
- VEXTH.{H.B/W.H/D.W/Q.D};
- VEXTH.{HU.BU/WU.HU/DU.WU/QU.DU}.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230504122810.4094787-19-gaosong@loongson.cn>
Song Gao [Thu, 4 May 2023 12:27:43 +0000 (20:27 +0800)]
target/loongarch: Implement vsat
This patch includes:
- VSAT.{B/H/W/D}[U].
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230504122810.4094787-18-gaosong@loongson.cn>
Song Gao [Thu, 4 May 2023 12:27:42 +0000 (20:27 +0800)]
target/loongarch: Implement vdiv/vmod
This patch includes:
- VDIV.{B/H/W/D}[U];
- VMOD.{B/H/W/D}[U].
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230504122810.4094787-17-gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230504122810.4094787-16-gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230504122810.4094787-15-gaosong@loongson.cn>
Song Gao [Thu, 4 May 2023 12:27:39 +0000 (20:27 +0800)]
target/loongarch: Implement vmax/vmin
This patch includes:
- VMAX[I].{B/H/W/D}[U];
- VMIN[I].{B/H/W/D}[U].
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230504122810.4094787-14-gaosong@loongson.cn>
Song Gao [Thu, 4 May 2023 12:27:38 +0000 (20:27 +0800)]
target/loongarch: Implement vadda
This patch includes:
- VADDA.{B/H/W/D}.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230504122810.4094787-13-gaosong@loongson.cn>
Song Gao [Thu, 4 May 2023 12:27:37 +0000 (20:27 +0800)]
target/loongarch: Implement vabsd
This patch includes:
- VABSD.{B/H/W/D}[U].
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230504122810.4094787-12-gaosong@loongson.cn>
Song Gao [Thu, 4 May 2023 12:27:36 +0000 (20:27 +0800)]
target/loongarch: Implement vavg/vavgr
This patch includes:
- VAVG.{B/H/W/D}[U];
- VAVGR.{B/H/W/D}[U].
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230504122810.4094787-11-gaosong@loongson.cn>
Song Gao [Thu, 4 May 2023 12:27:35 +0000 (20:27 +0800)]
target/loongarch: Implement vaddw/vsubw
This patch includes:
- VADDW{EV/OD}.{H.B/W.H/D.W/Q.D}[U];
- VSUBW{EV/OD}.{H.B/W.H/D.W/Q.D}[U];
- VADDW{EV/OD}.{H.BU.B/W.HU.H/D.WU.W/Q.DU.D}.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230504122810.4094787-10-gaosong@loongson.cn>
Song Gao [Thu, 4 May 2023 12:27:34 +0000 (20:27 +0800)]
target/loongarch: Implement vhaddw/vhsubw
This patch includes:
- VHADDW.{H.B/W.H/D.W/Q.D/HU.BU/WU.HU/DU.WU/QU.DU};
- VHSUBW.{H.B/W.H/D.W/Q.D/HU.BU/WU.HU/DU.WU/QU.DU}.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230504122810.4094787-9-gaosong@loongson.cn>
Song Gao [Thu, 4 May 2023 12:27:33 +0000 (20:27 +0800)]
target/loongarch: Implement vsadd/vssub
This patch includes:
- VSADD.{B/H/W/D}[U];
- VSSUB.{B/H/W/D}[U].
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230504122810.4094787-8-gaosong@loongson.cn>
Song Gao [Thu, 4 May 2023 12:27:32 +0000 (20:27 +0800)]
target/loongarch: Implement vneg
This patch includes;
- VNEG.{B/H/W/D}.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230504122810.4094787-7-gaosong@loongson.cn>
Song Gao [Thu, 4 May 2023 12:27:31 +0000 (20:27 +0800)]
target/loongarch: Implement vaddi/vsubi
This patch includes:
- VADDI.{B/H/W/D}U;
- VSUBI.{B/H/W/D}U.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230504122810.4094787-6-gaosong@loongson.cn>
Song Gao [Thu, 4 May 2023 12:27:30 +0000 (20:27 +0800)]
target/loongarch: Implement vadd/vsub
This patch includes:
- VADD.{B/H/W/D/Q};
- VSUB.{B/H/W/D/Q}.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230504122810.4094787-5-gaosong@loongson.cn>
Song Gao [Thu, 4 May 2023 12:27:29 +0000 (20:27 +0800)]
target/loongarch: Add CHECK_SXE maccro for check LSX enable
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230504122810.4094787-4-gaosong@loongson.cn>
Song Gao [Thu, 4 May 2023 12:27:28 +0000 (20:27 +0800)]
target/loongarch: meson.build support build LSX
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230504122810.4094787-3-gaosong@loongson.cn>
Song Gao [Thu, 4 May 2023 12:27:27 +0000 (20:27 +0800)]
target/loongarch: Add LSX data type VReg
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230504122810.4094787-2-gaosong@loongson.cn>
Merge tag 'pull-ppc-20230505' of https://gitlab.com/danielhb/qemu into staging
ppc patch queue for 2023-05-05:
This queue includes fixes for ppc and spapr emulation, a build fix for
the pseries machine and a new reviewer for ppc/spapr.
We're also carrying a Coverity fix for the sm501 display.
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# =iwNT
# -----END PGP SIGNATURE-----
# gpg: Signature made Fri 05 May 2023 05:26:00 PM BST
# gpg: using EDDSA key 17EBFF9923D01800AF2838193CD9CA96DE033164
# gpg: issuer "danielhb413@gmail.com"
# gpg: Good signature from "Daniel Henrique Barboza <danielhb413@gmail.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 17EB FF99 23D0 1800 AF28 3819 3CD9 CA96 DE03 3164
* tag 'pull-ppc-20230505' of https://gitlab.com/danielhb/qemu:
hw/ppc/Kconfig: NVDIMM is a hard requirement for the pseries machine
tests: tcg: ppc64: Add tests for Vector Extract Mask Instructions
tcg: ppc64: Fix mask generation for vextractdm
MAINTAINERS: Adding myself in the list for ppc/spapr
ppc: spapr: cleanup cr get/set with helpers.
hw/display/sm501: Remove unneeded increment from loop
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
In this series:
- fix block_bitmap_mapping (juan)
- RDMA cleanup (juan)
- qemu file cleanup (juan)
Please apply.
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# =79n1
# -----END PGP SIGNATURE-----
# gpg: Signature made Fri 05 May 2023 01:47:17 AM BST
# gpg: using RSA key 1899FF8EDEBF58CCEE034B82F487EF185872D723
# gpg: Good signature from "Juan Quintela <quintela@redhat.com>" [undefined]
# gpg: aka "Juan Quintela <quintela@trasno.org>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 1899 FF8E DEBF 58CC EE03 4B82 F487 EF18 5872 D723
* tag 'migration-20230505-pull-request' of https://gitlab.com/juan.quintela/qemu:
qemu-file: Make ram_control_save_page() use accessors for rate_limit
qemu-file: Make total_transferred an uint64_t
qemu-file: remove shutdown member
qemu-file: No need to check for shutdown in qemu_file_rate_limit
migration: qemu_file_total_transferred() function is monotonic
migration: max_postcopy_bandwidth is a size parameter
migration/rdma: Check for postcopy sooner
migration/rdma: It makes no sense to recive that flag without RDMA
migration/rdma: We can calculate the rioc from the QEMUFile
migration/rdma: simplify ram_control_load_hook()
migration: Make RAM_SAVE_FLAG_HOOK a normal case entry
migration: Rename xbzrle_enabled xbzrle_started
migration: Put zero_pages in alphabetical order
migration: Document all migration_stats
migration/rdma: Don't pass the QIOChannelRDMA as an opaque
migration: Fix block_bitmap_mapping migration
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
While the old type was correct in the ideal sense, some ABIs require
the argument to be zero-extended. Using uint32_t for all such values
is a decent compromise.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Unify all computation of argument stack offset in one function.
This requires that we adjust ref_slot to be in the same units,
by adding max_reg_slots during init_call_layout.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
tcg/sparc64: Drop is_64 test from tcg_out_qemu_ld data return
In tcg_canonicalize_memop, we remove MO_SIGN from MO_32 operations
with TCG_TYPE_I32. Thus this is never set. We already have an
identical test just above which does not include is_64
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
tcg/riscv: Rationalize args to tcg_out_qemu_{ld,st}
Interpret the variable argument placement in the caller. Pass data_type
instead of is64 -- there are several places where we already convert back
from bool to type. Clean things up by using type throughout.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
The port currently does not support "oversize" guests, which
means riscv32 can only target 32-bit guests. We will soon be
building TCG once for all guests. This implies that we can
only support riscv64.
Since all Linux distributions target riscv64 not riscv32,
this is not much of a restriction and simplifies the code.
The brcond2 and setcond2 opcodes are exclusive to 32-bit hosts,
so we can and should remove the stubs.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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