ARM: dts: r8a7794: Add missing clock for secondary CA7 CPU core
Currently only the primary CPU in the CA7 cluster has a clocks property,
while the secondary CPU core is driven by the same clock.
Add the missing clocks property to fix this.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
ARM: dts: r8a7793: Add missing clock for secondary CA15 CPU core
Currently only the primary CPU in the CA15 cluster has a clocks
property, while the secondary CPU core is driven by the same clock.
Add the missing clocks property to fix this.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
ARM: dts: r8a7792: Add missing clock for secondary CA15 CPU core
Currently only the primary CPU in the CA15 cluster has a clocks
property, while the secondary CPU core is driven by the same clock.
Add the missing clocks property to fix this.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
ARM: dts: r8a7791: Add missing clock for secondary CA15 CPU core
Currently only the primary CPU in the CA15 cluster has a clocks
property, while the secondary CPU core is driven by the same clock.
Add the missing clocks property to fix this.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Currently only the CPU cores in the CA15 cluster have clocks properties.
Add the missing clocks properties for the CPU cores in the CA7 cluster
to fix this.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
ARM: dts: r8a7790: Add missing clocks for secondary CA15 CPU cores
Currently only the primary CPU in the CA15 cluster has a clocks
property, while the secondary CPU cores are driven by the same clock.
Add the missing clocks properties to fix this.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
ARM: dts: r8a7743: Add missing clock for secondary CA15 CPU core
Currently only the primary CPU in the CA15 cluster has a clocks
property, while the secondary CPU core is driven by the same clock.
Add the missing clocks property to fix this.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Chris Paterson <chris.paterson2@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Improve hardware description by adding a clocks property to the device
node corresponding to the primary CA15 CPU core, which is for now the
only one described.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Simon Horman [Fri, 13 Oct 2017 12:33:09 +0000 (14:33 +0200)]
ARM: dts: r8a7794: Use R-Car GPIO Gen2 fallback compat string
Use newly added R-Car GPIO Gen2 fallback compat string
in place of now deprecated non-generation specific
R-Car GPIO fallback compat string in the DT of the r8a7794 SoC.
This should have no run-time effect as the driver matches against
the per-SoC compat string before considering the fallback compat string.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Simon Horman [Fri, 13 Oct 2017 12:33:08 +0000 (14:33 +0200)]
ARM: dts: r8a7793: Use R-Car GPIO Gen2 fallback compat string
Use newly added R-Car GPIO Gen2 fallback compat string
in place of now deprecated non-generation specific
R-Car GPIO fallback compat string in the DT of the r8a7793 SoC.
This should have no run-time effect as the driver matches against
the per-SoC compat string before considering the fallback compat string.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Simon Horman [Fri, 13 Oct 2017 12:33:07 +0000 (14:33 +0200)]
ARM: dts: r8a7792: Use R-Car GPIO Gen2 fallback compat string
Use newly added R-Car GPIO Gen2 fallback compat string
in place of now deprecated non-generation specific
R-Car GPIO fallback compat string in the DT of the r8a7792 SoC.
This should have no run-time effect as the driver matches against
the per-SoC compat string before considering the fallback compat string.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Simon Horman [Fri, 13 Oct 2017 12:33:06 +0000 (14:33 +0200)]
ARM: dts: r8a7791: Use R-Car GPIO Gen2 fallback compat string
Use newly added R-Car GPIO Gen2 fallback compat string
in place of now deprecated non-generation specific
R-Car GPIO fallback compat string in the DT of the r8a7791 SoC.
This should have no run-time effect as the driver matches against
the per-SoC compat string before considering the fallback compat string.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Simon Horman [Fri, 13 Oct 2017 12:33:05 +0000 (14:33 +0200)]
ARM: dts: r8a7790: Use R-Car GPIO Gen2 fallback compat string
Use newly added R-Car GPIO Gen2 fallback compat string
in place of now deprecated non-generation specific
R-Car GPIO fallback compat string in the DT of the r8a7790 SoC.
This should have no run-time effect as the driver matches against
the per-SoC compat string before considering the fallback compat string.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Simon Horman [Fri, 13 Oct 2017 12:33:04 +0000 (14:33 +0200)]
ARM: dts: r8a7743: Use R-Car GPIO Gen2 fallback compat string
Use newly added R-Car GPIO Gen2 fallback compat string
in place of now deprecated non-generation specific
R-Car GPIO fallback compat string in the DT of the r8a7743 SoC.
This should have no run-time effect as the driver matches against
the per-SoC compat string before considering the fallback compat string.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Simon Horman [Fri, 13 Oct 2017 12:33:03 +0000 (14:33 +0200)]
ARM: dts: r8a7779: Use R-Car GPIO Gen1 fallback compat string
Use newly added R-Car GPIO Gen1 fallback compat string
in place of now deprecated non-generation specific
R-Car GPIO fallback compat string in DT of r8a7779 SoC.
As the driver does not match on "renesas,gpio-r8a7779" there
are some run-time considerations for this patch:
* When a resulting DTB is used with kernels newer than v4.14 this should
not have any run-time effect as renesas,rcar-gen1-gpio is matched by the
driver since commit dbd1dad2ab8f ("gpio: rcar: add gen[123] fallback
compatibility strings")
* However, when used with older kernels GPIO will be disabled as
no compat string match will be made by the driver.
The regression documented above for the new DTB with old kernel case
is acceptable in my opinion.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Simon Horman [Fri, 13 Oct 2017 12:33:02 +0000 (14:33 +0200)]
ARM: dts: r8a7778: Use R-Car GPIO Gen1 fallback compat string
Use newly added R-Car GPIO Gen1 fallback compat string
in place of now deprecated non-generation specific
R-Car GPIO fallback compat string in DT of r8a7778 SoC.
As the driver does not match on "renesas,gpio-r8a7778" there
are some run-time considerations for this patch:
* When a resulting DTB is used with kernels newer than v4.14 this should
not have any run-time effect as renesas,rcar-gen1-gpio is matched by the
driver since commit dbd1dad2ab8f ("gpio: rcar: add gen[123] fallback
compatibility strings")
* However, when used with older kernels GPIO will be disabled as
no compat string match will be made by the driver.
The regression documented above for the new DTB with old kernel case
is acceptable in my opinion.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Jacopo Mondi [Mon, 9 Oct 2017 08:48:35 +0000 (10:48 +0200)]
ARM: dts: gr-peach: Enable ostm0 and ostm1 timers
Enable ostm0 and ostm1 timers to be used as clock source and clockevent
source. The timers provides greater accuracy than the already enabled
mtu2 one.
With these enabled:
clocksource: ostm: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 57352151442 ns
sched_clock: 32 bits at 33MHz, resolution 30ns, wraps every 64440619504ns
ostm: used for clocksource
ostm: used for clock events
Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Suggested-by: Chris Brandt <chris.brandt@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Biju Das [Wed, 11 Oct 2017 09:04:33 +0000 (10:04 +0100)]
ARM: dts: iwg20d-q7: Enable HS-USB
Enable HS-USB device for the iWave G20D-Q7 carrier board based on
RZ/G1M.
Also disable the host mode support on usb otg port by default to avoid
pin conflicts.
Signed-off-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Chris Paterson <chris.paterson2@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Dietmar Eggemann [Wed, 30 Aug 2017 14:41:20 +0000 (15:41 +0100)]
ARM: dts: r8a7790: add cpu capacity-dmips-mhz information
The following 'capacity-dmips-mhz' dt property values are used:
Cortex-A15: 1024, Cortex-A7: 539
They have been derived form the cpu_efficiency values:
Cortex-A15: 3891, Cortex-A7: 2048
by scaling them so that the Cortex-A15s (big cores) use 1024.
The cpu_efficiency values were originally derived from the "Big.LITTLE
Processing with ARM Cortex™-A15 & Cortex-A7" white paper
(http://www.cl.cam.ac.uk/~rdm34/big.LITTLE.pdf). Table 1 lists 1.9x
(3891/2048) as the Cortex-A15 vs Cortex-A7 performance ratio for the
Dhrystone benchmark.
The following platform is affected once cpu-invariant accounting
support is re-connected to the task scheduler:
r8a7790-lager
Signed-off-by: Dietmar Eggemann <dietmar.eggemann@arm.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Fabrizio Castro [Fri, 6 Oct 2017 17:59:53 +0000 (18:59 +0100)]
ARM: dts: iwg20d-q7-dbcm-ca: Add device trees for camera DB
This patch adds a .dtsi that describes the camera daughter board
and a .dts to describe the HW made of iWave's RZ/G1M SoM, iWave's
RZ/G1M/G1N Qseven carrier board, and the camera daughter board.
The camera daughter board .dtsi adds support for ttySC[14].
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Chris Paterson <chris.paterson2@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Fabrizio Castro [Fri, 6 Oct 2017 17:59:52 +0000 (18:59 +0100)]
ARM: dts: iwg20d-q7: Rework DT architecture
Since the same carrier board may host RZ/G1M and RZ/G1N based
Systems on Module, the DT architecture for iwg20d-q7 needs
better decoupling. This patch provides:
* iwg20d-q7-common.dtsi - its purpose is to define the carrier
board definitions, and its content is basically the same
as the previous version of r8a7743-iwg20d-q7.dts, only it
has no reference to the SoM .dtsi, and that's why the
filename doesn't mention the SoC name any more.
* r8a7743-iwg20d-q7.dts - its new purpose is to put together
the SoM .dtsi (r8a7743-iwg20m.dtsi) and the carrier board
.dtsi defined by this very patch, along with "model" and
"compatible" properties.
The final DT architecture to describe the board is now:
r8a7743-iwg20d-q7.dts # Carrier Board + SoM
├── r8a7743-iwg20m.dtsi # SoM
│  └── r8a7743.dtsi # SoC
└── iwg20d-q7-common.dtsi # Carrier Board
and maximizes the reuse of the definitions for the carrier board
and for the SoM.
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Chris Paterson <chris.paterson2@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Jacopo Mondi [Thu, 5 Oct 2017 08:58:19 +0000 (10:58 +0200)]
ARM: dts: gr-peach: Enable MTU2 timer pulse unit
MTU2 multi-function/multi-channel timer/counter is not enabled for
GR-Peach board. The timer is used as clock event source to schedule
wake-ups, and without this enabled all sleeps not performed through busy
waiting hang the board.
Add properties to describe the reset topology for on-SoC devices:
- Add the "#reset-cells" property to the CPG/MSSR device node,
- Add resets and reset-names properties to the various device nodes.
This allows to reset SoC devices using the Reset Controller API.
Note that resets usually match the corresponding module clocks.
Exceptions are:
- The audio module has resets for the Serial Sound Interfaces only,
- The display module has only a single reset for all DU channels, but
adding reset properties for the display is postponed.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add properties to describe the reset topology for on-SoC devices:
- Add the "#reset-cells" property to the CPG/MSSR device node,
- Add resets and reset-names properties to the various device nodes.
This allows to reset SoC devices using the Reset Controller API.
Note that resets usually match the corresponding module clocks.
Exceptions are:
- The audio module has resets for the Serial Sound Interfaces only,
- The display module has only a single reset for all DU channels, but
adding reset properties for the display is postponed.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add properties to describe the reset topology for on-SoC devices:
- Add the "#reset-cells" property to the CPG/MSSR device node,
- Add resets and reset-names properties to the various device nodes.
This allows to reset SoC devices using the Reset Controller API.
Note that resets usually match the corresponding module clocks.
Exceptions are:
- The audio module has resets for the Serial Sound Interfaces only,
but audio is not yet enabled in r8a7792.dtsi,
- The display module has only a single reset for all DU channels, but
adding reset properties for the display is postponed.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add properties to describe the reset topology for on-SoC devices:
- Add the "#reset-cells" property to the CPG/MSSR device node,
- Add resets and reset-names properties to the various device nodes.
This allows to reset SoC devices using the Reset Controller API.
Note that resets usually match the corresponding module clocks.
Exceptions are:
- The audio module has resets for the Serial Sound Interfaces only,
- The display module has only a single reset for all DU channels, but
adding reset properties for the display is postponed.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add properties to describe the reset topology for on-SoC devices:
- Add the "#reset-cells" property to the CPG/MSSR device node,
- Add resets and reset-names properties to the various device nodes.
This allows to reset SoC devices using the Reset Controller API.
Note that resets usually match the corresponding module clocks.
Exceptions are:
- The audio module has resets for the Serial Sound Interfaces only,
- The display module has only a single reset for all DU channels, but
adding reset properties for the display is postponed.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Biju Das [Wed, 6 Sep 2017 13:52:06 +0000 (14:52 +0100)]
ARM: dts: r8a7743: Add IIC cores to dtsi
Signed-off-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Chris Paterson <chris.paterson2@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Biju Das [Wed, 30 Aug 2017 15:17:14 +0000 (16:17 +0100)]
ARM: dts: iwg22d-sodimm: Add Ethernet AVB support
Define the iWave RainboW-G22D board dependent part of the Ethernet
AVB device node.
On some older versions of the platform (before R4.0) the phy address
may be 1 or 3. The address is fixed to 3 for R4.0 onwards (which
will be the first mainstream release), hence using 3 in the dts.
Signed-off-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Chris Paterson <chris.paterson2@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Biju Das [Tue, 29 Aug 2017 09:56:23 +0000 (10:56 +0100)]
ARM: dts: iwg20d-q7: Add RTC support
Define the iWave RainboW-G20D-Qseven board dependent part of the
RTC device node.
Signed-off-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Chris Paterson <chris.paterson2@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
ARM: dts: r8a7791: Convert to new CPG/MSSR bindings
Convert the R-Car M2-W SoC from the old "Renesas R-Car Gen2 Clock Pulse
Generator (CPG)", "Renesas CPG DIV6 Clock", and "Renesas CPG Module Stop
(MSTP) Clocks" DT bindings to the new unified "Renesas Clock Pulse
Generator / Module Standby and Software Reset" DT bindings.
This simplifies the DTS files, and allows to add support for reset
control later.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Biju Das [Mon, 14 Aug 2017 11:49:49 +0000 (12:49 +0100)]
ARM: dts: iwg20d-q7: Add SDHI1 support
Define the iWave RainboW-G20D-Qseven board dependent part of the
SDHI1 device node.
Signed-off-by: Biju Das <biju.das@bp.renesas.com> Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Biju Das [Mon, 14 Aug 2017 11:49:48 +0000 (12:49 +0100)]
ARM: dts: iwg20m: Enable SDHI0 controller
Enable the SDHI0 controller on iWave RZG1M Qseven SOM.
Signed-off-by: Biju Das <biju.das@bp.renesas.com> Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
ARM: dts: r8a7794: Convert to new CPG/MSSR bindings
Convert the R-Car E2 SoC from the old "Renesas R-Car Gen2 Clock Pulse
Generator (CPG)", "Renesas CPG DIV6 Clock", and "Renesas CPG Module Stop
(MSTP) Clocks" DT bindings to the new unified "Renesas Clock Pulse
Generator / Module Standby and Software Reset" DT bindings.
This simplifies the DTS files, and allows to add support for reset
control later.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
ARM: dts: r8a7793: Convert to new CPG/MSSR bindings
Convert the R-Car M2-N SoC from the old "Renesas R-Car Gen2 Clock Pulse
Generator (CPG)", "Renesas CPG DIV6 Clock", and "Renesas CPG Module Stop
(MSTP) Clocks" DT bindings to the new unified "Renesas Clock Pulse
Generator / Module Standby and Software Reset" DT bindings.
This simplifies the DTS files, and allows to add support for reset
control later.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
ARM: dts: r8a7792: Convert to new CPG/MSSR bindings
Convert the R-Car V2H SoC from the old "Renesas R-Car Gen2 Clock Pulse
Generator (CPG)" and "Renesas CPG Module Stop (MSTP) Clocks" DT bindings
to the new unified "Renesas Clock Pulse Generator / Module Standby and
Software Reset" DT bindings.
This simplifies the DTS files, and allows to add support for reset
control later.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
ARM: dts: r8a7790: Convert to new CPG/MSSR bindings
Convert the R-Car H2 SoC from the old "Renesas R-Car Gen2 Clock Pulse
Generator (CPG)", "Renesas CPG DIV6 Clock", and "Renesas CPG Module Stop
(MSTP) Clocks" DT bindings to the new unified "Renesas Clock Pulse
Generator / Module Standby and Software Reset" DT bindings.
This simplifies the DTS files, and allows to add support for reset
control later.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Merge tag 'upstream-4.14-rc1' of git://git.infradead.org/linux-ubifs
Pull UBI updates from Richard Weinberger:
"Minor improvements"
* tag 'upstream-4.14-rc1' of git://git.infradead.org/linux-ubifs:
UBI: Fix two typos in comments
ubi: fastmap: fix spelling mistake: "invalidiate" -> "invalidate"
ubi: pr_err() strings should end with newlines
ubi: pr_err() strings should end with newlines
ubi: pr_err() strings should end with newlines
Merge branch 'for-linus-4.14-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rw/uml
Pull UML updates from Richard Weinberger:
- minor improvements
- fixes for Debian's new gcc defaults (pie enabled by default)
- fixes for XSTATE/XSAVE to make UML work again on modern systems
* 'for-linus-4.14-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rw/uml:
um: return negative in tuntap_open_tramp()
um: remove a stray tab
um: Use relative modversions with LD_SCRIPT_DYN
um: link vmlinux with -no-pie
um: Fix CONFIG_GCOV for modules.
Fix minor typos and grammar in UML start_up help
um: defconfig: Cleanup from old Kconfig options
um: Fix FP register size for XSTATE/XSAVE
1) Fix hotplug deadlock in hv_netvsc, from Stephen Hemminger.
2) Fix double-free in rmnet driver, from Dan Carpenter.
3) INET connection socket layer can double put request sockets, fix
from Eric Dumazet.
4) Don't match collect metadata-mode tunnels if the device is down,
from Haishuang Yan.
5) Do not perform TSO6/GSO on ipv6 packets with extensions headers in
be2net driver, from Suresh Reddy.
6) Fix scaling error in gen_estimator, from Eric Dumazet.
7) Fix 64-bit statistics deadlock in systemport driver, from Florian
Fainelli.
8) Fix use-after-free in sctp_sock_dump, from Xin Long.
9) Reject invalid BPF_END instructions in verifier, from Edward Cree.
* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net: (43 commits)
mlxsw: spectrum_router: Only handle IPv4 and IPv6 events
Documentation: link in networking docs
tcp: fix data delivery rate
bpf/verifier: reject BPF_ALU64|BPF_END
sctp: do not mark sk dumped when inet_sctp_diag_fill returns err
sctp: fix an use-after-free issue in sctp_sock_dump
netvsc: increase default receive buffer size
tcp: update skb->skb_mstamp more carefully
net: ipv4: fix l3slave check for index returned in IP_PKTINFO
net: smsc911x: Quieten netif during suspend
net: systemport: Fix 64-bit stats deadlock
net: vrf: avoid gcc-4.6 warning
qed: remove unnecessary call to memset
tg3: clean up redundant initialization of tnapi
tls: make tls_sw_free_resources static
sctp: potential read out of bounds in sctp_ulpevent_type_enabled()
MAINTAINERS: review Renesas DT bindings as well
net_sched: gen_estimator: fix scaling error in bytes/packets samples
nfp: wait for the NSP resource to appear on boot
nfp: wait for board state before talking to the NSP
...
Commit 5620a0d1aac ("firmware: delete in-kernel firmware") removed the
entire firmware directory. Unfortunately it thereby also removed the
support for built-in firmware.
This restores the ability to build firmware directly into the kernel by
pruning the original Makefile to the necessary minimum. The default for
EXTRA_FIRMWARE_DIR is now the standard directory /lib/firmware/.
mlxsw: spectrum_router: Only handle IPv4 and IPv6 events
The driver doesn't support events from address families other than IPv4
and IPv6, so ignore them. Otherwise, we risk queueing a work item before
it's initialized.
This can happen in case a VRF is configured when MROUTE_MULTIPLE_TABLES
is enabled, as the VRF driver will try to add an l3mdev rule for the
IPMR family.
Fixes: 65e65ec137f4 ("mlxsw: spectrum_router: Don't ignore IPv6 notifications") Signed-off-by: Ido Schimmel <idosch@mellanox.com> Reported-by: Andreas Rammhold <andreas@rammhold.de> Reported-by: Florian Klink <flokli@flokli.de> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Eric Dumazet [Fri, 15 Sep 2017 23:47:42 +0000 (16:47 -0700)]
tcp: fix data delivery rate
Now skb->mstamp_skb is updated later, we also need to call
tcp_rate_skb_sent() after the update is done.
Fixes: 8c72c65b426b ("tcp: update skb->skb_mstamp more carefully") Signed-off-by: Eric Dumazet <edumazet@google.com> Acked-by: Soheil Hassas Yeganeh <soheil@google.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Merge branch '4.14-features' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS updates from Ralf Baechle:
"This is the main pull request for 4.14 for MIPS; below a summary of
the non-merge commits:
CM:
- Rename mips_cm_base to mips_gcr_base
- Specify register size when generating accessors
- Use BIT/GENMASK for register fields, order & drop shifts
- Add cluster & block args to mips_cm_lock_other()
CPC:
- Use common CPS accessor generation macros
- Use BIT/GENMASK for register fields, order & drop shifts
- Introduce register modify (set/clear/change) accessors
- Use change_*, set_* & clear_* where appropriate
- Add CM/CPC 3.5 register definitions
- Use GlobalNumber macros rather than magic numbers
- Have asm/mips-cps.h include CM & CPC headers
- Cluster support for topology functions
- Detect CPUs in secondary clusters
CPS:
- Read GIC_VL_IDENT directly, not via irqchip driver
DMA:
- Consolidate coherent and non-coherent dma_alloc code
- Don't use dma_cache_sync to implement fd_cacheflush
FPU emulation / FP assist code:
- Another series of 14 commits fixing corner cases such as NaN
propgagation and other special input values.
- Zero bits 32-63 of the result for a CLASS.D instruction.
- Enhanced statics via debugfs
- Do not use bools for arithmetic. GCC 7.1 moans about this.
- Correct user fault_addr type
Generic MIPS:
- Enhancement of stack backtraces
- Cleanup from non-existing options
- Handle non word sized instructions when examining frame
- Fix detection and decoding of ADDIUSP instruction
- Fix decoding of SWSP16 instruction
- Refactor handling of stack pointer in get_frame_info
- Remove unreachable code from force_fcr31_sig()
- Convert to using %pOF instead of full_name
- Remove the R6000 support.
- Move FP code from *_switch.S to *_fpu.S
- Remove unused ST_OFF from r2300_switch.S
- Allow platform to specify multiple its.S files
- Add #includes to various files to ensure code builds reliable and
without warning..
- Remove __invalidate_kernel_vmap_range
- Remove plat_timer_setup
- Declare various variables & functions static
- Abstract CPU core & VP(E) ID access through accessor functions
- Store core & VP IDs in GlobalNumber-style variable
- Unify checks for sibling CPUs
- Add CPU cluster number accessors
- Prevent direct use of generic_defconfig
- Make CONFIG_MIPS_MT_SMP default y
- Add __ioread64_copy
- Remove unnecessary inclusions of linux/irqchip/mips-gic.h
GIC:
- Introduce asm/mips-gic.h with accessor functions
- Use new GIC accessor functions in mips-gic-timer
- Remove counter access functions from irq-mips-gic.c
- Remove gic_read_local_vp_id() from irq-mips-gic.c
- Simplify shared interrupt pending/mask reads in irq-mips-gic.c
- Simplify gic_local_irq_domain_map() in irq-mips-gic.c
- Drop gic_(re)set_mask() functions in irq-mips-gic.c
- Remove gic_set_polarity(), gic_set_trigger(), gic_set_dual_edge(),
gic_map_to_pin() and gic_map_to_vpe() from irq-mips-gic.c.
- Convert remaining shared reg access, local int mask access and
remaining local reg access to new accessors
- Move GIC_LOCAL_INT_* to asm/mips-gic.h
- Remove GIC_CPU_INT* macros from irq-mips-gic.c
- Move various definitions to the driver
- Remove gic_get_usm_range()
- Remove __gic_irq_dispatch() forward declaration
- Remove gic_init()
- Use mips_gic_present() in place of gic_present and remove
gic_present
- Move gic_get_c0_*_int() to asm/mips-gic.h
- Remove linux/irqchip/mips-gic.h
- Inline __gic_init()
- Inline gic_basic_init()
- Make pcpu_masks a per-cpu variable
- Use pcpu_masks to avoid reading GIC_SH_MASK*
- Clean up mti, reserved-cpu-vectors handling
- Use cpumask_first_and() in gic_set_affinity()
- Let the core set struct irq_common_data affinity
microMIPS:
- Fix microMIPS stack unwinding on big endian systems
MIPS-GIC:
- SYNC after enabling GIC region
NUMA:
- Remove the unused parent_node() macro
R6:
- Constify r2_decoder_tables
- Add accessor & bit definitions for GlobalNumber
SMP:
- Constify smp ops
- Allow boot_secondary SMP op to return errors
VDSO:
- Drop gic_get_usm_range() usage
- Avoid use of linux/irqchip/mips-gic.h
Platform changes:
Alchemy:
- Add devboard machine type to cpuinfo
- update cpu feature overrides
- Threaded carddetect irqs for devboards
CI20:
- Enable GPIO and RTC drivers in defconfig
- Add ethernet and fixed-regulator nodes to DTS
Generic platform:
- Move Boston and NI 169445 FIT image source to their own files
- Include asm/bootinfo.h for plat_fdt_relocated()
- Include asm/time.h for get_c0_*_int()
- Include asm/bootinfo.h for plat_fdt_relocated()
- Include asm/time.h for get_c0_*_int()
- Allow filtering enabled boards by requirements
- Don't explicitly disable CONFIG_USB_SUPPORT
- Bump default NR_CPUS to 16
JZ4700:
- Probe the jz4740-rtc driver from devicetree
Lantiq:
- Drop check of boot select from the spi-falcon driver.
- Drop check of boot select from the lantiq-flash MTD driver.
- Access boot cause register in the watchdog driver through regmap
- Add device tree binding documentation for the watchdog driver
- Add docs for the RCU DT bindings.
- Convert the fpi bus driver to a platform_driver
- Remove ltq_reset_cause() and ltq_boot_select(
- Switch to a proper reset driver
- Switch to a new drivers/soc GPHY driver
- Add an USB PHY driver for the Lantiq SoCs using the RCU module
- Use of_platform_default_populate instead of __dt_register_buses
- Enable MFD_SYSCON to be able to use it for the RCU MFD
- Replace ltq_boot_select() with dummy implementation.
Loongson 2F:
- Allow NULL clock for clk_get_rate
Malta:
- Use new GIC accessor functions
NI 169445:
- Add support for NI 169445 board.
- Only include in 32r2el kernels
Octeon:
- Add support for watchdog of 78XX SOCs.
- Add support for watchdog of CN68XX SOCs.
- Expose support for mips32r1, mips32r2 and mips64r1
- Enable more drivers in config file
- Add support for accessing the boot vector.
- Remove old boot vector code from watchdog driver
- Define watchdog registers for 70xx, 73xx, 78xx, F75xx.
- Make CSR functions node aware.
- Allow access to CIU3 IRQ domains.
- Misc cleanups in the watchdog driver
Omega2+:
- New board, add support and defconfig
Pistachio:
- Enable Root FS on NFS in defconfig
Ralink:
- Add Mediatek MT7628A SoC
- Allow NULL clock for clk_get_rate
- Explicitly request exclusive reset control in the pci-mt7620 PCI driver.
SEAD3:
- Only include in 32 bit kernels by default
VoCore:
- Add VoCore as a vendor t0 dt-bindings
- Add defconfig file"
* '4.14-features' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (167 commits)
MIPS: Refactor handling of stack pointer in get_frame_info
MIPS: Stacktrace: Fix microMIPS stack unwinding on big endian systems
MIPS: microMIPS: Fix decoding of swsp16 instruction
MIPS: microMIPS: Fix decoding of addiusp instruction
MIPS: microMIPS: Fix detection of addiusp instruction
MIPS: Handle non word sized instructions when examining frame
MIPS: ralink: allow NULL clock for clk_get_rate
MIPS: Loongson 2F: allow NULL clock for clk_get_rate
MIPS: BCM63XX: allow NULL clock for clk_get_rate
MIPS: AR7: allow NULL clock for clk_get_rate
MIPS: BCM63XX: fix ENETDMA_6345_MAXBURST_REG offset
mips: Save all registers when saving the frame
MIPS: Add DWARF unwinding to assembly
MIPS: Make SAVE_SOME more standard
MIPS: Fix issues in backtraces
MIPS: jz4780: DTS: Probe the jz4740-rtc driver from devicetree
MIPS: Ci20: Enable RTC driver
watchdog: octeon-wdt: Add support for 78XX SOCs.
watchdog: octeon-wdt: Add support for cn68XX SOCs.
watchdog: octeon-wdt: File cleaning.
...