Chunming Zhou [Tue, 9 May 2017 05:39:40 +0000 (13:39 +0800)]
drm/amdgpu: fix dependency issue
The problem is that executing the jobs in the right order doesn't give you the right result
because consecutive jobs executed on the same engine are pipelined.
In other words job B does it buffer read before job A has written it's result.
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 5 May 2017 14:26:12 +0000 (10:26 -0400)]
drm/amdgpu/soc15: use atomfirmware for setting bios scratch for reset
Need to use the atomfirmware interface rather than atombios since
soc15 is atomfirmware based.
Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 5 May 2017 14:21:36 +0000 (10:21 -0400)]
drm/amdgpu/atomfirmware: add function to update engine hang status
Update the scratch reg for when the engine is hung.
Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Julien Isorce <jisorce@oblong.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Guenter Roeck [Thu, 4 May 2017 06:49:18 +0000 (23:49 -0700)]
drm/amdgpu: Use less generic enum definitions
alpha:allmodconfig fails to build as follows.
drivers/gpu/drm/amd/amdgpu/amdgpu.h:1006:2: error:
expected identifier before '(' token
drivers/gpu/drm/amd/amdgpu/amdgpu.h:1011:28: error:
'NGG_BUF_MAX' undeclared here
The problem is not really the enum definition of NGG_BUF_MAX but PARAM,
which happens to be defined differently for alpha and a couple of other
architectures.
Use less generic defines for NGG enums to solve the problem.
Fixes: bce23e00f3369 ("drm/amdgpu: add NGG parameters") Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Thu, 4 May 2017 03:07:02 +0000 (11:07 +0800)]
drm/amd/powerplay: disable engine spread spectrum feature on Vega10.
Vega10 atomfirmware do not have ASIC_InternalSS_Info table
so disable this feature by default in driver.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Ken Wang <Qingqing.wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Mon, 1 May 2017 08:15:31 +0000 (16:15 +0800)]
drm/amdgpu:fix waiting on dirty fence
if bo->shadow is NULL (race issue:BO shadow was just released
and gpu-reset kick in but BO hasn't yet) recover_vram_from_shadow
won't set @next, so the following "fence=next"
will wrongly use a fence pointer which may already dirty.
fixing it by set next to NULL prior to recover_vram_from_shadow
Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Chunming Zhou<david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Thu, 27 Apr 2017 09:14:57 +0000 (17:14 +0800)]
drm/amdgpu:PTE flag should be 64 bit width
otherwise we'll lost the high 32 bit for pte, which lead
to incorrect MTYPE for vega10.
Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Tue, 2 May 2017 08:51:49 +0000 (16:51 +0800)]
drm/amd/powerplay: set soc floor voltage on boot on vega10.
Send the VBIOS bootup VDDC as a SOC floor voltage to SMU
before populating the PPTABLE. After DPM is enabled, This
floor voltage will be removed. This will prevent SMC from
going to Vmin upon receiving PPTable causing a violation.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Shaoyun Liu [Fri, 28 Apr 2017 20:14:59 +0000 (16:14 -0400)]
drm/amdgpu: Reserve 0-2 invalidation reg sets for none-amdgpu usages
Firmware used reg set 2 for tlb invalidation. AMDGPU can start from reg
set 3 to avoid the conflict. AMDKFD will use the reg set 0 or 1 when
necesary.
Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com> Reviewws-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
The purpose of the refactor was for amdgpu_crtc_prepare/submit_flip to
be used by the DC code, but that's no longer the case.
Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Michel Dänzer [Fri, 28 Apr 2017 08:28:14 +0000 (17:28 +0900)]
drm/amdgpu: Make amdgpu_bo_reserve use uninterruptible waits for cleanup
Some of these paths probably cannot be interrupted by a signal anyway.
Those that can would fail to clean up things if they actually got
interrupted.
Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: fix deadlock of reservation between cs and gpu reset v2
the case could happen when gpu reset:
1. when gpu reset, cs can be continue until sw queue is full, then push job will wait with holding pd reservation.
2. gpu_reset routine will also need pd reservation to restore page table from their shadow.
3. cs is waiting for gpu_reset complete, but gpu reset is waiting for cs releases reservation.
v2: handle amdgpu_cs_submit error path.
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by: Monk Liu <monk.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
v2: 64-bit aligned for gpu info
v3: squash in wave_front_fix
Signed-off-by: Ken Wang <Qingqing.Wang@amd.com> Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Qiang Yu <Qiang.Yu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Thu, 27 Apr 2017 15:13:39 +0000 (17:13 +0200)]
drm/amdgpu: remove unused and mostly unimplemented CGS functions v2
Those functions are all unused and some not even implemented.
v2: keep cgs_get_pci_resource, it is used by the ACP driver.
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Xie [Tue, 25 Apr 2017 21:09:24 +0000 (17:09 -0400)]
drm/amdgpu: Fix use of interruptible waiting
There is no good mechanism to handle the corresponding error.
When signal interrupt happens, unpin is not called.
As a result, inside AMDGPU, the statistic of pin size will be wrong.
Signed-off-by: Alex Xie <AlexBin.Xie@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Xie [Wed, 26 Apr 2017 17:31:01 +0000 (13:31 -0400)]
drm/amdgpu: Fix use of interruptible waiting
Either in cgs functions or for callers of cgs functions:
1. The signal interrupt can affect the expected behaviour
2. There is no good mechanism to handle the corresponding error
3. There is no chance of deadlock in these single BO waiting
4. There is no clear benefit for interruptible waiting
5. Future caller of these functions might have same issue.
Signed-off-by: Alex Xie <AlexBin.Xie@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
if the job is reset twice, then the parent could be NULL.
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: validate shadow before restoring from it
Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Roger.He <Hongbo.He@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Xie [Mon, 24 Apr 2017 19:33:16 +0000 (15:33 -0400)]
drm/amdgpu: Fix use of interruptible waiting
1. The signal interrupt can affect the expected behaviour.
2. There is no good mechanism to handle the corresponding error.
When signal interrupt happens, unpin is not called.
As a result, inside AMDGPU, the statistic of pin size will be wrong.
Signed-off-by: Alex Xie <AlexBin.Xie@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Xie [Mon, 24 Apr 2017 19:26:57 +0000 (15:26 -0400)]
drm/amdgpu: Real return value can be over-written when clean up
Signed-off-by: Alex Xie <AlexBin.Xie@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Xie [Mon, 24 Apr 2017 18:27:00 +0000 (14:27 -0400)]
drm/amdgpu: Fix use of interruptible waiting
1. The signal interrupt can affect the expected behaviour.
2. There is no good mechanism to handle the corresponding error.
Signed-off-by: Alex Xie <AlexBin.Xie@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Xie [Mon, 24 Apr 2017 17:53:04 +0000 (13:53 -0400)]
drm/amdgpu: Fix use of interruptible waiting
1. The signal interrupt can affect the expected behaviour.
2. There is no good mechanism to handle the corresponding error.
Signed-off-by: Alex Xie <AlexBin.Xie@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Xie [Mon, 24 Apr 2017 17:52:41 +0000 (13:52 -0400)]
drm/amdgpu: Fix use of interruptible waiting
1. The signal interrupt can affect the expected behaviour.
2. There is no mechanism to handle the corresponding error.
Signed-off-by: Alex Xie <AlexBin.Xie@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Xie [Mon, 24 Apr 2017 17:30:43 +0000 (13:30 -0400)]
drm/amdgpu: Fix use of interruptible waiting
If amdgpu_bo_reserve function is interrupted by signal,
amdgpu_bo_kunmap function is not called.
Signed-off-by: Alex Xie <AlexBin.Xie@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Mario Kleiner [Sun, 23 Apr 2017 23:33:09 +0000 (01:33 +0200)]
drm/radeon: Make display watermark calculations more accurate
Avoid big roundoff errors in scanline/hactive durations for
high pixel clocks, especially for >= 500 Mhz, and thereby
program more accurate display fifo watermarks.
This is a port of the corresponding amdgpu patch.
Implemented for DCE 4,6,8.
Tested on Evergreen/DCE-4 with Radeon HD-5770.
Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Mario Kleiner [Sun, 23 Apr 2017 23:33:08 +0000 (01:33 +0200)]
drm/radeon: Avoid overflows/divide-by-zero in latency_watermark calculations.
At dot clocks > approx. 250 Mhz, some of these calcs will overflow and
cause miscalculation of latency watermarks, and for some overflows also
divide-by-zero driver crash. Make calcs more overflow resistant.
This is a direct port of the corresponding patch from amdgpu-kms,
copy-paste for cik from dce-8 and si from dce-6, with a slightly
simpler variant for evergreen dce-4/5.
Only tested on DCE-4 evergreen with a Radeon HD-5770.
Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Mario Kleiner [Sun, 23 Apr 2017 23:02:46 +0000 (01:02 +0200)]
drm/amdgpu: Add missing lb_vblank_lead_lines setup to DCE-6 path.
This apparently got lost when implementing the new DCE-6 support
and would cause failures in pageflip scheduling and timestamping.
Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Pan Bian [Mon, 24 Apr 2017 08:45:51 +0000 (16:45 +0800)]
drm/radeon: check return value of radeon_fence_emit
Function radeon_fence_emit() returns -ENOMEM if there is no enough
memory. And in this case, function radeon_ring_unlock_undo() rather than
function radeon_ring_unlock_commit() should be called. However, in
function radeon_test_create_and_emit_fence(), the return value of
radeon_fence_emit() is ignored. This patch adds the check.
Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Pan Bian <bianpan2016@163.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Pan Bian [Mon, 24 Apr 2017 08:38:05 +0000 (16:38 +0800)]
drm/radeon: check return value of radeon_ring_lock
Function radeon_ring_lock() returns an errno on failure, and its return
value should be validated. However, in functions r420_cp_errata_init()
and r420_cp_errata_fini(), its return value is not checked. This patch
adds the checks.
Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Pan Bian <bianpan2016@163.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Frank Min [Mon, 17 Apr 2017 03:19:45 +0000 (11:19 +0800)]
drm/amdgpu/soc15: enable UVD code path for sriov
Enable UVD block for SRIOV.
Signed-off-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Frank Min [Mon, 17 Apr 2017 03:51:44 +0000 (11:51 +0800)]
drm/amdgpu/uvd7: add UVD hw init sequences for sriov
Add UVD hw init.
Signed-off-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Frank Min [Mon, 17 Apr 2017 03:45:35 +0000 (11:45 +0800)]
drm/amdgpu/uvd7: add uvd doorbell initialization for sriov
Add UVD doorbell for SRIOV.
Signed-off-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Frank Min [Sun, 16 Apr 2017 05:37:07 +0000 (13:37 +0800)]
drm/amdgpu/vce4: move mm table constructions functions into mmsch header file
Move mm table construction functions into mmsch header file so that
UVD can reuse it.
Signed-off-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Daniel Wang [Wed, 19 Apr 2017 08:09:08 +0000 (16:09 +0800)]
drm/amdgpu/vce4: fix a PSP loading VCE issue
Fixed PSP loading issue for sriov.
Signed-off-by: Daniel Wang <Daniel.Wang2@amd.com> Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Daniel Wang [Thu, 20 Apr 2017 03:45:09 +0000 (11:45 +0800)]
drm/amdgpu/psp: skip loading SDMA/RLCG under SRIOV VF
Now GPU hypervisor will load SDMA and RLCG ucode, so skip it
in guest.
Signed-off-by: Daniel Wang <Daniel.Wang2@amd.com> Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
The root cause is some ring doesn't have scheduler, like KIQ ring
Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[ 132.036658] amdgpu 0000:22:00.0: VM IB without ID
[ 132.036709] [drm:amdgpu_job_run [amdgpu]] *ERROR* Error scheduling IBs (-22)
[ 132.036755] [drm:amd_sched_main [amdgpu]] *ERROR* Failed to run job!
root cause is fence is signaled during sync transfer.
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Fri, 21 Apr 2017 08:05:56 +0000 (10:05 +0200)]
drm/amdgpu: fix VM clearing in amdgpu_gem_object_close
We need to check if the VM is swapped out before trying to update it.
Fixes: 23e0563e48f7 ("drm/amdgpu: clear freed mappings immediately when BO may be freed") Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add gtt print like vram when dump mm table V2
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Thu, 20 Apr 2017 10:11:47 +0000 (12:11 +0200)]
drm/amdgpu: fix amdgpu_ttm_bo_eviction_valuable
BOs not mapped into the GART are always valuable for an eviction. Otherwise we
don't correctly swap them out on VRAM evictions during memory pressure.
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/powerplay: add error message to remind user updating firmware
Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Zhang, Jerry [Wed, 19 Apr 2017 01:53:29 +0000 (09:53 +0800)]
drm/amdgpu: PRT support for gfx9 (v3)
Fix PRT handling on gfx9
v2: unify PRT bit for all ASICs
v3: move PRT flag checking in amdgpu_vm_bo_split_mapping()
Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> Acked-by: David Zhou <david1.zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Wed, 19 Apr 2017 12:41:19 +0000 (14:41 +0200)]
drm/amdgpu: fix amdgpu_vm_clear_freed v2
Use amdgpu_vm_bo_update_mapping() instead of amdgpu_vm_bo_split_mapping() here.
We don't want any flags set in the cleared areas and splitting
shouldn't be necessary.
v2: fix typo in commit message
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
Fix issue that PSP initialization will fail if reload amdgpu module.
That's because the PSP ring must be destroyed to be ready for the
next time PSP initialization.
Changes in v2:
- Move psp_ring_destroy before all BOs free (suggested by
Ray Huang).
Changes in v3:
- Check firmware load type, if it is not PSP, we should do
nothing in fw_fini(), and of course will not destroy
PSP ring too (suggested by Ray Huang).
Signed-off-by: Trigger Huang <trigger.huang@amd.com> Reviewed-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Wed, 12 Apr 2017 09:34:26 +0000 (17:34 +0800)]
drm/amdgpu: update smu9 driver interface
Updated interface between the driver and the SMU controller.
Signed-off-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tom St Denis [Wed, 19 Apr 2017 15:03:04 +0000 (11:03 -0400)]
drm/amd/amdgpu: Print out ring name in dev_info
So it's more obvious which rings are using which INV engines.
Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tom St Denis [Wed, 19 Apr 2017 13:02:41 +0000 (09:02 -0400)]
drm/amd/amdgpu: Change comp GFXv9 ring name to remove space
umr expects the ring name to be a complete word. This also
makes it consistent with GFXv7/8.
Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tom St Denis [Wed, 19 Apr 2017 13:01:42 +0000 (09:01 -0400)]
drm/amd/amdgpu: Change comp GFXv6 ring name to remove space
umr expects the ring name to be a complete word. This also
makes it consistent with GFXv7/8.
Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Tue, 18 Apr 2017 11:21:44 +0000 (19:21 +0800)]
drm/amdgpu: fix memory clock can't switch on CI.
if we set only lowest mclk level enabled,
when we enable uvd dpm during boot time,
mclk will be fixed in the lowest level.
the mclk switch will fail if try to enable
other level of mclk at this time.
so set all mclk levels enabled.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Mon, 6 Mar 2017 12:34:57 +0000 (13:34 +0100)]
drm/amdgpu: fix coding style and printing in amdgpu_doorbell_init
Based on commit "drm/radeon: remove useless and potentially wrong message".
The size of the info printing is incorrect and the PCI subsystems prints
the same info on boot anyway.
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Pixel Ding [Thu, 23 Feb 2017 03:10:33 +0000 (11:10 +0800)]
drm/amdgpu/virt: don't check VALID bit for FLR completion message
The interrupt after FLR is missed sometimes due to hardware reason, so
guest driver get the notification of FLR completion via polling
message. Then host doesn't write VALID bit to avoid sending interrupt,
otherwise the completion will be handled twice.
So there's a valid message without VALID bit for FLR completion,
driver should handle it without checking.
drm/amdgpu: fix dead lock if any ip block resume failed in s3
Driver must free the console lock whether driver resuming successful
or not. Otherwise, fb_console will be always waiting for the lock and
then cause system stuck.
Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
projects / mirror_ubuntu-eoan-kernel.git / log