drm/amdgpu/mes10.1: add mes firmware info fields

The newly added fields is to store mes firmware related information.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amdgpu/ucode: add mes firmware file support

The newly added firmware struct is for mes firmware file.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amdgpu/ucode: add the definitions of MES ucode and ucode data

MES requires two seperate firmwares: ucode and ucode data.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amdgpu/sdma5: incorrect variable type for gpu address

Incorrect programming with 64bit gpu address assignment for
32bit variable.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amdgpu/sdma5: fix a sdma potential hang in VK_Examples test

[why]
When page fault happens, it could lead to sdma hang is RESP_MODE =
0 for non-PRT case.

[how]
Setting  SDMAx_UTCL1_CNTL.RESP_MODE to 0b011 to avoid SDMA halt.

Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: tiancyin <tianci.yin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amd/powerplay: remove uvd_gated/vce_gated from smu_power_context (v2)

It's not needed for navi.

v2: remove unused variable (Alex)

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amdgpu/nv: set vcn pg flag

Enable VCN power gating by default.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amdgpu: enable vcn dpm scheme for navi

On navi1x, vcn dpm scheme was merged into powergating scheme.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amdgpu/vcn2: don't access register when power gated

It will cause bus hang to access register UVD_STATUS
when VCN is in the state of power gated.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amd/powerplay: add new interface for vcn powergating

add new interface for vcn powrergating and vcn dpm as well.

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amd/powerplay: enable vcn powergating v2

enable vcn powergating in driver for navi10

v2: set vcn pg bit according to AMD_PG_SUPPORT_VCN flag

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amdgpu/vcn2: notify SMU power up/down VCN

For sw control power gating, it needs notify SMU to power up/down VCN
when enter/exit working state.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amdgpu/gfx10: fix issues for suspend/resume

1). use PREEMPT_QUEUE instead of RESET_QUEUE for gfx ring disablement.
2). Need wait for unmapping queue done before continue execution.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Tianci Yin <tianci.yin@amd.com>
Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amd/powerplay: set dpm_enabled flag but don't enable vcn dpm

This patch sets dpm_enabled flag but don't enable vcn dpm, because vcn dpm
doesn't work so far and we needs to enable the sysfs interfaces.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amd/powerplay: update smu11_driver_if_navi10.h

update the smu11_driver_if_navi10.h since navi10 smu fw
update to 42.15.0

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amdgpu/gfx10: fix resume failure when enabling async gfx ring

'adev->in_suspend' code path is missing in gfx_v10_0_gfx_init_queue()

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amdgpu: disable some gfx light sleep

temporarily disable to avoid s3 test failure.

s3 test failure log:
"[drm:amdgpu_job_timedout [amdgpu]] *ERROR* ring sdma0 timeout,
signaled seq=8278, emitted seq=8281"

Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Tianci Yin <tianci.yin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amdgpu/gfx10: update gfx golden settings

add new registers: mmCGTT_SPI_CLK_CTRL, mmDB_DEBUG3 and
mmGL2C_CGTT_SCLK_CTRL.

Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Tianci Yin <tianci.yin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amd/powerplay: do not set dpm_enabled flag before VCN/DCN DPM is workable

This dpm_enabled flag will be recognized as the VCN DPM enabled as well. In fact
VCN/DCN DPM on Navi10 is not good so far, so we cannot enable it for now.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amd/powerplay: fix the incorrect type of pptable

This patch is to fix the incorrect type of pptable, otherwise, the data will be
totally wrong in parsing phase.

Signed-off-by: Kenneth Feng <Kenneth.Feng@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amd/powerplay: don't include the smu11 driver if header in smu v11 (v2)

This header is actually for each asic, so we should not include in smu_v11_0.c.
And rename the one for navi10.

v2: add hack for XGMI (Alex)

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amd/powerplay: move getting MAX_FAN_RPM value to asic level

Getting MAX_FAN_RPM value needs to be read by pptable, so it should be moved to
asic level.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amd/powerplay: introduce smu power source type to handle AC/DC source for each asic

This patch introduces new smu power source type, it's to handle the different
AC/DC source defines for each asic with the same smu ip.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amd/powerplay: move Watermarks_t uses into asic level

This patch moves the rest of Watermarks_t uses into asic level. It's to avoid
the conflicts with different asic.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amd/powerplay: move SmuMetrics_t uses into asic level

This patch moves the rest of SmuMetrics_t uses into asic level. It's to avoid the
conflicts with different asic.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amd/powerplay: move PPTable_t uses into asic level

This patch moves the rest of PPTable_t uses into asic level. It's to avoid the
conflicts with different asic.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amd/powerplay: use the table size member in the structure instead of getting directly

This patch uses the table size member in the structure instead of getting
directly, because the table is different in each asic.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amd/powerplay: modify smu_update_table to use SMU_TABLE_xxx as the input

Table id may be different for each asic, so it's good to use this as the input
for common interface.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amd/powerplay/smu11: remove smu_update_table_with_arg

Nothing was using it.  Just replace with smu_update_table
which is what everything was using via a wrapper anyway.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amd/powerplay: add tables_init interface for each asic

The smc tables defines should be in the asic level.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amd/powerplay: init table_count for smu tables on asic level

TABLE_COUNT should be inited in asic level. Because the value may be different
on each asic even on the same ip.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amd/powerplay: introduce smu table id type to handle the smu table for each asic

This patch introduces new smu table type, it's to handle the different smu table
defines for each asic with the same smu ip.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amd/powerplay: introduce smu feature type to handle feature mask for each asic

This patch introduces new smu feature type, it's to handle the different feature
mask defines for each asic with the same smu ip.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amd/powerplay: introduce smu clk type to handle ppclk for each asic

This patch introduces new smu clk type, it's to handle the different ppclk
defines for each asic with the same smu ip.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amdgpu: enable sw smu driver for navi10 by default

Navi10 will use sw smu driver for dynamic power managment,
while vega20 could also use sw smu driver when amdgpu_dpm is
set to 2

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amd/powerplay: enable DCEFCLK dpm support

Enabale DCEFCLK dpm on navi10

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amd/powerplay: gfxoff-seperate the Vega20 case

seperate the Vega20 case from navi10 for gfxoff so that gfxoff
won't be allowed on Vega20

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amd/amdgpu: fw version check with gfxoff

1. check the firmware version when enabling gfxoff
2. overwrite the pptable to make sure gfxoff is really
enabled on navi10

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amd: add gfxoff support on navi10

add the gfxoff interface to navi10,it's disabled by default.

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amd/powerplay: add allowed feature mask for navi10

add smu feature mask:
1.FEATURE_DPM_PREFETCHER_BIT
2.FEATURE_DPM_PREFETCHER_BIT
3.FEATURE_ATHUB_PG

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amd/powerplay: optimization feature mask function for asic

1.change function return value type: from "unallowed" to "allowed"
2.replace feature mask number with feature macro, the code will clear.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amd/powerplay: remove duplicate code from smu hw init

remove duplicate code (un-used) in smu

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amd/powerplay: implement smc firmware v2.1 for smu11

1.add smc_firmware_header_v2_1 hfirmware support, support more pptable in smc firmware.
2.optimization current pptable load framework.
3.rename read_pptable_from_vbios with setup_pptable.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amd/powerplay: add smu11 smu_if_version check for navi10

add smu11 fw version check for navi10

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amd/powerplay: move the function of is_dpm_running to asic file

the function os is_dpm_running is aisc related function,
so move them to asic file.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amd/powerplay: move the function of read_sensor to asic file

The read_sensor functions has asic related parts code,
so move them to asic file to implement.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amd/powerplay: move the function of uvd&vce dpm to asic file

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amd/powerplay: move the function of get[set]_power_profile to asic file

The callback of get[set]_power_profile is asic related function,
so move theme into vega20_ppt file.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amd/powerplay: move the funciton of conv_profile_to_workload to asic file

the function of conv_profile_to_workload is asic related function,
so move them into vega20_ppt file

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amd/powerplay: enable power features

the below smu related power features can be enabled now.
1.Prefetcher
2.GFX DPM
3.SOCCLK DPM
4.MP0CLK DPM
5.LCLK DPM
6.GFX ULV
7.CG
8.PPT
9.TDC
10.GFX EDC
11.VR0HOT
12.Fan Control
13.Thermal Control
14.LED Display
15.MMHub PG
16.ATHub PG

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amd/powerplay: skip od feature on navi10 for the moment

OD feature isn't enabled on navi10 so skip it for the moment.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amd/powerplay: modify the feature mask to enable gfx/soc dpm

So far, the gfx/soc dpm is enabled with feature mask set.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amd/powerplay: introduce the function to load the soft pptable for navi10 (v2)

Driver is able to load soft pptable from smc bin file with this function. We
stored the soft pptable in the bottom of smc.bin that the version is v2.

v2: remove is_fw_v2_0 flag.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amd/powerplay: smu needs to be initialized after rlc in direct mode

For gfx 10, rlc firmware loading relies on smu firmware is loaded firstly, so in
direct type, it has to load smc ucode here before rlc. And meanwhile, the smu
initialization has to move after rlc, otherwise, smu message will get failure
during the handshake with rlc and smu.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amdgpu: fix the issue of checking on message mapping

The navi10_message_map[index] scope should be in PPSMC_Message_Count not in
SMU_MSG_MAX_COUNT.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amdgpu: bump smc firmware header version to v2 (v2)

This patch bumps smc firmware header version to v2 for storing soft pptable.

v2: fix the typo, and add prints for v2 header

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amd/powerplay: update smu11 driver if header for navi10 (v2)

This patch updates smu11 driver if header for navi10 to match 42.09.00 smu
firmware.

v2: clean up comments

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amd/powerplay: enable backdoor smu fw loading (v2)

enable backdoor smu fw loading on navi10

v2: squash in define fix (Alex)

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amd/powerplay: move bootup value before read pptable from vbios

In navi10, we need read the pp_table_id from bootup value, then decide whether
use load the soft pptable.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amd/powerplay: add navi10 smc ucode init and navi10 ppt functions setting

This patch adds navi10 smc ucode init and ppt functions setting.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amd/powerplay: set smu v11 funcs for navi10

Naiv10 also uses smu v11 functions.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amd/powerplay: introduce the navi10 pptable implementation

This patch introduces the navi10 pptable implementation, so far it is already
has firmware loading, pptable side loading, writing back to smc, and feature
mask enabling.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amd/powerplay: fix the mp/smuio header for navi10

SMU11 should use mp11 and smuio11 headers.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amd/powerplay: update smu 11 driver if header for navi10

This patch updates smu 11 driver if header for navi10.

UVD/VCE won't be used for navi10. Here, reverve them for vega20.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amd/powerplay: update smu v11 ppsmc header

This patch updates smu v11 ppsmc header for navi10.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amdgpu: add to set navi ip blocks

Set the IPs for navi10 in early_init like other asics.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amdgpu: add Navi10 pci ids

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amdkfd: Add navi10 support to amdkfd. (v3)

KFD (kernel fusion driver) is the kernel driver
for the compute backend for usermode compute
stack.

v2: squash in updates (Alex)
v3: squash in rebase fixes (Alex)

Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
Signed-off-by: Philip Cox <Philip.Cox@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amdgpu: update golden setting programming logic

Since from soc15, make sure only AndMasked bit get changed
when applied or_mask

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amdgpu: Add navi10 kfd support for amdgpu (v3)

KFD (Kernel Fusion Driver) is the compute backend driver
for AMD GPUs.

v2: squash in updates (Alex)
v3: fix warnings (Alex)

Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
Signed-off-by: Philip Cox <Philip.Cox@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amdgpu: add navi10 common ip block (v3)

This adds the core SOC code for navi asics.

v1: add place holder and initial basic function (Ray)
v2: add new introduced functions to avoid reference
    NULL pointer (Hawking)
v3L squash in updates (Alex)

Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amdgpu: avoid to use SOC15_REG_OFFSET in static array for navi10

Move to the header file.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amdgpu: add gfx v10 implementation (v10)

GFX is the graphics and compute block on the GPU.

v1: add initial gfx v10 implementation (Ray)
v2: convert to new get_vm_pde function in emit_vm_flush (Hawking)
v3: switch to new emit ib interfaces (Hawking)
v4: squash in updates (Alex)
v5: remove unused variables (Alex)
v6: v6: some golden regs moved to vbios (Alex)
v7: squash in some cleanups (Alex)
v8: squash in golden settings update (Alex)
v9: squash in whitespace fixes (Ernst Sjöstrand, Alex)
v10: squash in GDS backup size fix and GDS/GWS/OA removal rebase fixes (Hawking)

Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amdgpu/mes10.1: add ip block mes10.1 (v2)

MES takes over the scheduling capability of GFX and SDMA,
add MES as a standalone ip.

v2: squash in updates (Alex)

Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amdgpu/mes: enable mes on navi10 and later asic

When amdgpu_mes is enabled and asic family is navi10 and
later asic, enable mes per device.

Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amdgpu/mes: add definitions of ip callback function

Abstract mes ip independent function layer.

Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amdgpu/mes: add mes header file and definition

Add dummy header file and definitions of mes.

Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amdgpu/mes: add amdgpu_mes driver parameter

amdgpu_mes, which is a driver scope parameter, is used
to whether enable mes or not.

MES (Micro Engine Scheduler) is the new on chip hw scheduling
microcontroller.  It can be used to handle queue scheduling and
preemption and priorities.

Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amdgpu: add initial VCN2.0 support (v2)

VCN (Video Core Next) is the video encode/decode block.

Porting over the same functions from VCN1.0

v2: squash in updates (Alex)

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amdgpu: add JPEG2.0 decode ring ib test

Add internal register offset for registers involving in ib tests

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amdgpu: add JPEG2.0 decode ring test

Use register from JPEG tile, the UVD tile reg won't work for JPEG

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amdgpu: add VCN2.0 decode ib test

Add internal register offset for registers involving in ib tests

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amdgpu: add VCN2.0 decode ring test

Add internal register offset for registers involving in ring tests

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amdgpu: add Navi10 VCN firmware support

Add Navi10 to VCN family

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amdgpu: add initial support for sdma v5.0 (v6)

SDMA (System DMA) is a general purpose DMA engine usable
by UMDs for transfers or the kernel for paging or GPUVM
updates.

v1: support basic funcitonalites includes rb, ib, vm,
    copy buffer and trap irq
v2: convert to use new get_vm_pde in emit_vm_flush
v3: retire amdgpu_ttm_set_active_vram_size from sdma v5
v4: retire the redundant hdp_invalidate implementation
v5: squash in updates
v6: some golden regs moved to vbios

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amdgpu: set the default value of pa_sc_tile_steering_override

So userspace can access it.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amdgpu: add pa_sc_tile_steering_override to drm_amdgpu_info_device

the initial/default value of pa_sc_tile_steering_override need to
be exposed to user mode driver

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amdgpu: disable concurrent flushes for Navi10 v2

Navi10 have a bug in the SDMA which can theoretically cause memory
corruption with concurrent VMID flushes

v2: explicitely check Navi10

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amdgpu/discovery: refactor ip list traversal

for each ip, check whether it is needed by amdgpu driver,
if yes, record its base addresses

v2: change some DRM_INFO to DRM_DEBUG
v3: remove unused variable (Alex)

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amdgpu/discovery: add module param for ip discovery enablement

to control enablement.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amdgpu/discovery: stop converting the units of base addresses

the unit is already in dword

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amdgpu/discovery: update definition for struct die_header

Update to latest spec.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amdgpu/discovery: stop taking psp header into account

psp will write a header to vram, but the value exposed in
RCC_CONFIG_MEMSIZE does not include the memory that this header is
written to. Therefore, the interpretation of the table does not need to
take the psp header into account.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amdgpu/discovery: fix hwid for nbio

Properly set this.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amdgpu/discovery: use hardcoded mmRCC_CONFIG_MEMSIZE

register base offset of nbio is not known before IP Discovery table is
parsed, so hardcode this value.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amdgpu/discovery: add harvest info data table

Add support for the harvest tables.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amdgpu/discovery: update definitions of table_info and binary_header

Use the proper definitions.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amdgpu/discovery: fix calculations of some gfx info

fix gfx info table handling.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amdgpu/discovery: add ip discovery initial support

The IP discovery table lists is populated by the psp at power on
and includes all of the hw details on the board:
- List of IPs and MMIO offsets
- IP harvest details
- IP configuration details

v2: prefix struct and function names with 'amdgpu'
v3: read table binary from vram using mmMM_INDEX and mmMM_DATA
    update TABLE_BINARY_MAX_SIZE to 64kb (1 TMR)
    add 'instance_number' field per ip info
    consider endianness and replace uint8/16/32_t with u8/16/32
    initialize register base addresses
    initialize adev->gfx.config and adev->gfx.cu_info to replace gpu info fw
    get major and minor version using a single api
    don't expose internal data structures in amdgpu_discovery.h
v4: RCC_CONFIG_MEMSIZE is in MB units
    hold mmio_idx_lock while reading ip discovery binary
v5: pick out discovery.h as a cross-OS header
    do structure pointer cast directly
    consider endianness while using the member of structure
    convert base addresses to dword

at boot up, PSP BL copies ip discovery binary from VBIOS(SPIROM) image to the
top of the frame buffer (just below the reserved regions for PSP & SMU).

ip discovery data table includes the collection of each ip's identification
number, base addresses, version number, and harvest setting placeholder.

gc data table includes gfx info structure.

Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drm/amdgpu: mark the partial job as preempted in mcbp unit test

In mcbp unit test, the test should detect the preempted job which may
be a partial execution ib and mark it as preempted; so that the gfx
block can correctly generate PM4 frame.

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>