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6 years agodrm/amd/display: update dml to match DV dml
Dmytro Laktyushkin [Thu, 28 Jun 2018 15:31:13 +0000 (11:31 -0400)]
drm/amd/display: update dml to match DV dml

DV updated their dml with an option to use max vstartup,
this updates dc dml with the same option

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amd/display: add max scl ratio to soc bounding box
Dmytro Laktyushkin [Thu, 28 Jun 2018 16:28:00 +0000 (12:28 -0400)]
drm/amd/display: add max scl ratio to soc bounding box

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amd/display: Fix new stream count check in dc_add_stream_to_ctx
Ken Chalmers [Wed, 27 Jun 2018 16:48:21 +0000 (12:48 -0400)]
drm/amd/display: Fix new stream count check in dc_add_stream_to_ctx

[Why]
The previous code could allow through attempts to enable more streams
than there are timing generators, in designs where the number of pipes
is greater than the number of timing generators.

[How]
Compare the new stream count to the resource pool's timing generator
count, instead of its pipe count.  Also correct a typo in the error
message.

Signed-off-by: Ken Chalmers <ken.chalmers@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amd/display: dp debugfs allow link rate lane count greater than dp rx reported...
Hersen Wu [Wed, 27 Jun 2018 17:03:04 +0000 (13:03 -0400)]
drm/amd/display: dp debugfs allow link rate lane count greater than dp rx reported caps

[Why]
when hw team does phy parameters tuning, there is need to force dp
link rate or lane count grater than the values from dp receiver to
check dp tx. current debufs limit link rate, lane count no more
than rx caps.

[How] remove force settings less than rx caps check

v2: Fix typo in title

Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amd/display: Expose couple OPTC functions through header
David Francis [Wed, 27 Jun 2018 19:55:57 +0000 (15:55 -0400)]
drm/amd/display: Expose couple OPTC functions through header

Signed-off-by: David Francis <David.Francis@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amd/display: Add CRC support for DCN
David Francis [Tue, 26 Jun 2018 18:58:15 +0000 (14:58 -0400)]
drm/amd/display: Add CRC support for DCN

[Why]
Regamma/CTM tests require CRC support

[How]
The CRC registers that were used in DCE exist under different
names in DCN.  The code was copied from DCE (in
dc/dce110/dce110_timing_generator.c) into DCN, and changed to
use the DCN register access helper functions.

Signed-off-by: David Francis <David.Francis@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amd/display: Return out_link_loss from interrupt handler
Fatemeh Darbehani [Tue, 26 Jun 2018 20:40:55 +0000 (16:40 -0400)]
drm/amd/display: Return out_link_loss from interrupt handler

Signed-off-by: Fatemeh Darbehani <fatemeh.darbehani@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amd/display: Add NULL check for local sink in edp_power_control
Yue Hin Lau [Wed, 27 Jun 2018 17:49:20 +0000 (13:49 -0400)]
drm/amd/display: Add NULL check for local sink in edp_power_control

[WHY]
PNP cause bsod regression fix

[HOW]
Add NULL check

Signed-off-by: Yue Hin Lau <Yuehin.Lau@amd.com>
Reviewed-by: Hugo Hu <Hugo.Hu@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amd/display: add pp to dc powerlevel enum translator
Mikita Lipski [Tue, 26 Jun 2018 13:52:29 +0000 (09:52 -0400)]
drm/amd/display: add pp to dc powerlevel enum translator

[why]
Add a switch statement to translate pp's powerlevel enum
to dc powerlevel statement enum
[how]
Add a translator function

Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
Reviewed-by: Sun peng Li <Sunpeng.Li@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amd/display: add DalEnableHDMI20 key support
Charlene Liu [Tue, 26 Jun 2018 22:49:32 +0000 (18:49 -0400)]
drm/amd/display: add DalEnableHDMI20 key support

[why]
"DalEnableHDMI20" set to 0, disallow HDMI YCbCr420 and  pixel clock > 340Mhz
Default is enabled.

Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amd/display: introduce concept of send_reset_length for i2c engines
Charlene Liu [Mon, 25 Jun 2018 23:28:54 +0000 (19:28 -0400)]
drm/amd/display: introduce concept of send_reset_length for i2c engines

Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amd/display: Read AUX channel even if only status byte is returned
Leo (Sunpeng) Li [Tue, 26 Jun 2018 14:50:16 +0000 (10:50 -0400)]
drm/amd/display: Read AUX channel even if only status byte is returned

[Why]
get_channel_status() can return 0 in returned_bytes, and report a
successful operation result. This is because it prunes the first status
byte out. This was preventing read_channel_reply() from being called
(due to the faulty condition), and consequently preventing the AUX
reply status from being set.

[How]
Fix the conditional so that it accounts for when get_channel_status()
returns 0 bytes read.

[Fixes]
Fixes possible edid read failures during S3 resume, where we are now
relying on DRM's DP AUX handling. This was an regression introduced by:

    Author: Harry Wentland <harry.wentland@amd.com>
        drm/amd/display: Return aux replies directly to DRM

Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amd/display: Right shift AUX reply value sooner than later
Leo (Sunpeng) Li [Tue, 26 Jun 2018 14:44:05 +0000 (10:44 -0400)]
drm/amd/display: Right shift AUX reply value sooner than later

[Why]
There is no point in keeping the AUX reply value in the raw format as
returned from reading the AUX_SW_DATA register.

[How]
Shift it within read_channel_reply(), where the register is read, before
returning it.

Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amd/display: Expose bunch of functions from dcn10_hw_sequencer
Eric Bernstein [Wed, 16 May 2018 20:19:50 +0000 (16:19 -0400)]
drm/amd/display: Expose bunch of functions from dcn10_hw_sequencer

v2: Remove spurious newline changes

Signed-off-by: Eric Bernstein <eric.bernstein@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amd/display: Add YCbCr420 only support for HDMI 4K@60
Jerry (Fangzhi) Zuo [Fri, 22 Jun 2018 21:12:47 +0000 (17:12 -0400)]
drm/amd/display: Add YCbCr420 only support for HDMI 4K@60

[Why]
Some monitors mark 4K@60 capable HDMI port only have 300MHz TMDS
maximum, but the edid includes 4K@60 mode in cea extension block.

[How]
To enable 4K@60, need to limit BW by allowing YCbCr420 ONLY mode.
Add YCbCr420 only support for monitors that do not fully support
HDMI2.0, e.g., ASUS PA328. The YCbCr420 only support applies to
DCN, DCE112 or higher.

Signed-off-by: Jerry (Fangzhi) Zuo <Jerry.Zuo@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amd/display: dal 3.1.54
Tony Cheng [Tue, 5 Jun 2018 13:15:15 +0000 (09:15 -0400)]
drm/amd/display: dal 3.1.54

Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amd/display: Linux hook test pattern through debufs
Hersen Wu [Fri, 22 Jun 2018 17:06:01 +0000 (13:06 -0400)]
drm/amd/display: Linux hook test pattern through debufs

bug fix: phy test PLTAT is special 80bit test pattern. The 80bit
data should be hard coded within driver so that user does not
need input the deata. previous driver does not have hard coded
80 bits pattern data for PLTPAT. Other than this PLTPAT, user
has to input 80 bits pattern data. In case user input less than
10 bytes data, un-input data byte will be filled by 0x00.

Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amd/display: expose dcn10_aux_initialize in header
Yongqiang Sun [Sun, 24 Jun 2018 16:18:54 +0000 (00:18 +0800)]
drm/amd/display: expose dcn10_aux_initialize in header

Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amd/display: add dcn cursor hotsport rotation and mirror support
Dmytro Laktyushkin [Thu, 21 Jun 2018 17:33:41 +0000 (13:33 -0400)]
drm/amd/display: add dcn cursor hotsport rotation and mirror support

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amd/display: set default GPIO_ID_HPD
Charlene Liu [Fri, 22 Jun 2018 01:32:36 +0000 (21:32 -0400)]
drm/amd/display: set default GPIO_ID_HPD

Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amd/display: add missing mask for dcn
Charlene Liu [Thu, 21 Jun 2018 21:57:51 +0000 (17:57 -0400)]
drm/amd/display: add missing mask for dcn

Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Reviewed-by: Duke Du <Duke.Du@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amd/display: Fix compile error on older GCC versions
Leo (Sunpeng) Li [Mon, 18 Jun 2018 16:23:03 +0000 (12:23 -0400)]
drm/amd/display: Fix compile error on older GCC versions

GCC 4.9 reports a 'missing braces around initializer' error. This is a
bug, documented here:

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=53119

Fix it by adding another brace.

Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com>
Reviewed-by: Mikita Lipski <Mikita.Lipski@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amd/display: Linux set/read lane settings through debugfs
Hersen Wu [Fri, 15 Jun 2018 14:32:50 +0000 (10:32 -0400)]
drm/amd/display: Linux set/read lane settings through debugfs

 function: get current DP PHY settings: voltage swing, pre-emphasis,
 post-cursor2 (defined by VESA DP specification)

 valid values:  voltage swing: 0,1,2,3  pre-emphasis : 0,1,2,3
 post cursor2 : 0,1,2,3

 debugfs file phy_setings is located at  /sys/kernel/debug/dri/0/DP-x

 there will be directories, like DP-1, DP-2,DP-3, etc. for DP display

 --- to figure out which DP-x is the display for DP to be check,
 cd DP-x
 ls -ll
 There should be debugfs file, like link_settings, phy_settings.
 cat link_settings
 from lane_count, link_rate to figure which DP-x is for display to be
 worked on

 --- to get current DP PHY settings,
 cat phy_settings

 --- to change DP PHY settings,
 echo <voltage_swing> <pre-emphasis> <post_cursor2> > phy_settings

 for examle, to change voltage swing to 2, pre-emphasis to 3,
 post_cursor2 to 0,
 echo 2 3 0 > phy_settings

 ---  to check if change be applied, get current phy settings by
 cat phy_settings

 ---  in case invalid values are set by user, like
 echo 1 4 0 > phy_settings

 HW will NOT be programmed by these settings.

cat phy_settings will show the previous valid settings.

Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amd/display: Patch for extend time to panel poweron.
Hugo Hu [Fri, 15 Jun 2018 19:49:55 +0000 (15:49 -0400)]
drm/amd/display: Patch for extend time to panel poweron.

[WHY]
In eDP spec, the min duration in LCDVDD on-off-on sequence should be
500ms, some BOE panels need 700ms to pass.
[HOW]
Add patch to wait more time when eDP power on.

Signed-off-by: Hugo Hu <hugo.hu@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amd/display: add additional info for cursor position programming
Dmytro Laktyushkin [Tue, 19 Jun 2018 19:49:02 +0000 (15:49 -0400)]
drm/amd/display: add additional info for cursor position programming

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amd/display: drop unused register defines
Dmytro Laktyushkin [Wed, 20 Jun 2018 15:40:15 +0000 (11:40 -0400)]
drm/amd/display: drop unused register defines

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amd/display: remove dentist_vco_freq from resource_pool
Dmytro Laktyushkin [Wed, 13 Jun 2018 17:52:53 +0000 (13:52 -0400)]
drm/amd/display: remove dentist_vco_freq from resource_pool

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amd/display: hook dp test pattern through debugfs
Hersen Wu [Tue, 19 Jun 2018 16:14:29 +0000 (12:14 -0400)]
drm/amd/display: hook dp test pattern through debugfs

 set PHY layer or Link layer test pattern
 PHY test pattern is used for PHY SI check.
 Link layer test will not affect PHY SI.

 - normal video mode
  0 = DP_TEST_PATTERN_VIDEO_MODE

 - PHY test pattern supported
  1 = DP_TEST_PATTERN_D102
  2 = DP_TEST_PATTERN_SYMBOL_ERROR
  3 = DP_TEST_PATTERN_PRBS7
  4 = DP_TEST_PATTERN_80BIT_CUSTOM
  5 = DP_TEST_PATTERN_CP2520_1
  6 = DP_TEST_PATTERN_CP2520_2 = DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE
  7 = DP_TEST_PATTERN_CP2520_3

 - DP PHY Link Training Patterns
  8 = DP_TEST_PATTERN_TRAINING_PATTERN1
  9 = DP_TEST_PATTERN_TRAINING_PATTERN2
  0xa = DP_TEST_PATTERN_TRAINING_PATTERN3
  0xb = DP_TEST_PATTERN_TRAINING_PATTERN4

 - DP Link Layer Test pattern
  0xc = DP_TEST_PATTERN_COLOR_SQUARES
  0xd = DP_TEST_PATTERN_COLOR_SQUARES_CEA
  0xe = DP_TEST_PATTERN_VERTICAL_BARS
  0xf = DP_TEST_PATTERN_HORIZONTAL_BARS
  0x10= DP_TEST_PATTERN_COLOR_RAMP

 debugfs phy_test_pattern is located at /syskernel/debug/dri/0/DP-x

 --- set test pattern
  echo <test pattern #> > test_pattern

 - custom test pattern
  If test pattern # is not supported, NO HW programming will be done
  for DP_TEST_PATTERN_80BIT_CUSTOM, it needs extra 10 bytes of data
  for the user pattern. input 10 bytes data are separated by space

  echo 0x4 0x11 0x22 0x33 0x44 0x55 0x66 0x77 0x88 0x99 0xaa >
  test_pattern

 --- reset test pattern
  echo 0 > test_pattern

 --- HPD detection is disabled when set PHY test pattern

  when PHY test pattern (pattern # within [1,7]) is set, HPD pin of
  HW ASIC is disable. User could unplug DP display from DP connected
  and plug scope to check test pattern PHY SI.
  If there is need unplug scope and plug DP display back, do steps
  below:
  echo 0 > phy_test_pattern
  unplug scope
  plug DP display.

  "echo 0 > phy_test_pattern" will re-enable HPD pin again so that
  video sw driver could detect "unplug scope" and "plug DP display"

Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amd/display: dcc always on for bw calculations on raven
Dmytro Laktyushkin [Wed, 13 Jun 2018 17:58:14 +0000 (13:58 -0400)]
drm/amd/display: dcc always on for bw calculations on raven

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amd/display: read DP sink and DP branch hardware and firmware revision from DPCD
Alvin lee [Tue, 19 Jun 2018 19:40:09 +0000 (15:40 -0400)]
drm/amd/display: read DP sink and DP branch hardware and firmware revision from DPCD

- define new dpcd address in drm
- implement new members in dpcd_caps to store values read from new dpcd address

Signed-off-by: Alvin lee <alvin.lee3@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amd/display: Convert remaining loggers off dc_logger
Nicholas Kazlauskas [Tue, 19 Jun 2018 13:58:24 +0000 (09:58 -0400)]
drm/amd/display: Convert remaining loggers off dc_logger

- Removed dal/dm/dc loggers from linux, switched to kernel prints
- Modified functions that used these directly to use macros
- dc_logger support is completely dropped from Linux

Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amd/display: Return aux replies directly to DRM
Harry Wentland [Wed, 9 May 2018 20:26:17 +0000 (16:26 -0400)]
drm/amd/display: Return aux replies directly to DRM

Currently we still go through DC code that does error checking, retries,
etc. There's no need for that since DRM already does that for us. This
simplifies the code a bit and makes it easier to debug.

This also ensures we correctly tell DRM how many bytes have actually
been read, as we should. This allows DRM to correctly read the EDID on
the Chamelium DP port.

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amd/display: Break out function to simply read aux reply
Harry Wentland [Tue, 8 May 2018 20:28:31 +0000 (16:28 -0400)]
drm/amd/display: Break out function to simply read aux reply

DRM's DP helpers take care of dealing with the error code for us. In
order not to step on each other's toes we'll need to be able to simply
read auch channel replies without further logic based on return values.

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Sun peng Li <Sunpeng.Li@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amd/display: Serialize is_dp_sink_present
Harry Wentland [Tue, 29 May 2018 17:11:55 +0000 (13:11 -0400)]
drm/amd/display: Serialize is_dp_sink_present

Access to GPIO needs to be serialized. Aux transactions are already
serialized in DRM but we also need to serialize access to the GPIO pin
for purposes of DP dongle detection.

Call is_dp_sink_present through DM so we can lock correctly. This
follows the same pattern used for DPCD transactions.

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amd/display: Expose configure_encoder for link_encoder
Tony Cheng [Mon, 18 Jun 2018 22:32:43 +0000 (18:32 -0400)]
drm/amd/display: Expose configure_encoder for link_encoder

Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amd/display: Define couple extra DCN registers
Charlene Liu [Mon, 18 Jun 2018 23:50:07 +0000 (19:50 -0400)]
drm/amd/display: Define couple extra DCN registers

Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amd/display: Add Azalia registers to HW sequencer
Eric Bernstein [Mon, 18 Jun 2018 19:45:07 +0000 (15:45 -0400)]
drm/amd/display: Add Azalia registers to HW sequencer

Signed-off-by: Eric Bernstein <eric.bernstein@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amd/display: Correct calculation of duration time.
Hugo Hu [Mon, 18 Jun 2018 19:27:58 +0000 (15:27 -0400)]
drm/amd/display: Correct calculation of duration time.

Signed-off-by: Hugo Hu <hugo.hu@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amd/display: dal 3.1.53
Tony Cheng [Tue, 5 Jun 2018 13:14:56 +0000 (09:14 -0400)]
drm/amd/display: dal 3.1.53

Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amd/display: set-read link rate and lane count through debugfs
Hersen Wu [Fri, 15 Jun 2018 18:25:48 +0000 (14:25 -0400)]
drm/amd/display: set-read link rate and lane count through debugfs

 function description
 get/ set DP configuration: lane_count, link_rate, spread_spectrum

  valid lane count value: 1, 2, 4
  valid link rate value:
  06h = 1.62Gbps per lane
  0Ah = 2.7Gbps per lane
  0Ch = 3.24Gbps per lane
  14h = 5.4Gbps per lane
  1Eh = 8.1Gbps per lane

  debugfs is located at /sys/kernel/debug/dri/0/DP-x/link_settings

  --- to get dp configuration

  xxd -l 300 phy_settings

  It will list current, verified, reported, preferred dp configuration.
  current -- for current video mode
  verified --- maximum configuration which pass link training
  reported --- DP rx report caps (DPCD register offset 0, 1 2)
  preferred --- user force settings

  --- set (or force) dp configuration

  echo <lane_count>  <link_rate>

  for example, to force to  2 lane, 2.7GHz,
  echo 4 0xa > link_settings

  spread_spectrum could not be changed dynamically.

  in case invalid lane count, link rate are force, no hw programming will be
  done. please check link settings after force operation to see if HW get
  programming.

  xxd -l 300 link_settings

  check current and preferred settings.

Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amd/display: fix incorrect check for atom table size
Tony Cheng [Sun, 17 Jun 2018 17:26:27 +0000 (13:26 -0400)]
drm/amd/display: fix incorrect check for atom table size

in case we have very few pins in the table, check fails and we can't boot

Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amd/display: generic indirect register access
Tony Cheng [Sat, 16 Jun 2018 23:43:41 +0000 (19:43 -0400)]
drm/amd/display: generic indirect register access

add generic indirect register access following our register access pattern

this will make it easier to review code and programming sequence,
with all the complexity hidden in macro

Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amd/display: fix bug where we are creating bogus i2c aux
Tony Cheng [Fri, 15 Jun 2018 21:53:35 +0000 (17:53 -0400)]
drm/amd/display: fix bug where we are creating bogus i2c aux

[WHY]
we were using  6 instances based on i2caux_dce110.c

[HOW]
pass in how many instances to ctor

Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amd/display: Move common GPIO registers into a common define
Charlene Liu [Fri, 15 Jun 2018 16:19:00 +0000 (12:19 -0400)]
drm/amd/display: Move common GPIO registers into a common define

Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amd/display: Linux Set/Read link rate and lane count through debugfs
Hersen Wu [Fri, 15 Jun 2018 13:28:34 +0000 (09:28 -0400)]
drm/amd/display: Linux Set/Read link rate and lane count through debugfs

expose dc function to be called by linux dm

Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
Reviewed-by: Sun peng Li <Sunpeng.Li@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amd/display: Implement cursor multiplier
Krunoslav Kovac [Thu, 14 Jun 2018 19:08:58 +0000 (15:08 -0400)]
drm/amd/display: Implement cursor multiplier

DCN allows cursor multiplier when blending FP16 surface.

Signed-off-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amd/display: support access ddc for mst branch
Eric Yang [Tue, 12 Jun 2018 22:37:12 +0000 (18:37 -0400)]
drm/amd/display: support access ddc for mst branch

[Why]
Megachip dockings accesses ddc line through display driver when
installing FW. Previously, we would fail every transaction because
link attached to mst branch did not have their ddc transaction type
set.

[How]
Set ddc transaction type when mst branch is connected.

Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amd/display: Add avoid_vbios_exec_table debug bit
Tony Cheng [Thu, 14 Jun 2018 20:06:10 +0000 (16:06 -0400)]
drm/amd/display: Add avoid_vbios_exec_table debug bit

Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amd/display: Separate HUBP surface size and rotation/mirror programming
Eric Bernstein [Fri, 8 Jun 2018 19:01:59 +0000 (15:01 -0400)]
drm/amd/display: Separate HUBP surface size and rotation/mirror programming

Separate HUBP surface size and rotation/mirror programming so that
HUBP revision without mirror/rotation do not access those register
fields.

Signed-off-by: Eric Bernstein <eric.bernstein@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agoRevert "drm/amd/display: make dm_dp_aux_transfer return payload bytes instead of...
Harry Wentland [Fri, 6 Jul 2018 14:54:33 +0000 (10:54 -0400)]
Revert "drm/amd/display: make dm_dp_aux_transfer return payload bytes instead of size"

This reverts commit cc195141133ac3e767d930bedd8294ceebf1f10b.

This commit was problematic on other OSes. The real solution is to
leave all the error checking to DRM and don't do it in DC, which is
addressed by "Return aux replies directly to DRM" later in this patchset.

v2: Add reason for revert.

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agoRevert "drm/amd/display: Don't return ddc result and read_bytes in same return value"
Harry Wentland [Fri, 6 Jul 2018 14:54:18 +0000 (10:54 -0400)]
Revert "drm/amd/display: Don't return ddc result and read_bytes in same return value"

This reverts commit 8a61bc085ffab3071c59efcbeff4044c034e7490.

Need to revert "make dm_dp_aux_transfer return payload bytes instead of
size", which this commit is based on. That commit was problematic on
other OSes. The real solution is to leave all the error checking to DRM
and don't do it in DC, which is addressed by "Return aux replies
directly to DRM" later in this patchset.

v2: Add reason for revert.

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amdgpu: Warn and update pin_size values when destroying a pinned BO
Michel Dänzer [Wed, 11 Jul 2018 10:42:55 +0000 (12:42 +0200)]
drm/amdgpu: Warn and update pin_size values when destroying a pinned BO

This shouldn't happen, but if it does, we'll get a backtrace of the
caller, and update the pin_size values as needed.

v2:
* Check bo->pin_count instead of placement flags (Christian König)

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amdgpu: Make pin_size values atomic
Michel Dänzer [Wed, 11 Jul 2018 10:00:40 +0000 (12:00 +0200)]
drm/amdgpu: Make pin_size values atomic

Concurrent execution of the non-atomic arithmetic could result in
completely bogus values.

v2:
* Rebased on v2 of the previous patch

Cc: stable@vger.kernel.org
Bugzilla: https://bugs.freedesktop.org/106872
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amdgpu: Keep track of amount of pinned CPU visible VRAM
Michel Dänzer [Wed, 11 Jul 2018 10:06:31 +0000 (12:06 +0200)]
drm/amdgpu: Keep track of amount of pinned CPU visible VRAM

Instead of CPU invisible VRAM. Preparation for the following, no
functional change intended.

v2:
* Also change amdgpu_vram_mgr_bo_invisible_size to
  amdgpu_vram_mgr_bo_visible_size, allowing further simplification
  (Christian König)

Cc: stable@vger.kernel.org
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/scheduler: modify args of drm_sched_entity_init
Nayan Deshmukh [Fri, 13 Jul 2018 09:51:14 +0000 (15:21 +0530)]
drm/scheduler: modify args of drm_sched_entity_init

replace run queue by a list of run queues and remove the
sched arg as that is part of run queue itself

Signed-off-by: Nayan Deshmukh <nayan26deshmukh@gmail.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Acked-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/scheduler: add a pointer to scheduler in the rq
Nayan Deshmukh [Fri, 13 Jul 2018 09:51:13 +0000 (15:21 +0530)]
drm/scheduler: add a pointer to scheduler in the rq

This patch is in preparation for a better load balancing in
scheduler. It allows us to associate entities with the
run queues instead of binding them to a scheduler.

Signed-off-by: Nayan Deshmukh <nayan26deshmukh@gmail.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Acked-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amdgpu: fix TTM move entity init order
Christian König [Thu, 12 Jul 2018 12:31:25 +0000 (14:31 +0200)]
drm/amdgpu: fix TTM move entity init order

We are initializing the entity before the scheduler is actually
initialized.

This can lead to all kind of problem, but especially NULL pointer deref
because of Nayan's scheduler work.

Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amd: Use newly added interrupt source defs for SOC15.
Andrey Grodzovsky [Fri, 25 May 2018 14:45:34 +0000 (10:45 -0400)]
drm/amd: Use newly added interrupt source defs for SOC15.

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amd: Add interrupt source definitions for SOC15 v3.
Andrey Grodzovsky [Fri, 25 May 2018 14:44:12 +0000 (10:44 -0400)]
drm/amd: Add interrupt source definitions for SOC15 v3.

Stop using 'magic numbers' when registering interrupt sources.

v2: Switch to kernel style comments.

v3:
Rebase.

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amd: Use newly added interrupt source defs for VI v3.
Andrey Grodzovsky [Fri, 25 May 2018 14:06:52 +0000 (10:06 -0400)]
drm/amd: Use newly added interrupt source defs for VI v3.

v2: Rebase
v3: Use defines for CP_SQ and CP_ECC_ERROR interrupts.

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amd: Add interrupt source definitions for VI v3.
Andrey Grodzovsky [Wed, 11 Jul 2018 21:34:35 +0000 (17:34 -0400)]
drm/amd: Add interrupt source definitions for VI v3.

Stop using 'magic numbers' when registering interrupt sources.

v2:
Clean redundant comments.
Switch to kernel style comments.

v3:
Add CP_ECC_ERROR define

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amd/powerplay: convert the sclk/mclk into Mhz for comparation
Evan Quan [Tue, 10 Jul 2018 03:35:16 +0000 (11:35 +0800)]
drm/amd/powerplay: convert the sclk/mclk into Mhz for comparation

Convert the clocks into right Mhz unit. Otherwise, it will miss
the equal situation.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amd/powerplay: no need to mask workable gfxoff feature for vega12
Evan Quan [Thu, 5 Jul 2018 02:44:33 +0000 (10:44 +0800)]
drm/amd/powerplay: no need to mask workable gfxoff feature for vega12

Gfxoff feature for vega12 is workable. So, there is no need to
mask it any more.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amd/powerplay: add vega12 SMU gfxoff support v3
Evan Quan [Wed, 4 Jul 2018 08:44:07 +0000 (16:44 +0800)]
drm/amd/powerplay: add vega12 SMU gfxoff support v3

Export apis for enabling/disabling SMU gfxoff support.

v2: fit the latest gfxoff support framework
v3: add feature_mask control

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Huang Rui <ray.huang at amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amdgpu: reduce the idle period that RLC has to wait before request CGCG
Evan Quan [Thu, 5 Jul 2018 02:30:36 +0000 (10:30 +0800)]
drm/amdgpu: reduce the idle period that RLC has to wait before request CGCG

Gfxoff feature may depends on the CGCG(on vega12, that's the case). This
change will help to enable gfxoff feature more frequently.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amdgpu: no touch for the reserved bit of RLC_CGTT_MGCG_OVERRIDE
Evan Quan [Thu, 5 Jul 2018 02:26:48 +0000 (10:26 +0800)]
drm/amdgpu: no touch for the reserved bit of RLC_CGTT_MGCG_OVERRIDE

On vega12, the bit0 of RLC_CGTT_MGCG_OVERRIDE is reserved.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amdgpu: drop mmRLC_PG_CNTL clear v2
Evan Quan [Wed, 4 Jul 2018 09:06:38 +0000 (17:06 +0800)]
drm/amdgpu: drop mmRLC_PG_CNTL clear v2

SMU owns this register so the driver should not set it
to avoid breaking gfxoff.

v2: update description

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
Reviewed-by: Huang Rui <ray.huang at amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amdgpu: correct rlc save restore list initialization for v2_1
Evan Quan [Thu, 5 Jul 2018 03:24:20 +0000 (11:24 +0800)]
drm/amdgpu: correct rlc save restore list initialization for v2_1

The save restore list initialization does not have to be pg guarded.
And for some asic(e.g. Vega12), it does not have cntl/gpm/srm lists.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amdgpu: init CSIB regardless of rlc version and pg status
Evan Quan [Thu, 5 Jul 2018 03:17:48 +0000 (11:17 +0800)]
drm/amdgpu: init CSIB regardless of rlc version and pg status

CSIB init has no relation with rlc version and pg status. It should be
needed regardless of them.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amdgpu: pin the csb buffer on hw init v2
Evan Quan [Wed, 4 Jul 2018 08:21:52 +0000 (16:21 +0800)]
drm/amdgpu: pin the csb buffer on hw init v2

Without this pin, the csb buffer will be filled with inconsistent
data after S3 resume. And that will causes gfx hang on gfxoff
exit since this csb will be executed then.

v2: fit amdgpu_bo_pin change(take one less argument)

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amd/pp: fix semicolon.cocci warnings
kbuild test robot [Tue, 10 Jul 2018 17:11:08 +0000 (01:11 +0800)]
drm/amd/pp: fix semicolon.cocci warnings

drivers/gpu/drm/amd/amdgpu/../powerplay/amd_powerplay.c:1209:17-18: Unneeded semicolon

 Remove unneeded semicolon.

Generated by: scripts/coccinelle/misc/semicolon.cocci

Fixes: ea870e44415a ("drm/amd/pp: Export notify_smu_enable_pwe to display")
CC: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: kbuild test robot <fengguang.wu@intel.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amdgpu: get VCN start to process in the dpm disabled case
Leo Liu [Wed, 4 Jul 2018 17:35:56 +0000 (13:35 -0400)]
drm/amdgpu: get VCN start to process in the dpm disabled case

Fixes: 22cc6c5e19 (drm/amdgpu: Add runtime VCN PG support)
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amdgpu: move cache window setup after power and clock resume
Leo Liu [Wed, 4 Jul 2018 17:43:38 +0000 (13:43 -0400)]
drm/amdgpu: move cache window setup after power and clock resume

To make register read/write reliable

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amdgpu: Take VCN jpeg ring into account in idle work handler
Leo Liu [Mon, 9 Jul 2018 15:59:01 +0000 (11:59 -0400)]
drm/amdgpu: Take VCN jpeg ring into account in idle work handler

VCN won't get power off when only jpeg active

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/ttm: Replace ttm_bo_unref() with ttm_bo_put()
Thomas Zimmermann [Thu, 21 Jun 2018 13:21:37 +0000 (15:21 +0200)]
drm/ttm: Replace ttm_bo_unref() with ttm_bo_put()

A call to ttm_bo_unref() clears the supplied pointer to NULL, while
ttm_bo_put() does not. None of the converted call sites requires the
pointer to become NULL, so the respective assign operations has been
left out from the patch.

Signed-off-by: Thomas Zimmermann <contact@tzimmermann.org>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/ttm: Replace ttm_bo_reference() with ttm_bo_get()
Thomas Zimmermann [Thu, 21 Jun 2018 13:21:36 +0000 (15:21 +0200)]
drm/ttm: Replace ttm_bo_reference() with ttm_bo_get()

Signed-off-by: Thomas Zimmermann <contact@tzimmermann.org>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/ttm: Introduce ttm_bo_get() and ttm_bo_put() for ref counting
Thomas Zimmermann [Thu, 21 Jun 2018 13:21:35 +0000 (15:21 +0200)]
drm/ttm: Introduce ttm_bo_get() and ttm_bo_put() for ref counting

The TTM buffer-object interface provides ttm_bo_reference() and
ttm_bo_unref() for managing reference counts. Replacing them with
ttm_bo_get() and ttm_bo_put() aligns the API with conventions used
throughout the Linux kernel.

The implementation of ttm_bo_unref() clears the supplied pointer
to NULL. This leads to workarounds where the caller saves the
pointer's value before de-referencing the BO. ttm_bo_put() does
not clear the supplied pointer.

Signed-off-by: Thomas Zimmermann <contact@tzimmermann.org>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/ttm: use swap macro in ttm_bo_handle_move_mem
Gustavo A. R. Silva [Mon, 9 Jul 2018 15:24:47 +0000 (10:24 -0500)]
drm/ttm: use swap macro in ttm_bo_handle_move_mem

Make use of the swap macro and remove unnecessary variable *tmp_mem*.
This makes the code easier to read and maintain. Also, reduces the
stack usage.

This code was detected with the help of Coccinelle.

Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amd/pp: Send khz clock values to DC for smu7/8
Harry Wentland [Mon, 9 Jul 2018 17:48:12 +0000 (13:48 -0400)]
drm/amd/pp: Send khz clock values to DC for smu7/8

The previous change wasn't covering smu 7 and 8 and therefore DC was
seeing wrong clock values.

This fixes an issue where the pipes seem to hang with a 4k DP and 1080p
HDMI display.

Fixes: c3df50abc84b ("drm/amd/pp: Convert clock unit to KHz as defined")
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Cc:rex.zhu@amd.com
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amdgpu: Verify root PD is mapped into kernel address space (v4)
Andrey Grodzovsky [Thu, 5 Jul 2018 18:49:34 +0000 (14:49 -0400)]
drm/amdgpu: Verify root PD is mapped into kernel address space (v4)

Problem: When PD/PT update made by CPU root PD was not yet mapped causing
page fault.

Fix: Verify root PD is mapped into CPU address space.

v2:
Make sure that we add the root PD to the relocated list
since then it's get mapped into CPU address space bt default
in amdgpu_vm_update_directories.

v3:
Drop change to not move kernel type BOs to evicted list.

v4:
Remove redundant bo move to relocated list.

Link: https://bugs.freedesktop.org/show_bug.cgi?id=107065
Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amdgpu: Present amdgpu_task_info in VM_FAULTS.
Andrey Grodzovsky [Fri, 29 Jun 2018 02:55:27 +0000 (22:55 -0400)]
drm/amdgpu: Present amdgpu_task_info in VM_FAULTS.

Extract and present the reposnsible process and thread when
VM_FAULT happens.

v2: Use getter and setter functions.

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Acked-by: Jim Qu <Jim.Qu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amdgpu: Add support for logging process info in amdgpu_vm.
Andrey Grodzovsky [Fri, 29 Jun 2018 02:51:32 +0000 (22:51 -0400)]
drm/amdgpu: Add support for logging process info in amdgpu_vm.

Add process and thread names and pids and a function to extract
this info from relevant amdgpu_vm.

v2: Add documentation and fix identation.

v3: Add getter and setter functions for amdgpu_task_info.

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Acked-by: Jim Qu <Jim.Qu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amd/display: Make function pointer structs const
Harry Wentland [Fri, 6 Jul 2018 13:49:05 +0000 (09:49 -0400)]
drm/amd/display: Make function pointer structs const

const to avoid hard-to-find bugs where some function overrides a
function pointer.

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amd/display: make function tables const
Christian König [Fri, 6 Jul 2018 12:19:07 +0000 (14:19 +0200)]
drm/amd/display: make function tables const

It is good practice to make global function tables const to avoid
accidental override.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amd/display: fix invalid function table override
Christian König [Fri, 6 Jul 2018 11:46:05 +0000 (13:46 +0200)]
drm/amd/display: fix invalid function table override

Otherwise we try to program hardware with the wrong watermark functions
when multiple DCE generations are installed in one system.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amd/pp: Convert 10KHz to KHz as variable name
Rex Zhu [Thu, 5 Jul 2018 08:45:21 +0000 (16:45 +0800)]
drm/amd/pp: Convert 10KHz to KHz as variable name

The default clock unit in powerplay is 10KHz.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amdgpu: Add CLK IP base offset
Rex Zhu [Thu, 5 Jul 2018 08:34:13 +0000 (16:34 +0800)]
drm/amdgpu: Add CLK IP base offset

so we can read/write the registers in CLK domain
through RREG32/WREG32_SOC15

Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amdgpu: Reserve VM root shared fence slot for command submission (v3)
Michel Dänzer [Mon, 25 Jun 2018 09:07:17 +0000 (11:07 +0200)]
drm/amdgpu: Reserve VM root shared fence slot for command submission (v3)

Without this, there could not be enough slots, which could trigger the
BUG_ON in reservation_object_add_shared_fence.

v2:
* Jump to the error label instead of returning directly (Jerry Zhang)
v3:
* Reserve slots for command submission after VM updates (Christian König)

Cc: stable@vger.kernel.org
Bugzilla: https://bugs.freedesktop.org/106418
Reported-by: mikhail.v.gavrilov@gmail.com
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amdgpu: fix kmap error handling for bo creations
Junwei Zhang [Tue, 26 Jun 2018 08:23:48 +0000 (16:23 +0800)]
drm/amdgpu: fix kmap error handling for bo creations

kmap happens after bo pin, so unpin is required on error

Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amdgpu: allocate gart memory when it's required (v3)
Junwei Zhang [Mon, 25 Jun 2018 05:32:24 +0000 (13:32 +0800)]
drm/amdgpu: allocate gart memory when it's required (v3)

Instead of calling gart address space on every bo pin,
allocates it on demand

v2: fix error handling
v3: drop the change on amdgpu_amdkfd_gpuvm.c, not needed.

Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agodrm/amdgpu: separate gpu address from bo pin
Junwei Zhang [Mon, 25 Jun 2018 04:51:14 +0000 (12:51 +0800)]
drm/amdgpu: separate gpu address from bo pin

It could be got by amdgpu_bo_gpu_offset() if need

Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
6 years agoMerge tag 'vmwgfx-next-4.19-3' of git://people.freedesktop.org/~thomash/linux into...
Dave Airlie [Tue, 10 Jul 2018 01:13:36 +0000 (11:13 +1000)]
Merge tag 'vmwgfx-next-4.19-3' of git://people.freedesktop.org/~thomash/linux into drm-next

This introduces a header update and support for multisample surfaces.

Signed-off-by: Dave Airlie <airlied@redhat.com>
Link: https://patchwork.freedesktop.org/patch/msgid/d020efb8-776d-5e8f-9d9f-122591e074d6@vmware.com
6 years agoMerge tag 'vmwgfx-next-4.19-2' of git://people.freedesktop.org/~thomash/linux into...
Dave Airlie [Tue, 10 Jul 2018 01:05:46 +0000 (11:05 +1000)]
Merge tag 'vmwgfx-next-4.19-2' of git://people.freedesktop.org/~thomash/linux into drm-next

A series of cleanups / reorganizations and modesetting changes that
mostly target atomic state validation.

[airlied: conflicts with SPDX stuff in amdgpu tree]
Signed-off-by: Dave Airlie <airlied@redhat.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1a88485e-e509-b00e-8485-19194f074115@vmware.com
6 years agoMerge branch 'drm-next-4.19' of git://people.freedesktop.org/~agd5f/linux into drm...
Dave Airlie [Tue, 10 Jul 2018 00:57:02 +0000 (10:57 +1000)]
Merge branch 'drm-next-4.19' of git://people.freedesktop.org/~agd5f/linux into drm-next

More features for 4.19:
- Use core pcie functionality rather than duplicating our own for pcie
  gens and lanes
- Scheduler function naming cleanups
- More documentation
- Reworked DC/Powerplay interfaces to improve power savings
- Initial stutter mode support for RV (power feature)
- Vega12 powerplay updates
- GFXOFF fixes
- Misc fixes

Signed-off-by: Dave Airlie <airlied@redhat.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180705221447.2807-1-alexander.deucher@amd.com
6 years agoMerge tag 'tilcdc-4.19' of https://github.com/jsarha/linux into drm-next
Dave Airlie [Tue, 10 Jul 2018 00:46:42 +0000 (10:46 +1000)]
Merge tag 'tilcdc-4.19' of https://github.com/jsarha/linux into drm-next

tilcdc pull request for v4.19

Single fix to defer probing.

Signed-off-by: Dave Airlie <airlied@redhat.com>
Link: https://patchwork.freedesktop.org/patch/msgid/a10f5b43-7711-6b80-1bc3-0dfce65c628f@ti.com
6 years agodrm/vmwgfx: Expose SM4_1 param to user space
Deepak Rawat [Wed, 20 Jun 2018 22:09:43 +0000 (15:09 -0700)]
drm/vmwgfx: Expose SM4_1 param to user space

A new param DRM_VMW_PARAM_SM4_1, is added for user space to determine
availability of SM4.1.

Minor version bump for SM4.1.

Signed-off-by: Deepak Rawat <drawat@vmware.com>
Reviewed-by: Sinclair Yeh <syeh@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Thomas Hellstrom <thellstrom@vmware.com>
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
6 years agodrm/vmwgfx: Add support for multisampling
Deepak Rawat [Wed, 20 Jun 2018 22:24:05 +0000 (15:24 -0700)]
drm/vmwgfx: Add support for multisampling

Support for SVGA3D_SURFACE_MULTISAMPLE and surface mob size according
to sample count.

Signed-off-by: Deepak Rawat <drawat@vmware.com>
Reviewed-by: Sinclair Yeh <syeh@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
6 years agodrm/vmwgfx: Add new ioctl for GB surface create and reference
Deepak Rawat [Wed, 20 Jun 2018 21:48:35 +0000 (14:48 -0700)]
drm/vmwgfx: Add new ioctl for GB surface create and reference

New ioctls DRM_VMW_GB_SURFACE_CREATE_EXT and DRM_VMW_GB_SURFACE_REF_EXT
are added which support 64-bit wide svga device surface flags, quality
level and multisample pattern.

Signed-off-by: Deepak Rawat <drawat@vmware.com>
Reviewed-by: Sinclair Yeh <syeh@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
6 years agodrm/vmwgfx: Support for SVGA3dSurfaceAllFlags in vmwgfx
Deepak Rawat [Wed, 20 Jun 2018 21:25:07 +0000 (14:25 -0700)]
drm/vmwgfx: Support for SVGA3dSurfaceAllFlags in vmwgfx

Since svga device introduced new 64bit SVGA3dSurfaceAllFlags, vmwgfx
now stores the surface flags internally as SVGA3dSurfaceAllFlags.
For legacy surface define commands, only lower 32-bit is used.

Signed-off-by: Deepak Rawat <drawat@vmware.com>
Reviewed-by: Sinclair Yeh <syeh@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Thomas Hellstrom <thellstrom@vmware.com>
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
6 years agodrm/vmwgfx: Add support for SVGA3dCmdDefineGBSurface_v3
Deepak Rawat [Wed, 20 Jun 2018 21:20:23 +0000 (14:20 -0700)]
drm/vmwgfx: Add support for SVGA3dCmdDefineGBSurface_v3

SVGA device added new command SVGA3dCmdDefineGBSurface_v3 which allows
64-bit SVGA3dSurfaceAllFlags. This commit adds support for
SVGA3dCmdDefineGBSurface_v3 command in vmwgfx.

Signed-off-by: Deepak Rawat <drawat@vmware.com>
Reviewed-by: Sinclair Yeh <syeh@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>