Ben Skeggs [Fri, 19 Feb 2010 22:06:36 +0000 (08:06 +1000)]
drm/nv50: fix instmem binding on IGPs to point at stolen system memory
This also modifies the unused PRAMIN PT entries to be all zeroes, can't
really recall why I used 9/0 initially, just that it didn't work for
some reason. It was likely masking a bug elsewhere that's since been
fixed.
Ben Skeggs [Thu, 11 Feb 2010 01:31:44 +0000 (11:31 +1000)]
drm/nv50: improve vram page table construction
This commit changes nouveau to construct PTEs which look very much like
the ones the binary driver creates.
I presume that filling multiple PTEs identically with length flags and
the physical address of the start of a block of VRAM is a hint to the
memory controller that it need not perform additional page table lookups
for that range of addresses.
drm/nv50: avoid unloading pgraph context when ctxprog is running
- We need to disable pgraph fifo access before checking the current channel,
otherwise we could still hit a running ctxprog.
- The writes to 0x400500 are already handled by pgraph->fifo_access and are
therefore redundant, moreover pgraph fifo access should not be reenabled
before current context is set as invalid. So remove them altogether.
Signed-off-by: Maarten Maathuis <madman2003@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Maarten Maathuis [Sun, 27 Dec 2009 11:22:07 +0000 (12:22 +0100)]
drm/nv50: align size of buffer object to the right boundaries.
- In the current situation the padding that is added is dangerous to write
to, userspace could potentially overwrite parts of another bo.
- Depth and stencil buffers are supposed to be large enough in general so
the waste of memory should be acceptable.
- Alternatives are hiding the padding from users or splitting vram into 2
zones.
Signed-off-by: Maarten Maathuis <madman2003@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Ben Skeggs [Tue, 9 Feb 2010 00:22:29 +0000 (10:22 +1000)]
drm/nv50: prevent multiple init tables being parsed at the same time
With DVI and DP plugged, the DVI clock change interrupts being run can
cause DP link training to fail. This adds a spinlock around init table
parsing to prevent this.
Ben Skeggs [Fri, 22 Jan 2010 03:17:28 +0000 (13:17 +1000)]
drm/nv40: make INIT_COMPUTE_MEM a NOP, just like nv50
It appears we aren't required to do memory sizing ourselves on nv40
either. NV40 init tables read a strap from PEXTDEV_BOOT_0 into a
CRTC register, and then later use that value to select a memory
configuration (written to PFB_CFG0, just like INIT_COMPUTE_MEM on
earlier cards) with INIT_IO_RESTRICT_PROG.
drm/nouveau: Fix fbcon on mixed pre-NV50 + NV50 multicard.
We used single shared fbops struct and patched it at fb init time with
pointers to the right variant. On mixed multicard, this meant that
it was either sending NV50-style commands to all cards, or NV04-style
commands to all cards.
Signed-off-by: Marcin Kościelnicki <koriakin@0x04.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Julia Lawall [Tue, 2 Feb 2010 22:40:30 +0000 (14:40 -0800)]
drivers/gpu/drm/nouveau/nouveau_grctx.c: correct NULL test
Test the just-allocated value for NULL rather than some other value.
The semantic patch that makes this change is as follows:
(http://coccinelle.lip6.fr/)
// <smpl>
@@
expression x,y;
statement S;
@@
x = \(kmalloc\|kcalloc\|kzalloc\)(...);
(
if ((x) == NULL) S
|
if (
- y
+ x
== NULL)
S
)
// </smpl>
Signed-off-by: Julia Lawall <julia@diku.dk> Cc: David Airlie <airlied@linux.ie> Cc: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Francisco Jerez [Sat, 30 Jan 2010 17:28:00 +0000 (18:28 +0100)]
drm/nouveau: Fixup semaphores on pre-nv50 cards.
Apparently, they generate a PFIFO interrupt each time one of the
semaphore methods is executed if its ctxdma wasn't manually marked as
valid. This patch makes it flip the valid bit in response to the
DMA_SEMAPHORE method (which triggers the IRQ even for a valid ctxdma).
Signed-off-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Ben Skeggs [Thu, 21 Jan 2010 05:03:23 +0000 (15:03 +1000)]
drm/nouveau: fix failure path if userspace specifies no valid memtypes
We need to add the buffer to the list even if we fail, otherwise the
validate_fini() call won't unreserve + unreference the GEM object,
making TTM very unhappy.
Ben Skeggs [Sun, 17 Jan 2010 22:52:35 +0000 (08:52 +1000)]
drm/nv50: prevent accidently turning off encoders we're actually using
On most cards the DisplayPort connector is created with 2 encoders sharing
a single SOR (for native DP, and for DVI-over-DP). The previous logic
for turning off unused encoders didn't take into account that we could
have multiple drm_encoders on a single hw encoder and ended up turning off
encoders that were actually being used still.
This patch fixes that issue. We probably want to look at something a bit
better later on, and only expose one drm_encoder per hw encoder block.
Luca Barbieri [Sat, 16 Jan 2010 14:30:15 +0000 (15:30 +0100)]
drm/nouveau: Evict buffers in VRAM before freeing sgdma
Currently, we take down the sgdma engine without evicting all buffers
from VRAM.
The TTM device release will try to evict anything in VRAM to GART
memory, but this will fail since sgdma has already been taken down.
This causes an infinite loop in kernel mode on module unload.
It usually doesn't happen because there aren't any buffer on close.
However, if the GPU is locked up, this condition is easily triggered.
This patch fixes it in the simplest way possible by cleaning VRAM
right before cleaning SGDMA memory.
Signed-off-by: Luca Barbieri <luca@luca-barbieri.com> Signed-off-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Currently Nouveau is unable to dismiss DMA_VTX_PROTECTION errors,
which results in an infinite loop in the interrupt handler.
These errors are caused both by bugs in the Gallium driver and by
user-specified index buffers with out of bounds indices.
By mmio-tracing the nVidia drivers, I found out how this is done.
On DMA_VTX_PROTECTION, The nVidia driver reads the register 0x402000,
always getting the value 4, and then writes 4 back to 0x402000.
This patch adds that logic by reading 0x402000 and writing the same
value back.
It's unclear what should happen if the value read is not 4, and
the current approach might not be the correct one.
To test this, modify mesa/progs/trivial/vbo-drawrange.c, defining
ELTOBJ to 1 and replacing indices with huge out of bounds integers.
Without this patch, the GPU and/or kernel should lock up.
With this patch, it should misrender as expected but not lock up.
The errors are still logged since they are useful for development.
This has been tested on NV49 and may not work on other cards.
To find out how things work on other cards, run the aforementioned
test using the blob with mmiotrace and grep for a read of the PGRAPH
source register.
Signed-off-by: Luca Barbieri <luca@luca-barbieri.com> Signed-off-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Andrea Tacconi [Thu, 14 Jan 2010 13:52:37 +0000 (14:52 +0100)]
drm/nouveau: add NV18 device id to call_lvds_manufacturer_script
This fixes imac black screen (NV18 card)
Signed-off-by: Andrea Tacconi <tacconet@libero.it> Signed-off-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Ben Skeggs [Thu, 14 Jan 2010 07:53:04 +0000 (17:53 +1000)]
drm/nouveau: less magic DCB 1.5 parsing
This in the very least matches the parsing of all the previously known
entries, and hopefully (at least closer to) correct for any we haven't
seen yet.
Ben Skeggs [Thu, 14 Jan 2010 05:58:10 +0000 (15:58 +1000)]
drm/nouveau: assume no nv04 board has a DCB table
There's a report of a TNT2 where the DCB table pointer is *not* NULL
(it contains a part of a VBIOS data string), and we assume this means
a DCB table is present, causing all kinds of hilarity.
Ben Skeggs [Tue, 12 Jan 2010 05:28:19 +0000 (15:28 +1000)]
drm/nouveau: wait on fence after bo move if validating for another channel
Not an ideal solution, but it'll do for the moment for correctness. We
need to come up with a nicer way to manage inter-channel sync, the hw
is unfortunately a little lacking in this area.
Should fix some resume corruption, as well as corruption that may be seen
while under memory pressure.
Ben Skeggs [Tue, 12 Jan 2010 03:02:19 +0000 (13:02 +1000)]
drm/nouveau: trust init table registers are safe
Apparently the original reason for checking this was there were known
register accesses that caused hangs on some chipsets. This was more
than likely because of incorrect parsing of previous opcodes, and I
hardly think aborting a script half way through is going to be any
better (in fact, we have had bug reports where this has been the cause
of s/r failures among other things).
This patch (which has been in Fedora 12 for a long time now) removes
all checking for known register ranges, and just leaves the check to
ensure the access is within the mapped aperture to avoid an oops.
Luca Barbieri [Wed, 6 Jan 2010 03:02:45 +0000 (04:02 +0100)]
drm/nouveau: Fix null deref in nouveau_fence_emit due to deleted fence
Currently Nouveau will unvalidate all buffers if it is forced to wait on
one, and then start revalidating from the beginning. While doing so, it
destroys the operation fence, causing nouveau_fence_emit to crash.
This patch fixes this bug by taking the fence object out of validate_op
and creating it just before emit. The fence pointer is initialized to 0
and unref'ed unconditionally.
In addition to fixing the bug, this prevents its reintroduction and
simplifies the code.
Signed-off-by: Luca Barbieri <luca@luca-barbieri.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Ben Skeggs [Wed, 6 Jan 2010 02:00:02 +0000 (12:00 +1000)]
drm/nv50: prevent a possible ctxprog hang
The below is mainly an educated guess at what's going on, docs would
sure be handy... NVIDIA? :P
It appears it's possible for a ctxprog to run even while a GPU exception
is pending. The GF8 and up ctxprogs appear to have a small snippet of
code which detects this, and stalls the ctxprog until it's been handled,
which essentially looks like:
if (r2 & 0x00008000) {
r0 |= 0x80000000;
while (r0 & 0x80000000) {}
}
I don't know of any way that flag would get cleared unless the driver
intervenes (and indeed, in the cases I've seen the hang, nothing steps
in to automagically clear it for us). This patch causes the driver to
clear the flag during the PGRAPH IRQ handler.
Francisco Jerez [Sat, 26 Dec 2009 01:09:36 +0000 (02:09 +0100)]
drm/nouveau: Use the software object for fencing.
This should avoid a race condition on nv0x, if we're doing it with
actual PGRAPH objects and a there's a fence within the FIFO DMA fetch
area when a context switch kicks in.
In that case we get an ILLEGAL_MTHD interrupt as expected, but the
values in PGRAPH_TRAPPED_ADDR aren't calculated correctly and they're
almost useless (e.g. you can see ILLEGAL_MTHDs for the now inactive
channel, with a wrong offset/data pair).
Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Francisco Jerez [Sat, 26 Dec 2009 01:42:45 +0000 (02:42 +0100)]
drm/nouveau: Allocate a per-channel instance of NV_SW.
It will be useful for various synchronization purposes, mostly stolen
from "[PATCH] drm/nv50: synchronize user channel after buffer object
move on kernel channel" by Maarten Maathuis.
Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Francisco Jerez [Wed, 16 Dec 2009 11:27:11 +0000 (12:27 +0100)]
drm/i2c/ch7006: Drop build time dependency to nouveau.
This partially reverts e4b41066, as this driver is intended to be
useful with any KMS driver for suitable hardware. The missing build
dependency that commit workarounded was DRM_KMS_HELPER.
Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Francisco Jerez [Fri, 11 Dec 2009 15:51:09 +0000 (16:51 +0100)]
drm/nouveau: Make the MM aware of pre-G80 tiling.
This commit has also the following 3 bugfix commits squashed into it from
the nouveau git tree:
drm/nouveau: Fix up the tiling alignment restrictions for nv1x.
drm/nouveau: Fix up the nv2x tiling alignment restrictions.
drm/nv50: fix align typo for g9x
Signed-off-by: Francisco Jerez <currojerez@riseup.net>
David John [Thu, 31 Dec 2009 06:30:46 +0000 (12:00 +0530)]
drm: Keep disabled outputs disabled after suspend / resume
With the current DRM code, an output that has been powered off
from userspace will automatically power back on when resuming
from suspend. This patch fixes this behaviour.
Tested only with the Intel i915 driver on an Intel GM45 Express
chipset.
Signed-off-by: David John <davidjon@xenontk.org> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Dave Airlie <airlied@redhat.com>
Jerome Glisse [Thu, 7 Jan 2010 14:39:14 +0000 (15:39 +0100)]
drm/radeon/kms: Don't try to enable IRQ if we have no handler installed
If for any reason we haven't installed handler we shouldn't try to
enable IRQ/MSI on the hw so we don't get unhandled IRQ/MSI which
makes the kernel sad.
Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Jerome Glisse [Thu, 7 Jan 2010 14:39:13 +0000 (15:39 +0100)]
drm: Avoid calling vblank function is vblank wasn't initialized
In some case vblank might not be initialized and we shouldn't
try to use associated function. This patch make sure this is
the case. It also export drm_vblank_cleanup so driver can cleanup
vblank if for any reason IRQ/MSI is not working.
Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Jerome Glisse [Thu, 7 Jan 2010 15:08:32 +0000 (16:08 +0100)]
drm/radeon/kms: Make sure we release AGP device if we acquired it
In some case we weren't releasing the AGP device at module unloading.
This leaded to unfunctional AGP at next module load. This patch make
sure we release the AGP bus if we acquire it.
Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Jerome Glisse [Thu, 7 Jan 2010 11:39:21 +0000 (12:39 +0100)]
drm/radeon/kms: Schedule host path read cache flush through the ring V2
R300 family will hard lockup if host path read cache flush is
done through MMIO to HOST_PATH_CNTL. But scheduling same flush
through ring seems harmless. This patch remove the hdp_flush
callback and add a flush after each fence emission which means
a flush after each IB schedule. Thus we should have same behavior
without the hard lockup.
Tested on R100,R200,R300,R400,R500,R600,R700 family.
V2: Adjust fence counts in r600_blit_prepare_copy()
Signed-off-by: Jerome Glisse <jglisse@redhat.com> Reviewed-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Long story short, this fixes sporadic hardlocks with my rv410 during
times of intense 2D acceleration (Flash on Fx3).
V2: Fix indentation and move errata_fini to suspend function so we
don't leak scratch register over suspend/resume cycle.
V3: Move scratch_reg to asic specific structure (aim is to slowly
move stuff to asic specific structure and avoid poluting
radeon_device struct with asic specific variables)
Darren Jenkins [Thu, 7 Jan 2010 06:35:21 +0000 (01:35 -0500)]
drm/radeon: fix a couple of array index errors
There are a couple of array overruns, and some associated confusion in
the code.
This is just a wild guess at what the code should actually look like.
Coverity CID: 13305 13306
agd5f: fix up the original intent of the timing code
Signed-off-by: Darren Jenkins <darrenrjenkins@gmail.com> Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Thu, 7 Jan 2010 04:00:29 +0000 (14:00 +1000)]
Merge remote branch 'korg/drm-radeon-next' into drm-linus
* korg/drm-radeon-next:
drm/radeon/kms: rs600: use correct mask for SW interrupt
gpu/drm/radeon/radeon_irq.c: move a dereference below a NULL test
drm/radeon/radeon_device.c: move a dereference below a NULL test
drm/radeon/radeon_fence.c: move a dereference below the NULL test
drm/radeon/radeon_connectors.c: add a NULL test before dereference
drm/radeon/kms: fix memory leak
drm/radeon/kms: add missing breaks in i2c and ss lookups
drm/radeon/kms: add primary dac adj values table
drm/radeon/kms: fallback to default connector table
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