Vinod Polimera [Thu, 2 Mar 2023 16:33:04 +0000 (22:03 +0530)]
drm: add helper functions to retrieve old and new crtc
Add new helper functions, drm_atomic_get_old_crtc_for_encoder
and drm_atomic_get_new_crtc_for_encoder to retrieve the
corresponding crtc for the encoder.
Signed-off-by: Sankeerth Billakanti <quic_sbillaka@quicinc.com> Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Patchwork: https://patchwork.freedesktop.org/patch/524718/ Link: https://lore.kernel.org/r/1677774797-31063-2-git-send-email-quic_vpolimer@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Rob Clark [Mon, 23 Jan 2023 15:37:45 +0000 (07:37 -0800)]
PM / devfreq: Fix build issues with devfreq disabled
The existing no-op shims for when PM_DEVFREQ (or an individual governor)
only do half the job. The governor specific config/tuning structs need
to be available to avoid compile errors in drivers using devfreq.
Fixes: 6563f60f14cb ("drm/msm/gpu: Add devfreq tuning debugfs") Signed-off-by: Rob Clark <robdclark@chromium.org> Acked-by: MyungJoo Ham <myungjoo.ham@samsung.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Patchwork: https://patchwork.freedesktop.org/patch/519801/ Link: https://lore.kernel.org/r/20230123153745.3185032-1-robdclark@gmail.com
Dmitry Baryshkov [Thu, 29 Dec 2022 19:18:30 +0000 (21:18 +0200)]
drm/msm/dpu: set pdpu->is_rt_pipe early in dpu_plane_sspp_atomic_update()
The function dpu_plane_sspp_atomic_update() updates pdpu->is_rt_pipe
flag, but after the commit 854f6f1c653b ("drm/msm/dpu: update the qos
remap only if the client type changes") it sets the flag late, after all
the qos functions have updated QoS programming. Move the flag update
back to the place where it happened before the mentioned commit to let
the pipe be programmed according to its current RT/non-RT state.
Fixes: 854f6f1c653b ("drm/msm/dpu: update the qos remap only if the client type changes") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/516239/ Link: https://lore.kernel.org/r/20221229191856.3508092-2-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Dmitry Baryshkov [Thu, 19 Jan 2023 13:22:17 +0000 (15:22 +0200)]
drm/msm/hdmi: make hdmi_phy_8960 OF clk provider
On MSM8960 the HDMI PHY provides the PLL clock to the MMCC. As we are
preparing to convert the MSM8960 to use DT clocks properties (rather
than global clock names), register the OF clock provider.
Dmitry Baryshkov [Thu, 19 Jan 2023 13:22:16 +0000 (15:22 +0200)]
drm/msm/hdmi: switch hdmi_pll_8960 to use parent_data
Replace parent_names usage with parent_data. Note, that this makes the
PLL default to board's `pxo_board' clock rather than just `pxo' clock,
as we are on a way to deprecate the global cxo/pxo clocks.
Dmitry Baryshkov [Thu, 19 Jan 2023 13:22:15 +0000 (15:22 +0200)]
dt-bindings: phy: qcom, hdmi-phy-other: mark it as clock provider
Eventually all HDMI PHYs are going to provide the HDMI PLL clock to the
MMCC. Add #clock-cells property required to provide the HDMI PLL clock to
other devices.
Dmitry Baryshkov [Tue, 24 Jan 2023 20:36:00 +0000 (22:36 +0200)]
drm/msm/dsi: properly handle the case of empty OPP table in dsi_mgr_bridge_mode_valid
It was left unnoticed during the review that even if there is no OPP
table in device tree, one will be created by a call to the function
devm_pm_opp_set_clkname(). This leads to dsi_mgr_bridge_mode_valid()
rejecting all modes if DT contains no OPP table for the DSI host.
Rework dsi_mgr_bridge_mode_valid() to handle this case by actually
checking that the table is populated with frequency entries before
returning an error.
Fixes: 8328041b8c82 ("drm/msm/dsi: implement opp table based check for dsi_mgr_bridge_mode_valid()") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/520076/ Link: https://lore.kernel.org/r/20230124203600.3488766-1-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Marijn Suijten [Wed, 25 Jan 2023 10:14:11 +0000 (11:14 +0100)]
drm/msm/dpu: Add DSC hardware blocks to register snapshot
Add missing DSC hardware block register ranges to the snapshot utility
to include them in dmesg (on MSM_DISP_SNAPSHOT_DUMP_IN_CONSOLE) and the
kms debugfs file.
Jiasheng Jiang [Tue, 6 Dec 2022 08:05:17 +0000 (16:05 +0800)]
drm/msm/dpu: Add check for cstate
As kzalloc may fail and return NULL pointer,
it should be better to check cstate
in order to avoid the NULL pointer dereference
in __drm_atomic_helper_crtc_reset.
Fixes: 1cff7440a86e ("drm/msm: Convert to using __drm_atomic_helper_crtc_reset() for reset.") Signed-off-by: Jiasheng Jiang <jiasheng@iscas.ac.cn> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/514163/ Link: https://lore.kernel.org/r/20221206080517.43786-1-jiasheng@iscas.ac.cn Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Stop mentioning #address-cells/#size-cells which are defined in
display/dsi-controller.yaml. Use unevaluatedProperties instead of
additionalProperties to allow skipping properties defined in other
schema files.
Bryan O'Donoghue [Wed, 18 Jan 2023 17:16:20 +0000 (17:16 +0000)]
dt-bindings: msm: dsi-controller-main: Add compatible strings for every current SoC
Currently we do not differentiate between the various users of the
qcom,mdss-dsi-ctrl. The driver is flexible enough to operate from one
compatible string but, the hardware does have some significant differences
in the number of clocks.
To facilitate documenting the clocks add the following compatible strings
DPU, DSI, MDSS:
- Support for SM8350, SM8450 SM8550 and SC8280XP platform
Core:
- Added bindings for SM8150 (driver support already present)
DPU:
- Partial support for DSC on SM8150 and SM8250
- Fixed color transformation matrix being lost on suspend/resume
DP:
- Support for DP on SDM845 and SC8280XP platforms
- HPD fixes
- Support for limiting DP link rate via DT property, this enables
support for HBR3 rates.
DSI:
- Validate display modes according to the DSI OPP table
- DSI PHY support for the SM6375 platform
- Fixed byte intf clock selection for 14nm PHYs
Dmitry Baryshkov [Sun, 22 Jan 2023 20:43:05 +0000 (22:43 +0200)]
Merge branches 'msm-next-lumag-core', 'msm-next-lumag-dpu', 'msm-next-lumag-dp', 'msm-next-lumag-dsi', 'msm-next-lumag-hdmi', 'msm-next-lumag-mdp5' and 'msm-next-lumag-mdp4' into msm-next-lumag
DPU, DSI, MDSS:
- Support for SM8350, SM8450 SM8550 and SC8280XP platform
Core:
- Added bindings for SM8150 (driver support already present)
DPU:
- Partial support for DSC on SM8150 and SM8250
- Fixed color transformation matrix being lost on suspend/resume
DP:
- Support for DP on SDM845 and SC8280XP platforms
- HPD fixes
- Support for limiting DP link rate via DT property, this enables
support for HBR3 rates.
DSI:
- Validate display modes according to the DSI OPP table
- DSI PHY support for the SM6375 platform
- Fixed byte intf clock selection for 14nm PHYs
Konrad Dybcio [Fri, 20 Jan 2023 21:00:53 +0000 (22:00 +0100)]
drm/msm/dsi: Allow 2 CTRLs on v2.5.0
v2.5.0 support was originally added for SC7280, but this hw is also
present on SM8350, which has one more DSI host. Bump up the dsi count
and fill in the register of the secondary host to allow it to probe.
This should not have any adverse effects on SC7280, as the secondary
CTRL will only be touched if it's defined, anyway.
Fixes: 65c391b31994 ("drm/msm/dsi: Add DSI support for SC7280") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/519513/ Link: https://lore.kernel.org/r/20230120210101.2146852-1-konrad.dybcio@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Dmitry Baryshkov [Wed, 18 Jan 2023 13:00:27 +0000 (15:00 +0200)]
drm/msm/dsi: correct byte intf clock rate for 14nm DSI PHY
According to the vendor kernel, byte intf clock rate should be a half of
the byte clock only when DSI PHY version is above 2.0 (in other words,
10nm PHYs and later) and only if PHY is used in D-PHY mode. Currently
MSM DSI code handles only the second part of the clause (C-PHY vs
D-PHY), skipping DSI PHY version check, which causes issues on some of
14nm DSI PHY platforms (e.g. qcm2290).
Move divisor selection to DSI PHY code, pass selected divisor through
shared timings and set byte intf clock rate accordingly.
Bryan O'Donoghue [Mon, 16 Jan 2023 22:52:17 +0000 (22:52 +0000)]
dt-bindings: msm: dsi-controller-main: Add vdd* descriptions back in
When converting from .txt to .yaml we didn't include descriptions for the
existing regulator supplies.
- vdd
- vdda
- vddio
Add those descriptions into the yaml now as they were prior to the
conversion. In the .txt description we marked these regulators as required,
however, that requirement appears to have been in error.
Taking the example of sc7180-trogdor-wormdingler.dtsi. The avdd and avee
come from GPIO controlled external regulators, not the SoC and in this case
there's no need for vddio to power an I/O bus. Similarly the regulators for
the LCD are controlled by the panel driver not by the dsi-ctrl driver.
It would be possible to connect a different type of panel to the DSI bus
here in which case we may or may not want to make use of vdd, vdda or
vddio.
This is also the case for older chipsets like apq8064, msm8916 etc the vdd*
regulators in the dsi-ctrl block are helpers not dependencies.
Add the description of vdd, vdda and vddio back in for the existing
upstream dts where vdd, vdda or vddio are already declared but, don't
declare those regulators required - they are not SoC requirements.
Konrad Dybcio [Mon, 16 Jan 2023 11:51:32 +0000 (12:51 +0100)]
dt-bindings: msm/dsi: Don't require vdds-supply on 7nm PHY
On some SoCs (hello SM6375) vdds-supply is not wired to any smd-rpm
or rpmh regulator, but instead powered by the VDD_MX/mx.lvl line,
which is voted for in the DSI ctrl node.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/518513/ Link: https://lore.kernel.org/r/20230116115132.348961-1-konrad.dybcio@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Abhinav Kumar [Thu, 12 Jan 2023 00:16:00 +0000 (16:16 -0800)]
drm/msm/dsi: implement opp table based check for dsi_mgr_bridge_mode_valid()
Currently there is no protection against a user trying to set
an unsupported mode on DSI. Implement a check based on the opp
table whether the byte clock for the mode can be supported by
validating whether an opp table entry exists.
For devices which have not added opp table support yet, skip
this check otherwise it will break bootup on those devices.
changes in v3:
- make the comment shorter
- handle all errors except ENODEV
Neil Armstrong [Mon, 9 Jan 2023 10:15:22 +0000 (11:15 +0100)]
drm/msm/dsi: add support for DSI-PHY on SM8550
SM8550 use a 4nm DSI PHYs, which share register definitions
with 7nm DSI PHYs. Rather than duplicating the driver, handle
4nm variant inside the common 5+7nm driver.
drm/msm/dsi: add support for DSI-PHY on SM8350 and SM8450
SM8350 and SM8450 use 5nm DSI PHYs, which share register definitions
with 7nm DSI PHYs. Rather than duplicating the driver, handle 5nm
variants inside the common 5+7nm driver.
Co-developed-by: Robert Foss <robert.foss@linaro.org> Signed-off-by: Robert Foss <robert.foss@linaro.org> Tested-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/514230/ Link: https://lore.kernel.org/r/20221207012231.112059-7-dmitry.baryshkov@linaro.org
[DB: changed compatibles per Krzysztof's request] Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Jessica Zhang [Wed, 18 Jan 2023 23:38:48 +0000 (15:38 -0800)]
drm/msm/dpu: Reapply CTM if modeset is needed
Add a !drm_atomic_crtc_needs_modeset() check to
_dpu_crtc_setup_cp_blocks() so that CTM is reapplied if the LM/DSPP
blocks were reallocated during modeset or after a suspend/resume.
Changes in V2:
- Fixed commit message
Changes in V3:
- Added mention of suspend/resume case back to commit message
Dmitry Baryshkov [Wed, 18 Jan 2023 03:17:15 +0000 (05:17 +0200)]
dt-bindings: display/msm: add qcom, sc8280xp-edp to list of eDP devices
Add qcom,sc8280xp-edp to the list of eDP devices, unblocking `aux-bus'
property and fobidding `#sound-dai-cells' property. Also since
sc8280xp-edp, overriding sc8280xp-dp, will contain 5 reg resources, drop
the reg contraint (as it will become equivalent to the top-level one,
requiring min 4 and max 5 reg entries).
Dmitry Baryshkov [Sun, 15 Jan 2023 14:00:22 +0000 (16:00 +0200)]
drm/msm/dpu: enable DPU_MDP_AUDIO_SELECT for sc8180x
According to the discussion ([1]) on the mailing list, platforms before
sm8250 (and derivatives) should program HDMI_DP_CORE_SELECT register to
route audio to the DP ports. Enable DPU_MDP_AUDIO_SELECT on sc8180x to
program correponding register.
Dmitry Baryshkov [Mon, 16 Jan 2023 06:33:14 +0000 (08:33 +0200)]
drm/msm/dpu: fix blend setup for DMA4 and DMA5 layers
SM8550 uses new register to map SSPP_DMA4 and SSPP_DMA5 units to blend
stages. Add proper support for this register to allow using these two
planes for image processing.
Fixes: efcd0107727c ("drm/msm/dpu: add support for SM8550") Cc: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550
Patchwork: https://patchwork.freedesktop.org/patch/518481/ Link: https://lore.kernel.org/r/20230116063316.728496-1-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Dmitry Baryshkov [Wed, 18 Jan 2023 04:12:33 +0000 (06:12 +0200)]
dt-bindings: display/msm: convert MDP5 schema to YAML format
Convert the mdp5.txt into the yaml format. Changes to the existing (txt) schema:
- MSM8996 has additional "iommu" clock, define it separately
- Add new properties used on some of platforms:
- interconnects, interconnect-names
- iommus
- power-domains
- operating-points-v2, opp-table
Bjorn Andersson [Tue, 17 Jan 2023 17:29:51 +0000 (09:29 -0800)]
drm/msm/dp: Remove INIT_SETUP delay
During initalization of the DisplayPort controller an EV_HPD_INIT_SETUP
event is generated, but with a delay of 100 units. This delay existed to
circumvent bug in the QMP combo PHY driver, where if the DP part was
powered up before USB, the common properties would not be properly
initialized - and USB wouldn't work.
This issue was resolved in the recent refactoring of the QMP driver,
so it's now possible to remove this delay.
While there is still a timing dependency in the current implementation,
test indicates that it's now possible to boot with an external display
on USB Type-C and have the display power up, without disconnecting and
reconnecting the cable.
Dmitry Baryshkov [Mon, 16 Jan 2023 03:44:35 +0000 (05:44 +0200)]
drm/msm/dpu: enable sourcesplit for sc7180/sc7280
According to the vendor dts files, both sc7180 and sc7280 support the
source split mode (using two LMs for a single output). Change these two
platforms to use MIXER_SDM845_MASK, which includes
DPU_MIXER_SOURCESPLIT. Rename MIXER_SC7180_MASK to MIXER_QCM2290_MASK,
since this platform doesn't seem to support source split mode.
Dmitry Baryshkov [Thu, 12 Jan 2023 05:36:59 +0000 (07:36 +0200)]
drm/msm/dpu: merge two CRTC debugfs dirs
For each CRTC we are creating two different debugfs directories one
using crtc index (created automatically for the CRC files) and another
one using CRTC name/object ID (for state and status files).
This can be confusing, so move our custom files to crtc->debugfs_entry,
effetively merging two debugfs dirs.
Marijn Suijten [Mon, 9 Jan 2023 23:15:55 +0000 (00:15 +0100)]
drm/msm/dpu: Disallow unallocated resources to be returned
In the event that the topology requests resources that have not been
created by the system (because they are typically not represented in
dpu_mdss_cfg ^1), the resource(s) in global_state (in this case DSC
blocks, until their allocation/assignment is being sanity-checked in
"drm/msm/dpu: Reject topologies for which no DSC blocks are available")
remain NULL but will still be returned out of
dpu_rm_get_assigned_resources, where the caller expects to get an array
containing num_blks valid pointers (but instead gets these NULLs).
To prevent this from happening, where null-pointer dereferences
typically result in a hard-to-debug platform lockup, num_blks shouldn't
increase past NULL blocks and will print an error and break instead.
After all, max_blks represents the static size of the maximum number of
blocks whereas the actual amount varies per platform.
^1: which can happen after a git rebase ended up moving additions to
_dpu_cfg to a different struct which has the same patch context.
Struct dpu_encoder_virt_ops is used to provide several callbacks to the
phys_enc backends. However these ops are static and are not supposed to
change in the foreseeble future. Drop the indirection and call
corresponding functions directly.
Jiasheng Jiang [Mon, 9 Jan 2023 02:20:38 +0000 (10:20 +0800)]
drm/msm: Add missing check and destroy for alloc_ordered_workqueue
Add check for the return value of alloc_ordered_workqueue as it may return
NULL pointer.
Moreover, use the destroy_workqueue in the later fails in order to avoid
memory leak.
Rob Clark [Tue, 10 Jan 2023 23:14:43 +0000 (15:14 -0800)]
drm/msm/gpu: Bypass PM QoS constraint for idle clamp
Change idle freq clamping back to the direct method, bypassing PM QoS
requests. The problem with using PM QoS requests is they call
(indirectly) the governors ->get_target_freq() which goes thru a
get_dev_status() cycle. The problem comes when the GPU becomes active
again and we remove the idle-clamp request, we go through another
get_dev_status() cycle for the period that the GPU has been idle, which
triggers the governor to lower the target freq excessively.
This partially reverts commit 7c0ffcd40b16 ("drm/msm/gpu: Respect PM QoS
constraints"), but preserves the use of boost QoS request, so that it
will continue to play nicely with other QoS requests such as a cooling
device. This also mostly undoes commit 78f815c1cf8f ("drm/msm: return the
average load over the polling period")
drm/msm/a2xx: support loading legacy (iMX) firmware
Support loading A200 firmware generated from the iMX firmware header
files. The firmware lacks protection support, however it allows GPU to
function properly while using the firmware files with clear license
which allows redistribution.
Cc: Jonathan Marek <jonathan@marek.ca> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Rob Clark <robdclark@gmail.com>
Patchwork: https://patchwork.freedesktop.org/patch/516443/ Link: https://lore.kernel.org/r/20230101155753.779176-1-dmitry.baryshkov@linaro.org Signed-off-by: Rob Clark <robdclark@chromium.org>
Rob Clark [Tue, 6 Dec 2022 19:21:23 +0000 (11:21 -0800)]
drm/msm: Add MSM_SUBMIT_BO_NO_IMPLICIT
In cases where implicit sync is used, it is still useful (for things
like sub-allocation, etc) to allow userspace to opt-out of implicit
sync on per-BO basis.
Marijn Suijten [Wed, 21 Dec 2022 23:19:43 +0000 (00:19 +0100)]
drm/msm/dpu: Add DSC configuration for SM8150 and SM8250
These DSC blocks on CTL V1 need to set its corresponding PINGPONG block
index in a hardware register to configure where to send pixel output to,
via the newly-added DPU_DSC_OUTPUT_CTRL feature flag.
Marijn Suijten [Wed, 21 Dec 2022 23:19:42 +0000 (00:19 +0100)]
drm/msm/dpu: Implement DSC binding to PP block for CTL V1
All V1 CTL blocks (active CTLs) explicitly bind the pixel output from a
DSC block to a PINGPONG block by setting the PINGPONG index in a DSC
hardware register.
Marijn Suijten [Wed, 21 Dec 2022 23:19:40 +0000 (00:19 +0100)]
drm/msm/dpu: Reject topologies for which no DSC blocks are available
Resource allocation of DSC blocks should behave more like LMs and CTLs
where NULL resources (based on initial hw_blk creation via definitions
in the catalog) are skipped ^1. The current hardcoded mapping of DSC
blocks however means that resource allocation shouldn't succeed at all
when the DSC block on the corresponding index doesn't exist, rather than
searching for the next free block.
This hardcoded mapping should be loosened separately as DPU 5.0.0
introduced a crossbar where DSC blocks can be "somewhat" freely bound to
any PP and CTL (in proper pairs).
^1: which, on hardware that supports DSC, can happen after a git rebase
ended up moving additions to _dpu_cfg to a different struct which has
the same patch context.
Marijn Suijten [Wed, 21 Dec 2022 23:19:38 +0000 (00:19 +0100)]
drm/msm/dsi: Flip greater-than check for slice_count and slice_per_intf
According to downstream /and the comment copied from it/ this comparison
should be the other way around. In other words, when the panel driver
requests to use more slices per packet than what could be sent over this
interface, it is bumped down to only use a single slice per packet (and
strangely not the number of slices that could fit on the interface).
Marijn Suijten [Wed, 21 Dec 2022 23:19:37 +0000 (00:19 +0100)]
drm/msm/dsi: Use DSC slice(s) packet size to compute word count
According to downstream the value to use for WORD_COUNT is
bytes_per_pkt, which denotes the number of bytes in a packet based on
how many slices have been configured by the panel driver times the
width of a slice times the number of bytes per pixel.
The DSC panels seen thus far use one byte per pixel, only one slice
per packet, and a slice width of half the panel width leading to the
desired bytes_per_pkt+1 value to be equal to hdisplay/2+1. This however
isn't the case anymore for panels that configure two slices per packet,
where the value should now be hdisplay+1.
Note that the aforementioned panel (on a Sony Xperia XZ3, sdm845) with
slice_count=1 has also been tested to successfully accept slice_count=2,
which would have shown corrupted output previously.
Marijn Suijten [Wed, 21 Dec 2022 23:19:36 +0000 (00:19 +0100)]
drm/msm/dpu: Wire up DSC mask for active CTL configuration
Active CTLs have to configure what DSC block(s) have to be enabled, and
what DSC block(s) have to be flushed; this value was initialized to zero
resulting in the necessary register writes to never happen (or would
write zero otherwise). This seems to have gotten lost in the DSC v4->v5
series while refactoring how the combination with merge_3d was handled.
Fixes: 58dca9810749 ("drm/msm/disp/dpu1: Add support for DSC in encoder") Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/515693/ Link: https://lore.kernel.org/r/20221221231943.1961117-2-marijn.suijten@somainline.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Bjorn Andersson [Wed, 7 Dec 2022 22:00:02 +0000 (14:00 -0800)]
drm/msm/dpu: Introduce SC8280XP
The Qualcomm SC8280XP platform contains DPU version 8.0.0, has 9
interfaces, 2 DSI controllers and 4 DisplayPort controllers. Extend the
necessary definitions and describe the DPU in the SC8280XP.
On sm8450 a register block was removed from MDP TOP. Accessing it during
snapshotting results in NoC errors / immediate reboot. Skip accessing
these registers during snapshot.
drm/msm/dpu: merge all MDP TOP registers to dpu_hwio.h
There is a separate header containing some of MDP TOP register
definitions, dpu_hwio.h. Move missing register definitions from
dpu_hw_top.c to the mentioned header.
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