Stefan Hajnoczi [Tue, 7 Dec 2021 13:23:31 +0000 (13:23 +0000)]
aio-posix: split poll check from ready handler
Adaptive polling measures the execution time of the polling check plus
handlers called when a polled event becomes ready. Handlers can take a
significant amount of time, making it look like polling was running for
a long time when in fact the event handler was running for a long time.
For example, on Linux the io_submit(2) syscall invoked when a virtio-blk
device's virtqueue becomes ready can take 10s of microseconds. This
can exceed the default polling interval (32 microseconds) and cause
adaptive polling to stop polling.
By excluding the handler's execution time from the polling check we make
the adaptive polling calculation more accurate. As a result, the event
loop now stays in polling mode where previously it would have fallen
back to file descriptor monitoring.
The following data was collected with virtio-blk num-queues=2
event_idx=off using an IOThread. Before:
Notice that ppoll(2) and eventfd read(2) syscalls are eliminated because
the IOThread stays in polling mode instead of falling back to file
descriptor monitoring.
As usual, polling is not implemented on Windows so this patch ignores
the new io_poll_read() callback in aio-win32.c.
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Stefano Garzarella <sgarzare@redhat.com>
Message-id: 20211207132336.36627-2-stefanha@redhat.com
[Fixed up aio_set_event_notifier() calls in
tests/unit/test-fdmon-epoll.c added after this series was queued.
--Stefan]
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
* remotes/lvivier-gitlab/tags/linux-user-for-7.0-pull-request: (30 commits)
linux-user: Implement capability prctls
linux-user: Implement PR_SET_PDEATHSIG
linux-user: Map signal number in PR_GET_PDEATHSIG
linux-user: Do not special-case NULL for PR_GET_PDEATHSIG
linux-user: Move target_struct.h generic definitions to generic/
linux-user/arm: Move target_oabi_flock64 out of target_structs.h
linux-user/xtensa: Use force_sig_fault
linux-user/sparc: Use force_sig_fault
linux-user/sh4: Use force_sig_fault
linux-user/s390x: Use force_sig_fault
linux-user/riscv: Use force_sig_fault
linux-user/ppc: Use force_sig_fault
linux-user/openrisc: Use force_sig_fault
target/mips: Extract trap code into env->error_code
target/mips: Extract break code into env->error_code
linux-user/mips: Use force_sig_fault
linux-user/mips: Improve do_break
linux-user/microblaze: Fix SIGFPE si_codes
linux-user/microblaze: Use force_sig_fault
linux-user/m68k: Use force_sig_fault
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Tue, 11 Jan 2022 08:29:00 +0000 (08:29 +0000)]
linux-user: Fix clang warning for nios2-linux-user code
The clang in Ubuntu 18.04 (10.0.0-4ubuntu1) produces a warning
on the code added in commit f5ef0e518d03 where we use a
shifted expression in a boolean context:
../../linux-user/elfload.c:2423:16: error: converting the result of '<<' to a boolean always evaluates to true [-Werror,-Wtautological-constant-compare]
} else if (LO_COMMPAGE) {
^
../../linux-user/elfload.c:1102:22: note: expanded from macro 'LO_COMMPAGE'
#define LO_COMMPAGE TARGET_PAGE_SIZE
^
/mnt/nvmedisk/linaro/qemu-from-laptop/qemu/include/exec/cpu-all.h:231:31: note: expanded from macro 'TARGET_PAGE_SIZE'
#define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS)
^
1 error generated.
The warning is bogus because whether LO_COMMPAGE is zero or not
depends on compile-time ifdefs; shut the compiler up by adding
an explicit comparison to zero.
Fixes: f5ef0e518d0331 ("linux-user/nios2: Map a real kuser page") Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Message-id: 20220111082900.3341274-1-peter.maydell@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
linux-user/arm: Move target_oabi_flock64 out of target_structs.h
Place it next to copy_from/to_user_oabi_flock64, the only users,
inside the existing target-specific ifdef. This leaves only
generic ipc structs in target_structs.h.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Message-Id: <20220107042600.149852-2-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Use the new function instead of setting up a target_siginfo_t
and calling queue_signal. Fix missing PC from EXCP_DEBUG by
merging the case with EXCP_BREAKPOINT.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220107213243.212806-21-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Use the new function instead of setting up a target_siginfo_t
and calling queue_signal. Fill in the missing PC for SIGTRAP.
The fault address for POWERPC_EXCP_ISI is nip exactly, not nip - 4.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220107213243.212806-20-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
target/mips: Extract break code into env->error_code
Simplify cpu_loop by doing all of the decode in translate.
This fixes a bug in that cpu_loop was not handling the
different layout of the R6 version of break16. This fixes
a bug in that cpu_loop extracted the wrong bits for the
mips16e break16 instruction.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220107213243.212806-17-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Use the new function instead of setting up a target_siginfo_t
and calling queue_signal. Fill in the missing PC for SIGTRAP
and SIGFPE; use force_sig (SI_KERNEL) for EXCP_DSPDIS.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220107213243.212806-16-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Rename to do_tr_or_bp, as per the kernel function.
Add a 'trap' argument, akin to the kernel's si_code, but clearer.
The return value is always 0, so change the return value to void.
Use force_sig and force_sig_fault.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220107213243.212806-15-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Use the new function instead of setting up a target_siginfo_t
and calling queue_signal. Fill in the missing PC for SIGTRAP
and missing si_code for SIGBUS.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220107213243.212806-6-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
* remotes/jsnow-gitlab/tags/python-pull-request:
simplebench: Fix Python syntax error (reported by LGTM)
python: update type hints for mypy 0.930
Python/aqmp: fix type definitions for mypy 0.920
python/aqmp: use absolute import statement
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Tue, 11 Jan 2022 11:39:31 +0000 (11:39 +0000)]
Merge remote-tracking branch 'remotes/philmd/tags/sdmmc-20220108' into staging
SD/MMC patches queue
- Add SDHC support for SD card SPI-mode (Frank Chang)
# gpg: Signature made Sat 08 Jan 2022 21:56:02 GMT
# gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE
* remotes/philmd/tags/sdmmc-20220108:
hw/sd: Add SDHC support for SD card SPI-mode
hw/sd/sdcard: Rename Write Protect Group variables
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Tue, 11 Jan 2022 10:12:29 +0000 (10:12 +0000)]
Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging
virtio: revert config interrupt changes
Lots of fallout from config interrupt changes. Author wants to rework
the patches. Let's revert quickly so others don't suffer meanwhile.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
# gpg: Signature made Mon 10 Jan 2022 21:03:44 GMT
# gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469
# gpg: issuer "mst@redhat.com"
# gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full]
# gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full]
# Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67
# Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469
* remotes/mst/tags/for_upstream:
Revert "virtio: introduce macro IRTIO_CONFIG_IRQ_IDX"
Revert "virtio-pci: decouple notifier from interrupt process"
Revert "virtio-pci: decouple the single vector from the interrupt process"
Revert "vhost: introduce new VhostOps vhost_set_config_call"
Revert "vhost-vdpa: add support for config interrupt"
Revert "virtio: add support for configure interrupt"
Revert "vhost: add support for configure interrupt"
Revert "virtio-net: add support for configure interrupt"
Revert "virtio-mmio: add support for configure interrupt"
Revert "virtio-pci: add support for configure interrupt"
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Stefan Weil [Fri, 7 Jan 2022 15:30:19 +0000 (16:30 +0100)]
simplebench: Fix Python syntax error (reported by LGTM)
Fixes: b2fcb0c5754c2554b8406376e99a75e9e0a6b7bd Signed-off-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: John Snow <jsnow@redhat.com>
Message-id: 20220107153019.504124-1-sw@weilnetz.de Signed-off-by: John Snow <jsnow@redhat.com>
John Snow [Mon, 10 Jan 2022 19:13:49 +0000 (14:13 -0500)]
python: update type hints for mypy 0.930
Mypy 0.930, released Dec 22, changes the way argparse objects are
considered. Crafting a definition that works under Python 3.6 and an
older mypy alongside newer versions simultaneously is ... difficult,
so... eh. Stub it out with an 'Any' definition to get the CI moving
again.
Oh well.
Signed-off-by: John Snow <jsnow@redhat.com> Reviewed-by: Beraldo Leal <bleal@redhat.com>
Message-id: 20220110191349.1841027-4-jsnow@redhat.com Signed-off-by: John Snow <jsnow@redhat.com>
John Snow [Mon, 10 Jan 2022 19:13:47 +0000 (14:13 -0500)]
python/aqmp: use absolute import statement
pylint's dependency astroid appears to have bugs in 2.9.1 and 2.9.2 (Dec
31 and Jan 3) that appear to erroneously expect the qemu namespace to
have an __init__.py file. astroid 2.9.3 (Jan 9) avoids that problem, but
appears to not understand a relative import within a namespace package.
Update the relative import - it was worth changing anyway, because these
packages will eventually be packaged and distributed separately.
Signed-off-by: John Snow <jsnow@redhat.com> Reviewed-by: Beraldo Leal <bleal@redhat.com>
Message-id: 20220110191349.1841027-2-jsnow@redhat.com Signed-off-by: John Snow <jsnow@redhat.com>
Fixes: 316011b8a7 ("virtio-pci: decouple the single vector from the interrupt process") Cc: "Cindy Lu" <lulu@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Fixes: 497679d510 ("virtio-net: add support for configure interrupt") Cc: "Cindy Lu" <lulu@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Fixes: d48185f1a4 ("virtio-mmio: add support for configure interrupt") Cc: "Cindy Lu" <lulu@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Fixes: d5d24d859c ("virtio-pci: add support for configure interrupt") Cc: "Cindy Lu" <lulu@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
target/m68k: don't word align SP in stack frame if M68K_FEATURE_UNALIGNED_DATA feature enabled
Commit a9431a03f7 ("target/m68k: add M68K_FEATURE_UNALIGNED_DATA feature") added
a new feature for processors from the 68020 onwards which do not require data
accesses to be word aligned.
Unfortunately the original commit missed an additional case whereby the SP is
still word aligned when setting up an additional format 1 stack frame so add the
necessary M68K_FEATURE_UNALIGNED_DATA feature guard.
The macfb VRAM memory region was configured with coalescing rather than dirty
memory logging enabled, causing some areas of the screen not to redraw after
a full screen update.
Laurent Vivier [Fri, 7 Jan 2022 10:50:49 +0000 (11:50 +0100)]
q800: fix segfault with invalid MacROM
"qemu-system-m68k -M q800 -bios /dev/null" crashes with a segfault
in q800_init().
This happens because the code doesn't check that rom_ptr() returned
a non-NULL pointer .
To avoid NULL pointer, don't allow 0 sized file and use bios_size with
rom_ptr().
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/756 Reported-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20220107105049.961489-1-laurent@vivier.eu> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Merge tag 'bsd-user-arm-pull-request' of gitlab.com:bsdimp/qemu into staging
bsd-user: arm (32-bit) support
This series of patches brings in 32-bit arm support for bsd-user. It implements
all the bits needed to do image activation, signal handling, stack management
and threading. This allows us to get to the "Hello World" level. The arm and x86
code are now the same as in the bsd-user fork. For full context, the fork is at
https://github.com/qemu-bsd-user/qemu-bsd-user/tree/blitz (though the the recent
sig{bus,segv} needed updates are incomplete).
v5 changes:
o Moved to using the CPUArchState typedef and move
set_sigtramp_args, get_mcontext, set_mcontext, and
get_ucontext_sigreturn prototypes to
bsd-user/freebsd/target_os_ucontext.h
o Fix issues with arm's set_mcontext related to masking
and remove an unnecessary check.
We're down to only one hunk needing review:
bsd-user/arm/target_arch_signal.c: arm set_mcontext
Warnings that should be ignored:
o make checkpatch has a couple of complaints about the comments for the
signal trampoline, since it's a false positive IMHO.
WARNING: Block comments use a leading /* on a separate line
+ /* 8 */ sys_sigreturn,
WARNING: Block comments use a leading /* on a separate line
+ /* 9 */ sys_exit
# gpg: Signature made Fri 07 Jan 2022 11:36:37 PM PST
# gpg: using RSA key 2035F894B00AA3CF7CCDE1B76C1CD1287DB01100
# gpg: Good signature from "Warner Losh <wlosh@netflix.com>" [unknown]
# gpg: aka "Warner Losh <imp@bsdimp.com>" [unknown]
# gpg: aka "Warner Losh <imp@freebsd.org>" [unknown]
# gpg: aka "Warner Losh <imp@village.org>" [unknown]
# gpg: aka "Warner Losh <wlosh@bsdimp.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 2035 F894 B00A A3CF 7CCD E1B7 6C1C D128 7DB0 1100
* tag 'bsd-user-arm-pull-request' of gitlab.com:bsdimp/qemu: (37 commits)
bsd-user: add arm target build
bsd-user/freebsd/target_os_ucontext.h: Require TARGET_*CONTEXT_SIZE
bsd-user/arm/signal.c: arm get_ucontext_sigreturn
bsd-user/arm/signal.c: arm set_mcontext
bsd-user/arm/signal.c: arm get_mcontext
bsd-user/arm/signal.c: arm set_sigtramp_args
bsd-user/arm/target_arch_signal.h: Define size of *context_t
bsd-user/arm/target_arch_signal.h: arm machine context and trapframe for signals
bsd-user/arm/target_arch_signal.h: arm specific signal registers and stack
bsd-user/arm/target_arch_elf.h: arm get_hwcap2 impl
bsd-user/arm/target_arch_elf.h: arm get hwcap
bsd-user/arm/target_arch_elf.h: arm defines for ELF
bsd-user/arm/target_arch_thread.h: Routines to create and switch to a thread
bsd-user/arm/target_arch_sigtramp.h: Signal Trampoline for arm
bsd-user/arm/target_arch_vmparam.h: Parameters for arm address space
bsd-user/arm/target_arch_reg.h: Implement core dump register copying
bsd-user/arm/target_arch_cpu.h: Implement system call dispatch
bsd-user/arm/target_arch_cpu.h: Implement data abort exceptions
bsd-user/arm/target_arch_cpu.h: Implement trivial EXCP exceptions
bsd-user/arm/target_arch_cpu.h: Dummy target_cpu_loop implementation
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Merge tag 'pull-riscv-to-apply-20220108' of github.com:alistair23/qemu into staging
Second RISC-V PR for QEMU 7.0
- Fix illegal instruction when PMP is disabled
- SiFive PDMA 64-bit support
- SiFive PLIC cleanups
- Mark Hypervisor extension as non experimental
- Enable Hypervisor extension by default
- Support 32 cores on the virt machine
- Corrections for the Vector extension
- Experimental support for 128-bit CPUs
- stval and mtval support for illegal instructions
# gpg: Signature made Fri 07 Jan 2022 09:50:11 PM PST
# gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054
* tag 'pull-riscv-to-apply-20220108' of github.com:alistair23/qemu: (37 commits)
target/riscv: Implement the stval/mtval illegal instruction
target/riscv: Fixup setting GVA
target/riscv: Set the opcode in DisasContext
target/riscv: actual functions to realize crs 128-bit insns
target/riscv: modification of the trans_csrxx for 128-bit support
target/riscv: helper functions to wrap calls to 128-bit csr insns
target/riscv: adding high part of some csrs
target/riscv: support for 128-bit M extension
target/riscv: support for 128-bit arithmetic instructions
target/riscv: support for 128-bit shift instructions
target/riscv: support for 128-bit U-type instructions
target/riscv: support for 128-bit bitwise instructions
target/riscv: accessors to registers upper part and 128-bit load/store
target/riscv: moving some insns close to similar insns
target/riscv: setup everything for rv64 to support rv128 execution
target/riscv: array for the 64 upper bits of 128-bit registers
target/riscv: separation of bitwise logic and arithmetic helpers
target/riscv: additional macros to check instruction support
qemu/int128: addition of div/rem 128-bit operations
exec/memop: Adding signed quad and octo defines
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Warner Losh [Thu, 4 Nov 2021 23:08:04 +0000 (17:08 -0600)]
bsd-user/arm/target_arch_signal.h: Define size of *context_t
Define the native sizes of mcontext_t and ucontext_t so that the tests
in target_os_ucontext.h ensure the size of arm's version of these
structures is correct.
Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Warner Losh [Thu, 23 Sep 2021 15:12:12 +0000 (09:12 -0600)]
bsd-user/arm/target_arch_vmparam.h: Parameters for arm address space
Various parameters describing the layout of the ARM address space. In
addition, define routines to get the stack pointer and to set the second
return value.
Signed-off-by: Stacey Son <sson@FreeBSD.org> Signed-off-by: Kyle Evans <kevans@FreeBSD.org> Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Kyle Evans <kevans@FreeBSD.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Warner Losh [Thu, 23 Sep 2021 15:08:21 +0000 (09:08 -0600)]
bsd-user/arm/target_arch_cpu.h: Implement system call dispatch
Implement the system call dispatch. This implements all three kinds of
system call: direct and the two indirect variants. It handles all the
special cases for thumb as well.
Signed-off-by: Stacey Son <sson@FreeBSD.org> Signed-off-by: Kyle Evans <kevans@FreeBSD.org> Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Kyle Evans <kevans@FreeBSD.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Implement EXCP_UDEF, EXCP_DEBUG, EXCP_INTERRUPT, EXCP_ATOMIC and
EXCP_YIELD. The first two generate a signal to the emulated
binary. EXCP_ATOMIC handles atomic operations. The remainder are fancy
nops.
Signed-off-by: Stacey Son <sson@FreeBSD.org> Signed-off-by: Mikaël Urankar <mikael.urankar@gmail.com> Signed-off-by: Kyle Evans <kevans@FreeBSD.org> Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Add a boiler plate CPU loop that does nothing except return an error for
all traps.
Signed-off-by: Sean Bruno <sbruno@FreeBSD.org> Signed-off-by: Stacey Son <sson@FreeBSD.org> Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Kyle Evans <kevans@FreeBSD.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Warner Losh [Thu, 23 Sep 2021 14:29:39 +0000 (08:29 -0600)]
bsd-user/arm/target_syscall.h: Add copyright and update name
The preferred name for the 32-bit arm is now armv7. Update the name to
reflect that. In addition, add Stacey's copyright to this file and
update the include guards to the new convention.
Signed-off-by: Stacey Son <sson@FreeBSD.org> Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Kyle Evans <kevans@FreeBSD.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Warner Losh [Thu, 4 Nov 2021 22:34:48 +0000 (16:34 -0600)]
bsd-user: create a per-arch signal.c file
Create a place-holder signal.c file for each of the architectures that
are currently built. In the future, some code that's currently inlined
in target_arch_signal.h will live here.
Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Warner Losh [Fri, 29 Oct 2021 14:39:01 +0000 (08:39 -0600)]
bsd-user/freebsd: Create common target_os_ucontext.h file
FreeBSD has a MI ucontext structure that contains the MD mcontext
machine state and other things that are machine independent. Create an
include file for all the ucontext stuff. It needs to be included in the
arch specific files after target_mcontext is defined. This is largely
copied from sys/_ucontext.h with the comments about layout removed
because we don't support ancient FreeBSD binaries.
Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Warner Losh [Thu, 4 Nov 2021 22:31:27 +0000 (16:31 -0600)]
bsd-user/mips*: Remove mips support
FreeBSD is dropping support for mips starting with FreeBSD 14. mips
support has been removed from the bsd-user fork because updating it for
new signal requirements will take too much time. Remove it here since it
is a distraction.
Signed-off-by: Warner Losh <imp@bsdimp.com> Acked-by: Richard Henderson <richard.henderson@linaro.org>
Alistair Francis [Mon, 20 Dec 2021 06:49:16 +0000 (16:49 +1000)]
target/riscv: Implement the stval/mtval illegal instruction
The stval and mtval registers can optionally contain the faulting
instruction on an illegal instruction exception. This patch adds support
for setting the stval and mtval registers.
The RISC-V spec states that "The stval register can optionally also be
used to return the faulting instruction bits on an illegal instruction
exception...". In this case we are always writing the value on an
illegal instruction.
This doesn't match all CPUs (some CPUs won't write the data), but in
QEMU let's just populate the value on illegal instructions. This won't
break any guest software, but will provide more information to guests.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20211220064916.107241-4-alistair.francis@opensource.wdc.com
Alistair Francis [Mon, 20 Dec 2021 06:49:15 +0000 (16:49 +1000)]
target/riscv: Fixup setting GVA
In preparation for adding support for the illegal instruction address
let's fixup the Hypervisor extension setting GVA logic and improve the
variable names.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20211220064916.107241-3-alistair.francis@opensource.wdc.com
Alistair Francis [Mon, 20 Dec 2021 06:49:14 +0000 (16:49 +1000)]
target/riscv: Set the opcode in DisasContext
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20211220064916.107241-2-alistair.francis@opensource.wdc.com
Frédéric Pétrot [Thu, 6 Jan 2022 21:01:08 +0000 (22:01 +0100)]
target/riscv: actual functions to realize crs 128-bit insns
The csrs are accessed through function pointers: we add 128-bit read
operations in the table for three csrs (writes fallback to the
64-bit version as the upper 64-bit information is handled elsewhere):
- misa, as mxl is needed for proper operation,
- mstatus and sstatus, to return sd
In addition, we also add read and write accesses to the machine and
supervisor scratch registers.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220106210108.138226-19-frederic.petrot@univ-grenoble-alpes.fr Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frédéric Pétrot [Thu, 6 Jan 2022 21:01:07 +0000 (22:01 +0100)]
target/riscv: modification of the trans_csrxx for 128-bit support
As opposed to the gen_arith and gen_shift generation helpers, the csr insns
do not have a common prototype, so the choice to generate 32/64 or 128-bit
helper calls is done in the trans_csrxx functions.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220106210108.138226-18-frederic.petrot@univ-grenoble-alpes.fr Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frédéric Pétrot [Thu, 6 Jan 2022 21:01:06 +0000 (22:01 +0100)]
target/riscv: helper functions to wrap calls to 128-bit csr insns
Given the side effects they have, the csr instructions are realized as
helpers. We extend this existing infrastructure for 128-bit sized csr.
We return 128-bit values using the same approach as for div/rem.
Theses helpers all call a unique function that is currently a fallback
on the 64-bit version.
The trans_csrxx functions supporting 128-bit are yet to be implemented.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220106210108.138226-17-frederic.petrot@univ-grenoble-alpes.fr Signed-off-by: Alistair Francis <alistair.francis@wdc.com>