Fabiano Rosas [Fri, 28 Jan 2022 12:15:04 +0000 (13:15 +0100)]
target/ppc: Simplify powerpc_excp_40x
Differences from the generic powerpc_excp code:
- Not BookE, so some MSR bits are cleared at interrupt dispatch;
- No MSR_HV or MSR_LE;
- No power saving states;
- No Hypervisor Emulation Assistance;
- Not 64 bits;
- No System call vectored;
- No Interrupts Little Endian;
- No Alternate Interrupt Location.
Cédric Le Goater [Fri, 28 Jan 2022 12:15:03 +0000 (13:15 +0100)]
ppc/ppc405: Fix TLB flushing
Commit cd0c6f473532 did not take into account 405 CPUs when adding
support to batching of TCG tlb flushes. Set the TLB_NEED_LOCAL_FLUSH
flag when the SPR_40x_PID is set or a TLB updated.
Cc: Thomas Huth <thuth@redhat.com> Cc: Christophe Leroy <christophe.leroy@csgroup.eu> Cc: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com> Fixes: cd0c6f473532 ("ppc: Do some batching of TCG tlb flushes") Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220113180352.1234512-1-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
vof.h requires "qom/object.h" for DECLARE_CLASS_CHECKERS(),
"exec/memory.h" for address_space_read/write(),
"exec/address-spaces.h" for address_space_memory
and more importantly "cpu.h" for target_ulong.
vof.c doesn't need "exec/ram_addr.h".
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220122003104.84391-1-f4bug@amsat.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
spapr.c: check bus != NULL in spapr_get_fw_dev_path()
spapr_get_fw_dev_path() is an impl of
FWPathProviderClass::get_dev_path(). This interface is used by
hw/core/qdev-fw.c via fw_path_provider_try_get_dev_path() in two
functions:
- static char *qdev_get_fw_dev_path_from_handler(), which is used only in
qdev_get_fw_dev_path_helper() and it's guarded by "if (dev &&
dev->parent_bus)";
- char *qdev_get_own_fw_dev_path_from_handler(), which is used in
softmmu/bootdevice.c in get_boot_device_path() like this:
if (dev) {
d = qdev_get_own_fw_dev_path_from_handler(dev->parent_bus, dev);
This means that, when called via softmmu/bootdevice.c, there's no check
of 'dev->parent_bus' being not NULL. The result is that the "BusState
*bus" arg of spapr_get_fw_dev_path() can potentially be NULL and if, at
the same time, "SCSIDevice *d" is not NULL, we'll hit this line:
target/ppc: fix 'skip KVM' cond in cpu_interrupt_exittb()
cpu_interrupt_exittb() was introduced by commit 044897ef4a22
("target/ppc: Fix system lockups caused by interrupt_request state
corruption") as a way to wrap cpu_interrupt() helper in BQL.
After that, commit 6d38666a8931 ("ppc: Ignore the CPU_INTERRUPT_EXITTB
interrupt with KVM") added a condition to skip this interrupt if we're
running with KVM.
Problem is that the change made by the above commit, testing for
!kvm_enabled() at the start of cpu_interrupt_exittb():
static inline void cpu_interrupt_exittb(CPUState *cs)
{
if (!kvm_enabled()) {
return;
}
(... do cpu_interrupt(cs, CPU_INTERRUPT_EXITTB) ...)
is doing the opposite of what it intended to do. This will return
immediately if not kvm_enabled(), i.e. it's a emulated CPU, and if
kvm_enabled() it will proceed to fire CPU_INTERRUPT_EXITTB.
Fix the 'skip KVM' condition so the function is a no-op when
kvm_enabled().
CC: Greg Kurz <groug@kaod.org>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/809 Fixes: 6d38666a8931 ("ppc: Ignore the CPU_INTERRUPT_EXITTB interrupt with KVM") Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: Greg Kurz <groug@kaod.org>
Message-Id: <20220121160841.9102-1-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Cédric Le Goater [Fri, 28 Jan 2022 12:15:02 +0000 (13:15 +0100)]
ppc/xive: check return value of ldq_be_dma()
The ldq_be_dma() routine was recently changed to return a result of
the transaction. Use it when loading the virtual structure descriptors
in the XIVE PowerNV model.
Cc: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220124081635.3672439-1-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
ppc/pnv: use a do-while() loop in pnv_phb4_translate_tve()
pnv_phb4_translate_tve() is quite similar to pnv_phb3_translate_tve(),
and that includes the fact that 'taddr' can be considered uninitialized
when throwing the "TCE access fault" error because, in theory, the loop
that sets 'taddr' can be skippable due to 'lev' being an signed int.
No one complained about this specific case yet, but since we took the
time to handle the same situtation in pnv_phb3_translate_tve(), let's
replicate it here as well.
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20220127122234.842145-3-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
ppc/pnv: use a do-while() loop in pnv_phb3_translate_tve()
The 'taddr' variable is left unintialized, being set only inside the
"while ((lev--) >= 0)" loop where we get the TCE address. The 'lev' var
is an int32_t that is being initiliazed by the GETFIELD() macro, which
returns an uint64_t.
For a human reader this means that 'lev' will always be positive or zero.
But some compilers may beg to differ. 'lev' being an int32_t can in theory
be set as negative, and the "while ((lev--) >= 0)" loop might never be
reached, and 'taddr' will be left unitialized. This can cause phb3_error()
to use 'taddr' uninitialized down below:
if ((is_write & !(tce & 2)) || ((!is_write) && !(tce & 1))) {
phb3_error(phb, "TCE access fault at 0x%"PRIx64, taddr);
A quick way of fixing it is to use a do/while() loop. This will keep the
same semanting as the existing while() loop does and the compiler will
understand that 'taddr' will be initialized at least once.
Suggested-by: Matheus K. Ferst <matheus.ferst@eldorado.org.br>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/573 Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220127122234.842145-2-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Vitaly Cheptsov [Fri, 28 Jan 2022 12:15:02 +0000 (13:15 +0100)]
target/ppc/mmu_common: Fix SRR1/MSR error code on Book-E
Book-E architecture does not set the error code in 31:27 bits
of SRR1, but instead uses these bits for custom fields such
as GS (Guest Supervisor).
Wrongly setting these fields will result in QEMU crashes
when attempting to execute not executable code due to the attempts
to use Guest Supervisor mode.
Cc: "Cédric Le Goater" <clg@kaod.org> Cc: Daniel Henrique Barboza <danielhb413@gmail.com> Cc: David Gibson <david@gibson.dropbear.id.au> Cc: Greg Kurz <groug@kaod.org> Cc: qemu-ppc@nongnu.org Cc: qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org Signed-off-by: Vitaly Cheptsov <cheptsov@ispras.ru> Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220121093107.15478-1-cheptsov@ispras.ru> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Christophe Leroy [Fri, 28 Jan 2022 12:15:01 +0000 (13:15 +0100)]
target/ppc: 603: fix restore of GPRs 0-3 on rfi
After a TLB miss exception, GPRs 0-3 must be restored on rfi.
This is managed by hreg_store_msr() which is called by do_rfi()
However, hreg_store_msr() does it if MSR[TGPR] is unset in the
passed MSR value.
The problem is that do_rfi() is given the content of SRR1 as
the value to be set in MSR, but TGPR bit is not part of SRR1
and that bit is used for something else and is sometimes set
to 1, leading to hreg_store_msr() not restoring GPRs.
So, do the same way as for POW bit, force clearing it.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Cc: Cedric Le Goater <clg@kaod.org> Cc: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220120103824.239573-1-christophe.leroy@csgroup.eu> Signed-off-by: Cédric Le Goater <clg@kaod.org>
"PowerPC Processor binding to IEEE 1275" says in
"8.2.1. Initial Register Values" that the initial state is defined as
32bit so do it for both SLOF and VOF.
This should not cause behavioral change as SLOF switches to 64bit very
early anyway. As nothing enforces LE anywhere, this drops it for VOF.
The goal is to make VOF work with TCG as otherwise it barfs with
qemu: fatal: TCG hflags mismatch (current:0x6c000004 rebuilt:0x6c000000)
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220107072423.2278113-1-aik@ozlabs.ru> Signed-off-by: Cédric Le Goater <clg@kaod.org>
We don't generate trace events for tests/ and qga/ because that it is
not simple and not necessary. We have corresponding comments in both
tests/meson.build and qga/meson.build.
Still to not miss possible future qapi code generation call, and not to
forget to enable trace events generation, let's enable it by default.
So, turn option --gen-trace into opposite --no-trace-events and use new
option only in tests/ and qga/ where we already have good comments why
we don't generate trace events code.
Note that this commit enables trace-events generation for qapi-gen.py
call from tests/qapi-schema/meson.build and storage-daemon/meson.build.
Still, both are kind of noop: tests/qapi-schema/ doesn't seem to
generate any QMP command code and no .trace-events files anyway,
storage-daemon/ uses common QMP command implementations and just
generate empty .trace-events
Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Message-Id: <20220126161130.3240892-8-vsementsov@virtuozzo.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
meson: document why we don't generate trace events for tests/ and qga/
Making trace generation work for tests/ and qga/ would involve some
Meson hackery to ensure we generate the trace-events files before
trace-tool uses them. Since we don't actually support tracing there
anyway, we bypass that problem.
Let's add corresponding comments.
Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Message-Id: <20220126161130.3240892-7-vsementsov@virtuozzo.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com>
[Pasto fixed, commit message punctuation tidied up] Signed-off-by: Markus Armbruster <armbru@redhat.com>
docs/qapi-code-gen: update to cover trace events code generation
Previous commits enabled trace events generation for most of QAPI
generated code (except for tests/ and qga/). Let's update documentation
to illustrate it.
Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Message-Id: <20220126161130.3240892-6-vsementsov@virtuozzo.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
1. Use --gen-trace when generate qmp commands
2. Add corresponding .trace-events files as outputs in qapi_files
custom target
3. Define global qapi_trace_events list of .trace-events file targets,
to fill in trace/qapi.build and to use in trace/meson.build
4. In trace/meson.build use the new array as an additional source of
.trace_events files to be processed
Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Message-Id: <20220126161130.3240892-5-vsementsov@virtuozzo.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
qapi/commands: Optionally generate trace for QMP commands
Add trace generation disabled by default and new option --gen-trace to
enable it. The next commit will enable it for qapi/, but not for qga/
and tests/. Making it work for the latter two would involve some Meson
hackery to ensure we generate the trace-events files before trace-tool
uses them. Since we don't actually support tracing there, we'll bypass
that problem.
Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Message-Id: <20220126161130.3240892-4-vsementsov@virtuozzo.com> Reviewed-by: Markus Armbruster <armbru@redhat.com>
[Superfluous #include dropped] Signed-off-by: Markus Armbruster <armbru@redhat.com>
Move error_propagate() to if (err) and make "if (err)" block mandatory.
This is to simplify further commit, which will bring trace events
generation for QMP commands.
Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Message-Id: <20220126161130.3240892-3-vsementsov@virtuozzo.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
We are going to generate trace events for QMP commands. We should
generate both trace_*() function calls and trace-events files listing
events for trace generator.
So, add an output module FOO.trace-events for each FOO schema module.
Since we're going to add trace events only to command marshallers,
make the trace-events output optional, so we don't generate so many
useless empty files.
Currently nobody set add_trace_events to True, so new functionality is
disabled. It will be enabled for QAPISchemaGenCommandVisitor
in a further commit.
Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Message-Id: <20220126161130.3240892-2-vsementsov@virtuozzo.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Victor Toso <victortoso@redhat.com>
Message-Id: <20211220145624.52801-1-victortoso@redhat.com> Acked-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
Vivek Goyal [Tue, 25 Jan 2022 18:51:14 +0000 (13:51 -0500)]
virtiofsd: Drop membership of all supplementary groups (CVE-2022-0358)
At the start, drop membership of all supplementary groups. This is
not required.
If we have membership of "root" supplementary group and when we switch
uid/gid using setresuid/setsgid, we still retain membership of existing
supplemntary groups. And that can allow some operations which are not
normally allowed.
For example, if root in guest creates a dir as follows.
$ mkdir -m 03777 test_dir
This sets SGID on dir as well as allows unprivileged users to write into
this dir.
And now as unprivileged user open file as follows.
$ su test
$ fd = open("test_dir/priviledge_id", O_RDWR|O_CREAT|O_EXCL, 02755);
This will create SGID set executable in test_dir/.
And that's a problem because now an unpriviliged user can execute it,
get egid=0 and get access to resources owned by "root" group. This is
privilege escalation.
Fixes: https://bugzilla.redhat.com/show_bug.cgi?id=2044863 Fixes: CVE-2022-0358 Reported-by: JIETAO XIAO <shawtao1125@gmail.com> Suggested-by: Miklos Szeredi <mszeredi@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Signed-off-by: Vivek Goyal <vgoyal@redhat.com>
Message-Id: <YfBGoriS38eBQrAb@redhat.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
dgilbert: Fixed missing {}'s style nit
John Snow [Mon, 10 Jan 2022 23:28:58 +0000 (18:28 -0500)]
scripts/cpu-x86-uarch-abi: switch to AQMP
Signed-off-by: John Snow <jsnow@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Reviewed-by: Beraldo Leal <bleal@redhat.com>
John Snow [Mon, 10 Jan 2022 23:28:57 +0000 (18:28 -0500)]
scripts/cpu-x86-uarch-abi: fix CLI parsing
Signed-off-by: John Snow <jsnow@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
John Snow [Mon, 10 Jan 2022 23:28:54 +0000 (18:28 -0500)]
python: move qmp utilities to python/qemu/utils
In order to upload a QMP package to PyPI, I want to remove any scripts
that I am not 100% confident I want to support upstream, beyond our
castle walls.
Move most of our QMP utilities into the utils package so we can split
them out from the PyPI upload.
Signed-off-by: John Snow <jsnow@redhat.com> Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Reviewed-by: Beraldo Leal <bleal@redhat.com>
John Snow [Mon, 10 Jan 2022 23:28:51 +0000 (18:28 -0500)]
python/qmp: switch qemu-ga-client to AQMP
Async QMP always raises a "ConnectError" on any connection error which
houses the cause in a second exception. We can check if this root cause
was python's ConnectionError to determine a fairly similar condition to
the original error check here.
Signed-off-by: John Snow <jsnow@redhat.com> Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Reviewed-by: Beraldo Leal <bleal@redhat.com>
John Snow [Mon, 10 Jan 2022 23:28:50 +0000 (18:28 -0500)]
python/qemu-ga-client: don't use deprecated CLI syntax in usage comment
Cleanup related to commit ccd3b3b8112b670f, "qemu-option: warn for
short-form boolean options".
Signed-off-by: John Snow <jsnow@redhat.com> Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
John Snow [Mon, 10 Jan 2022 23:28:49 +0000 (18:28 -0500)]
python/aqmp: rename AQMPError to QMPError
This is in preparation for renaming qemu.aqmp to qemu.qmp. I should have
done this from this from the very beginning, but it's a convenient time
to make sure this churn is taken care of.
Signed-off-by: John Snow <jsnow@redhat.com> Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
John Snow [Mon, 10 Jan 2022 23:28:47 +0000 (18:28 -0500)]
python/aqmp: copy type definitions from qmp
Copy the remaining type definitions from QMP into the qemu.aqmp.legacy
module. Now, users that require the legacy interface don't need to
import anything else but qemu.aqmp.legacy wrapper.
Signed-off-by: John Snow <jsnow@redhat.com> Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Reviewed-by: Beraldo Leal <bleal@redhat.com>
John Snow [Mon, 10 Jan 2022 23:28:45 +0000 (18:28 -0500)]
python/aqmp: add __del__ method to legacy interface
asyncio can complain *very* loudly if you forget to back out of things
gracefully before the garbage collector starts destroying objects that
contain live references to asyncio Tasks.
The usual fix is just to remember to call aqmp.disconnect(), but for the
sake of the legacy wrapper and quick, one-off scripts where a graceful
shutdown is not necessarily of paramount imporance, add a courtesy
cleanup that will trigger prior to seeing screenfuls of confusing
asyncio tracebacks.
Note that we can't *always* save you from yourself; depending on when
the GC runs, you might just seriously be out of luck. The best we can do
in this case is to gently remind you to clean up after yourself.
(Still much better than multiple pages of incomprehensible python
warnings for the crime of forgetting to put your toys away.)
Signed-off-by: John Snow <jsnow@redhat.com> Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Reviewed-by: Beraldo Leal <bleal@redhat.com>
John Snow [Wed, 19 Jan 2022 19:39:13 +0000 (14:39 -0500)]
python: use avocado's "new" runner
The old legacy runner no longer seems to work with output logging, so we
can't see failure logs when a test case fails. The new runner doesn't
(seem to) support Coverage.py yet, but seeing error output is a more
important feature.
Signed-off-by: John Snow <jsnow@redhat.com> Reviewed-by: Beraldo Leal <bleal@redhat.com>
Message-id: 20220119193916.4138217-3-jsnow@redhat.com Signed-off-by: John Snow <jsnow@redhat.com>
John Snow [Fri, 21 Jan 2022 00:52:21 +0000 (19:52 -0500)]
python: pin setuptools below v60.0.0
setuptools is a package that replaces the python stdlib 'distutils'. It
is generally installed by all venv-creating tools "by default". It isn't
actually needed at runtime for the qemu package, so our own setup.cfg
does not mention it as a dependency.
However, tox will create virtual environments that include it, and will
upgrade it to the very latest version. the 'venv' tool will also include
whichever version your host system happens to have.
Unfortunately, setuptools version 60.0.0 and above include a hack to
forcibly overwrite python's built-in distutils. The pylint tool that we
use to run code analysis checks on this package relies on distutils and
suffers regressions when setuptools >= 60.0.0 is present at all, see
https://github.com/PyCQA/pylint/issues/5704
Instruct tox and the 'check-dev' targets to avoid setuptools packages
that are too new, for now. Pipenv is unaffected, because setuptools 60
does not offer Python 3.6 support, and our pipenv config is pinned
against Python 3.6.
Signed-off-by: John Snow <jsnow@redhat.com> Reviewed-by: Beraldo Leal <bleal@redhat.com> Reviewed-by: Cleber Rosa <crosa@redhat.com> Tested-by: Cleber Rosa <crosa@redhat.com>
Message-id: 20220121005221.142236-1-jsnow@redhat.com Signed-off-by: John Snow <jsnow@redhat.com>
Peter Maydell [Fri, 21 Jan 2022 10:31:25 +0000 (10:31 +0000)]
Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20220121-1' into staging
Third RISC-V PR for QEMU 7.0
* Fixes for OpenTitan timer
* Correction of OpenTitan PLIC stride length
* RISC-V KVM support
* Device tree code cleanup
* Support for the Zve64f and Zve32f extensions
* OpenSBI binary loading support for the Spike machine
* Removal of OpenSBI ELFs
* Support for the UXL field in xstatus
# gpg: Signature made Fri 21 Jan 2022 05:57:09 GMT
# gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054
* remotes/alistair/tags/pull-riscv-to-apply-20220121-1: (61 commits)
target/riscv: Relax UXL field for debugging
target/riscv: Enable uxl field write
target/riscv: Set default XLEN for hypervisor
target/riscv: Adjust scalar reg in vector with XLEN
target/riscv: Adjust vector address with mask
target/riscv: Fix check range for first fault only
target/riscv: Remove VILL field in VTYPE
target/riscv: Adjust vsetvl according to XLEN
target/riscv: Split out the vill from vtype
target/riscv: Split pm_enabled into mask and base
target/riscv: Calculate address according to XLEN
target/riscv: Alloc tcg global for cur_pm[mask|base]
target/riscv: Create current pm fields in env
target/riscv: Adjust csr write mask with XLEN
target/riscv: Relax debug check for pm write
target/riscv: Use gdb xml according to max mxlen
target/riscv: Extend pc for runtime pc write
target/riscv: Ignore the pc bits above XLEN
target/riscv: Create xl field in env
target/riscv: Sign extend pc for different XLEN
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
LIU Zhiwei [Thu, 20 Jan 2022 12:20:50 +0000 (20:20 +0800)]
target/riscv: Relax UXL field for debugging
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-24-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
LIU Zhiwei [Thu, 20 Jan 2022 12:20:49 +0000 (20:20 +0800)]
target/riscv: Enable uxl field write
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-23-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
LIU Zhiwei [Thu, 20 Jan 2022 12:20:48 +0000 (20:20 +0800)]
target/riscv: Set default XLEN for hypervisor
When swap regs for hypervisor, the value of vsstatus or mstatus_hs
should have the right XLEN. Otherwise, it will propagate to mstatus.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-22-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
LIU Zhiwei [Thu, 20 Jan 2022 12:20:47 +0000 (20:20 +0800)]
target/riscv: Adjust scalar reg in vector with XLEN
When sew <= 32bits, not need to extend scalar reg.
When sew > 32bits, if xlen is less that sew, we should sign extend
the scalar register, except explicitly specified by the spec.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-21-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
LIU Zhiwei [Thu, 20 Jan 2022 12:20:46 +0000 (20:20 +0800)]
target/riscv: Adjust vector address with mask
The mask comes from the pointer masking extension, or the max value
corresponding to XLEN bits.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220120122050.41546-20-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
LIU Zhiwei [Thu, 20 Jan 2022 12:20:45 +0000 (20:20 +0800)]
target/riscv: Fix check range for first fault only
Only check the range that has passed the address translation.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-19-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
LIU Zhiwei [Thu, 20 Jan 2022 12:20:44 +0000 (20:20 +0800)]
target/riscv: Remove VILL field in VTYPE
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Acked-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-18-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
LIU Zhiwei [Thu, 20 Jan 2022 12:20:43 +0000 (20:20 +0800)]
target/riscv: Adjust vsetvl according to XLEN
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-17-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
LIU Zhiwei [Thu, 20 Jan 2022 12:20:42 +0000 (20:20 +0800)]
target/riscv: Split out the vill from vtype
We need not specially process vtype when XLEN changes.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-16-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
LIU Zhiwei [Thu, 20 Jan 2022 12:20:41 +0000 (20:20 +0800)]
target/riscv: Split pm_enabled into mask and base
Use cached cur_pmmask and cur_pmbase to infer the
current PM mode.
This may decrease the TCG IR by one when pm_enabled
is true and pm_base_enabled is false.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-15-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
LIU Zhiwei [Thu, 20 Jan 2022 12:20:40 +0000 (20:20 +0800)]
target/riscv: Calculate address according to XLEN
Define one common function to compute a canonical address from a register
plus offset. Merge gen_pm_adjust_address into this function.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-14-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
LIU Zhiwei [Thu, 20 Jan 2022 12:20:39 +0000 (20:20 +0800)]
target/riscv: Alloc tcg global for cur_pm[mask|base]
Replace the array of pm_mask/pm_base with scalar variables.
Remove the cached array value in DisasContext.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-13-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
LIU Zhiwei [Thu, 20 Jan 2022 12:20:38 +0000 (20:20 +0800)]
target/riscv: Create current pm fields in env
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220120122050.41546-12-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
LIU Zhiwei [Thu, 20 Jan 2022 12:20:37 +0000 (20:20 +0800)]
target/riscv: Adjust csr write mask with XLEN
Write mask is representing the bits we care about.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-11-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
LIU Zhiwei [Thu, 20 Jan 2022 12:20:36 +0000 (20:20 +0800)]
target/riscv: Relax debug check for pm write
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-10-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
LIU Zhiwei [Thu, 20 Jan 2022 12:20:35 +0000 (20:20 +0800)]
target/riscv: Use gdb xml according to max mxlen
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-9-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
LIU Zhiwei [Thu, 20 Jan 2022 12:20:34 +0000 (20:20 +0800)]
target/riscv: Extend pc for runtime pc write
In some cases, we must restore the guest PC to the address of the start of
the TB, such as when the instruction counter hits zero. So extend pc register
according to current xlen for these cases.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-8-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
LIU Zhiwei [Thu, 20 Jan 2022 12:20:33 +0000 (20:20 +0800)]
target/riscv: Ignore the pc bits above XLEN
The read from PC for translation is in cpu_get_tb_cpu_state, before translation.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-7-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
LIU Zhiwei [Thu, 20 Jan 2022 12:20:32 +0000 (20:20 +0800)]
target/riscv: Create xl field in env
Current xlen has been used in helper functions and many other places.
The computation of current xlen is not so trivial, so that we should
recompute it as little as possible.
Fortunately, xlen only changes in very seldom cases, such as exception,
misa write, mstatus write, cpu reset, migration load. So that we can only
recompute xlen in this places and cache it into CPURISCVState.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-6-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
LIU Zhiwei [Thu, 20 Jan 2022 12:20:31 +0000 (20:20 +0800)]
target/riscv: Sign extend pc for different XLEN
When pc is written, it is sign-extended to fill the widest supported XLEN.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-5-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
LIU Zhiwei [Thu, 20 Jan 2022 12:20:30 +0000 (20:20 +0800)]
target/riscv: Sign extend link reg for jal and jalr
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-4-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
LIU Zhiwei [Thu, 20 Jan 2022 12:20:29 +0000 (20:20 +0800)]
target/riscv: Don't save pc when exception return
As pc will be written by the xepc in exception return, just ignore
pc in translation.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-3-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
LIU Zhiwei [Thu, 20 Jan 2022 12:20:28 +0000 (20:20 +0800)]
target/riscv: Adjust pmpcfg access with mxl
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-2-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Anup Patel [Thu, 13 Jan 2022 14:50:39 +0000 (20:20 +0530)]
hw/riscv: spike: Allow using binary firmware as bios
Currently, we have to use OpenSBI firmware ELF as bios for the spike
machine because the HTIF console requires ELF for parsing "fromhost"
and "tohost" symbols.
The latest OpenSBI can now optionally pick-up HTIF register address
from HTIF DT node so using this feature spike machine can now use
OpenSBI firmware BIN as bios.
Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang [Tue, 18 Jan 2022 01:45:20 +0000 (09:45 +0800)]
target/riscv: rvv-1.0: Allow Zve32f extension to be turned on
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-18-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang [Tue, 18 Jan 2022 01:45:19 +0000 (09:45 +0800)]
target/riscv: rvv-1.0: Add Zve32f support for narrowing type-convert insns
Vector narrowing conversion instructions are provided to and from all
supported integer EEWs for Zve32f extension.
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-17-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang [Tue, 18 Jan 2022 01:45:18 +0000 (09:45 +0800)]
target/riscv: rvv-1.0: Add Zve32f support for widening type-convert insns
Vector widening conversion instructions are provided to and from all
supported integer EEWs for Zve32f extension.
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-16-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang [Tue, 18 Jan 2022 01:45:17 +0000 (09:45 +0800)]
target/riscv: rvv-1.0: Add Zve32f support for single-width fp reduction insns
Vector single-width floating-point reduction operations for EEW=32 are
supported for Zve32f extension.
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-15-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang [Tue, 18 Jan 2022 01:45:16 +0000 (09:45 +0800)]
target/riscv: rvv-1.0: Add Zve32f support for scalar fp insns
Zve32f extension requires the scalar processor to implement the F
extension and implement all vector floating-point instructions for
floating-point operands with EEW=32 (i.e., no widening floating-point
operations).
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-14-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang [Tue, 18 Jan 2022 01:45:15 +0000 (09:45 +0800)]
target/riscv: rvv-1.0: Add Zve32f support for configuration insns
All Zve* extensions support the vector configuration instructions.
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-13-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang [Tue, 18 Jan 2022 01:45:14 +0000 (09:45 +0800)]
target/riscv: rvv-1.0: Add Zve32f extension into RISC-V
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-12-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang [Tue, 18 Jan 2022 01:45:13 +0000 (09:45 +0800)]
target/riscv: rvv-1.0: Allow Zve64f extension to be turned on
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-11-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang [Tue, 18 Jan 2022 01:45:12 +0000 (09:45 +0800)]
target/riscv: rvv-1.0: Add Zve64f support for narrowing type-convert insns
Vector narrowing conversion instructions are provided to and from all
supported integer EEWs for Zve64f extension.
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-10-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang [Tue, 18 Jan 2022 01:45:11 +0000 (09:45 +0800)]
target/riscv: rvv-1.0: Add Zve64f support for widening type-convert insns
Vector widening conversion instructions are provided to and from all
supported integer EEWs for Zve64f extension.
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-9-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang [Tue, 18 Jan 2022 01:45:10 +0000 (09:45 +0800)]
target/riscv: rvv-1.0: Add Zve64f support for single-width fp reduction insns
Vector single-width floating-point reduction operations for EEW=32 are
supported for Zve64f extension.
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-8-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang [Tue, 18 Jan 2022 01:45:09 +0000 (09:45 +0800)]
target/riscv: rvv-1.0: Add Zve64f support for scalar fp insns
Zve64f extension requires the scalar processor to implement the F
extension and implement all vector floating-point instructions for
floating-point operands with EEW=32 (i.e., no widening floating-point
operations).
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-7-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang [Tue, 18 Jan 2022 01:45:08 +0000 (09:45 +0800)]
target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and vsmul.vx insns
All Zve* extensions support all vector fixed-point arithmetic
instructions, except that vsmul.vv and vsmul.vx are not supported
for EEW=64 in Zve64*.
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-6-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang [Tue, 18 Jan 2022 01:45:07 +0000 (09:45 +0800)]
target/riscv: rvv-1.0: Add Zve64f support for vmulh variant insns
All Zve* extensions support all vector integer instructions,
except that the vmulh integer multiply variants that return the
high word of the product (vmulh.vv, vmulh.vx, vmulhu.vv, vmulhu.vx,
vmulhsu.vv, vmulhsu.vx) are not included for EEW=64 in Zve64*.
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-5-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang [Tue, 18 Jan 2022 01:45:06 +0000 (09:45 +0800)]
target/riscv: rvv-1.0: Add Zve64f support for load and store insns
All Zve* extensions support all vector load and store instructions,
except Zve64* extensions do not support EEW=64 for index values when
XLEN=32.
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-4-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang [Tue, 18 Jan 2022 01:45:05 +0000 (09:45 +0800)]
target/riscv: rvv-1.0: Add Zve64f support for configuration insns
All Zve* extensions support the vector configuration instructions.
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-3-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang [Tue, 18 Jan 2022 01:45:04 +0000 (09:45 +0800)]
target/riscv: rvv-1.0: Add Zve64f extension into RISC-V
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-2-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
The pointer assignment "const char *p = path;" in function
qemu_fdt_add_path is unnecessary. Let's remove it and just
use the "path" passed in. No functional change.
Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Yanan Wang <wangyanan55@huawei.com> Reviewed-by: Andrew Jones <drjones@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-id: 20220111032758.27804-1-wangyanan55@huawei.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Thomas Huth [Fri, 7 Jan 2022 13:38:44 +0000 (14:38 +0100)]
softmmu/device_tree: Silence compiler warning with --enable-sanitizers
If I configure my build with --enable-sanitizers, my GCC (v8.5.0)
complains:
.../softmmu/device_tree.c: In function ‘qemu_fdt_add_path’:
.../softmmu/device_tree.c:560:18: error: ‘retval’ may be used uninitialized
in this function [-Werror=maybe-uninitialized]
int namelen, retval;
^~~~~~
It's a false warning since the while loop is always executed at least
once (p has to be non-NULL, otherwise the derefence in the if-statement
earlier will crash). Thus let's switch to a do-while loop here instead
to make the compiler happy in all cases.
Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Andrew Jones <drjones@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
Message-id: 20220107133844.145039-1-thuth@redhat.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Yifei Jiang [Wed, 12 Jan 2022 08:13:27 +0000 (16:13 +0800)]
target/riscv: Implement virtual time adjusting with vm state changing
We hope that virtual time adjusts with vm state changing. When a vm
is stopped, guest virtual time should stop counting and kvm_timer
should be stopped. When the vm is resumed, guest virtual time should
continue to count and kvm_timer should be restored.
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com> Signed-off-by: Mingwang Li <limingwang@huawei.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220112081329.1835-12-jiangyifei@huawei.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Yifei Jiang [Wed, 12 Jan 2022 08:13:26 +0000 (16:13 +0800)]
target/riscv: Add kvm_riscv_get/put_regs_timer
Add kvm_riscv_get/put_regs_timer to synchronize virtual time context
from KVM.
To set register of RISCV_TIMER_REG(state) will occur a error from KVM
on kvm_timer_state == 0. It's better to adapt in KVM, but it doesn't matter
that adaping in QEMU.
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com> Signed-off-by: Mingwang Li <limingwang@huawei.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220112081329.1835-11-jiangyifei@huawei.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
projects / mirror_qemu.git / log