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4 years agodrm/amdgpu: pull ras controller int status only when ras enabled
Hawking Zhang [Mon, 18 Nov 2019 10:17:12 +0000 (18:17 +0800)]
drm/amdgpu: pull ras controller int status only when ras enabled

ras_controller_irq and athub_err_event_irq are only registered
when PCIE_BIF ras is marked as supported. as the result, the driver
also just need pull the int status in such case.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: John Clements <john.clements@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amdgpu: switch to common helper func for psp cmd submission
Hawking Zhang [Mon, 18 Nov 2019 09:39:55 +0000 (17:39 +0800)]
drm/amdgpu: switch to common helper func for psp cmd submission

Drop all the IP specific cmd_submit callback function
and use the common helper instead

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: John Clements <john.clements@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amdgpu: add helper func for psp ring cmd submission
Hawking Zhang [Mon, 18 Nov 2019 09:03:12 +0000 (17:03 +0800)]
drm/amdgpu: add helper func for psp ring cmd submission

Except for ring wptr update, the psp ring cmd submission
function shouldn't be IP specific one. Create a common
helper function to be shared for all the ASICs.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: John Clements <john.clements@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amdgpu: add psp funcs for ring write pointer read/write
Hawking Zhang [Mon, 18 Nov 2019 09:13:56 +0000 (17:13 +0800)]
drm/amdgpu: add psp funcs for ring write pointer read/write

The ring write pointer regsiter update is the only part that
is IP specific ones in psp_cmd_submit function.

Add two callbacks for wptr read/write so that we unify the
psp_cmd_submit function for all the ASICs.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: John Clements <john.clements@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/powerplay: add missing header file declaration
Evan Quan [Tue, 19 Nov 2019 03:43:45 +0000 (11:43 +0800)]
drm/amd/powerplay: add missing header file declaration

This can fix the compile errors below:
drivers/gpu/drm/amd/amdgpu/../powerplay/smu_v11_0.c: In function ‘smu_v11_0_baco_set_state’:
drivers/gpu/drm/amd/amdgpu/../powerplay/smu_v11_0.c:1674:27: error: implicit declaration of function ‘amdgpu_ras_get_context’ [-Werror=implicit-function-declaration]
  struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
                           ^
drivers/gpu/drm/amd/amdgpu/../powerplay/smu_v11_0.c:1674:27: warning: initialization makes pointer from integer without a cast [-Wint-conversion]
drivers/gpu/drm/amd/amdgpu/../powerplay/smu_v11_0.c:1692:19: error: dereferencing pointer to incomplete type ‘struct amdgpu_ras’
   if (!ras || !ras->supported) {

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/powerplay: add Arcturus baco reset support
Evan Quan [Mon, 4 Nov 2019 09:31:29 +0000 (17:31 +0800)]
drm/amd/powerplay: add Arcturus baco reset support

Enable baco reset support on Arcturus.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/powerplay: correct swSMU baco reset related settings
Evan Quan [Mon, 18 Nov 2019 09:04:24 +0000 (17:04 +0800)]
drm/amd/powerplay: correct swSMU baco reset related settings

Added bif doorbell interrupt setting and applied different
settings for BACO reset for RAS recovery.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agoRevert "drm/amd/display: enable S/G for RAVEN chip"
Alex Deucher [Fri, 15 Nov 2019 15:26:52 +0000 (10:26 -0500)]
Revert "drm/amd/display: enable S/G for RAVEN chip"

This reverts commit 1c4259159132ae4ceaf7c6db37a6cf76417f73d9.

S/G display is not stable with the IOMMU enabled on some
platforms.

Bug: https://bugzilla.kernel.org/show_bug.cgi?id=205523
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amdgpu: disable gfxoff on original raven
Alex Deucher [Fri, 15 Nov 2019 15:21:23 +0000 (10:21 -0500)]
drm/amdgpu: disable gfxoff on original raven

There are still combinations of sbios and firmware that
are not stable.

Bug: https://bugzilla.kernel.org/show_bug.cgi?id=204689
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amdgpu: remove experimental flag for Navi14
Alex Deucher [Fri, 15 Nov 2019 14:38:28 +0000 (09:38 -0500)]
drm/amdgpu: remove experimental flag for Navi14

5.4 and newer works fine with navi14.

Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amdgpu: disable gfxoff when using register read interface
Alex Deucher [Thu, 14 Nov 2019 16:39:05 +0000 (11:39 -0500)]
drm/amdgpu: disable gfxoff when using register read interface

When gfxoff is enabled, accessing gfx registers via MMIO
can lead to a hang.

Bug: https://bugzilla.kernel.org/show_bug.cgi?id=205497
Acked-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amdgpu/powerplay: properly set PP_GFXOFF_MASK (v2)
Alex Deucher [Wed, 13 Nov 2019 16:08:35 +0000 (11:08 -0500)]
drm/amdgpu/powerplay: properly set PP_GFXOFF_MASK (v2)

So that the setting reflects what the hw supports. This will
be used in a subsequent patch so needs to be correct.

v2: squash in fix from Colin Ian King

Bug: https://bugzilla.kernel.org/show_bug.cgi?id=205497
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/powerplay: return errno code to caller when error occur
Chen Wandun [Mon, 18 Nov 2019 08:03:34 +0000 (16:03 +0800)]
drm/amd/powerplay: return errno code to caller when error occur

return errno code to caller when error occur, and meanwhile
remove gcc '-Wunused-but-set-variable' warning.

drivers/gpu/drm/amd/amdgpu/../powerplay/smumgr/vegam_smumgr.c: In function vegam_populate_smc_boot_level:
drivers/gpu/drm/amd/amdgpu/../powerplay/smumgr/vegam_smumgr.c:1364:6: warning: variable result set but not used [-Wunused-but-set-variable]

Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Chen Wandun <chenwandun@huawei.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amdgpu: remove not needed memset
zhengbin [Mon, 18 Nov 2019 09:00:31 +0000 (17:00 +0800)]
drm/amdgpu: remove not needed memset

Fixes coccicheck warning:

drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c:64:13-31: WARNING: dma_alloc_coherent use in ih -> ring already zeroes out memory,  so memset is not needed

Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: zhengbin <zhengbin13@huawei.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amdgpu: fix bad DMA from INTERRUPT_CNTL2
Sam Bobroff [Sun, 17 Nov 2019 23:53:54 +0000 (10:53 +1100)]
drm/amdgpu: fix bad DMA from INTERRUPT_CNTL2

The INTERRUPT_CNTL2 register expects a valid DMA address, but is
currently set with a GPU MC address.  This can cause problems on
systems that detect the resulting DMA read from an invalid address
(found on a Power8 guest).

Instead, use the DMA address of the dummy page because it will always
be safe.

Fixes: 27ae10641e9c ("drm/amdgpu: add interupt handler implementation for si v3")
Signed-off-by: Sam Bobroff <sbobroff@linux.ibm.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/radeon: fix bad DMA from INTERRUPT_CNTL2
Sam Bobroff [Sun, 17 Nov 2019 23:53:53 +0000 (10:53 +1100)]
drm/radeon: fix bad DMA from INTERRUPT_CNTL2

The INTERRUPT_CNTL2 register expects a valid DMA address, but is
currently set with a GPU MC address.  This can cause problems on
systems that detect the resulting DMA read from an invalid address
(found on a Power8 guest).

Instead, use the DMA address of the dummy page because it will always
be safe.

Fixes: d8f60cfc9345 ("drm/radeon/kms: Add support for interrupts on r6xx/r7xx chips (v3)")
Fixes: 25a857fbe973 ("drm/radeon/kms: add support for interrupts on SI")
Fixes: a59781bbe528 ("drm/radeon: add support for interrupts on CIK (v5)")
Signed-off-by: Sam Bobroff <sbobroff@linux.ibm.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/radeon: remove set but not used variable 'tv_pll_cntl1'
zhengbin [Fri, 15 Nov 2019 12:13:00 +0000 (20:13 +0800)]
drm/radeon: remove set but not used variable 'tv_pll_cntl1'

Fixes gcc '-Wunused-but-set-variable' warning:

drivers/gpu/drm/radeon/radeon_legacy_tv.c: In function radeon_legacy_tv_mode_set:
drivers/gpu/drm/radeon/radeon_legacy_tv.c:538:24: warning: variable tv_pll_cntl1 set but not used [-Wunused-but-set-variable]

It is introduced by commit 4ce001abafaf ("drm/radeon/kms:
add initial radeon tv-out support."), but never used,
so remove it.

Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: zhengbin <zhengbin13@huawei.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/radeon: remove set but not used variable 'blocks'
zhengbin [Fri, 15 Nov 2019 12:12:59 +0000 (20:12 +0800)]
drm/radeon: remove set but not used variable 'blocks'

Fixes gcc '-Wunused-but-set-variable' warning:

drivers/gpu/drm/radeon/radeon_combios.c: In function radeon_combios_get_power_modes:
drivers/gpu/drm/radeon/radeon_combios.c:2638:10: warning: variable blocks set but not used [-Wunused-but-set-variable]

It is introduced by commit 56278a8edace ("drm/radeon/kms:
pull power mode info from bios tables (v3)"), but never used,
so remove it.

Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: zhengbin <zhengbin13@huawei.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/radeon: remove set but not used variable 'radeon_connector'
zhengbin [Fri, 15 Nov 2019 12:12:58 +0000 (20:12 +0800)]
drm/radeon: remove set but not used variable 'radeon_connector'

Fixes gcc '-Wunused-but-set-variable' warning:

drivers/gpu/drm/radeon/radeon_display.c: In function radeon_crtc_scaling_mode_fixup:
drivers/gpu/drm/radeon/radeon_display.c:1685:27: warning: variable radeon_connector set but not used [-Wunused-but-set-variable]

It is not used since commit 377bd8a98d7d ("drm/radeon:
use a fetch function to get the edid")

Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: zhengbin <zhengbin13@huawei.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/radeon: remove set but not used variable 'dig_connector'
zhengbin [Fri, 15 Nov 2019 12:12:57 +0000 (20:12 +0800)]
drm/radeon: remove set but not used variable 'dig_connector'

Fixes gcc '-Wunused-but-set-variable' warning:

drivers/gpu/drm/radeon/atombios_dp.c: In function radeon_dp_get_panel_mode:
drivers/gpu/drm/radeon/atombios_dp.c:415:36: warning: variable dig_connector set but not used [-Wunused-but-set-variable]

It is not used since commit 379dfc25e257 ("drm/radeon/dp:
switch to the common i2c over aux code")

Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: zhengbin <zhengbin13@huawei.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/radeon: remove set but not used variable 'backbias_response_time'
zhengbin [Fri, 15 Nov 2019 12:12:56 +0000 (20:12 +0800)]
drm/radeon: remove set but not used variable 'backbias_response_time'

Fixes gcc '-Wunused-but-set-variable' warning:

drivers/gpu/drm/radeon/si_dpm.c: In function si_program_response_times:
drivers/gpu/drm/radeon/si_dpm.c:3640:29: warning: variable backbias_response_time set but not used [-Wunused-but-set-variable]

It is introduced by commit a9e61410921b ("drm/radeon/kms:
add dpm support for SI (v7)"), but never used, so remove it.

Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: zhengbin <zhengbin13@huawei.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/radeon: remove set but not used variable 'size', 'relocs_chunk'
zhengbin [Fri, 15 Nov 2019 12:12:55 +0000 (20:12 +0800)]
drm/radeon: remove set but not used variable 'size', 'relocs_chunk'

Fixes gcc '-Wunused-but-set-variable' warning:

drivers/gpu/drm/radeon/r600_cs.c: In function r600_cs_track_validate_cb:
drivers/gpu/drm/radeon/r600_cs.c:353:22: warning: variable size set but not used [-Wunused-but-set-variable]
drivers/gpu/drm/radeon/r600_cs.c: In function r600_cs_track_validate_db:
drivers/gpu/drm/radeon/r600_cs.c:520:27: warning: variable size set but not used [-Wunused-but-set-variable]
drivers/gpu/drm/radeon/r600_cs.c: In function r600_dma_cs_next_reloc:
drivers/gpu/drm/radeon/r600_cs.c:2345:26: warning: variable relocs_chunk set but not used [-Wunused-but-set-variable]

The first 'size' is not used since commit f30df2fad0c9 ("drm/radeon/r600:
fix tiling issues in CS checker.")

The second 'size' is introduced by commit 88f50c80748b ("drm/radeon/kms:
add htile support to the cs checker v3"), but never used, so remove it.

'relocs_chunk' is not used since commit 9305ede6afe2 ("radeon/kms:
fix dma relocation checking")

Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: zhengbin <zhengbin13@huawei.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/display: Fix coding error in connector atomic check
Mikita Lipski [Tue, 12 Nov 2019 14:13:20 +0000 (09:13 -0500)]
drm/amd/display: Fix coding error in connector atomic check

[why]
For MST connector atomic check we have to check a new CRTC state
instead of an old one, when checking if CRTC is disabled to
release VCPI slots allocated.

Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/display: Fix static analysis bug in validate_bksv
Bhawanpreet Lakha [Wed, 6 Nov 2019 19:58:45 +0000 (14:58 -0500)]
drm/amd/display: Fix static analysis bug in validate_bksv

[Why]
static analysis throws the error below

Out-of-bounds read (OVERRUN)
Overrunning array of 5 bytes at byte offset 7 by dereferencing pointer
(uint64_t *)hdcp->auth.msg.hdcp1.bksv.

var n is going to contain  r0p and bcaps. if they are non-zero the count
will be wrong

How]
Use memcpy instead to avoid this.

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/display: split rxstatus for hdmi and dp
Bhawanpreet Lakha [Thu, 24 Oct 2019 20:07:58 +0000 (16:07 -0400)]
drm/amd/display: split rxstatus for hdmi and dp

[Why]
Currently we share rxstatus between HDMI and DP, so we use 16bits
The drm defines work with 1bytes at a time. So we need to
split the HDMI rxstatus into 2bytes before we can use drm defines

[How]
-create rxstatus for dp and hdmi. rxstatus for hdmi is split into bytes
using arrays.
-use drm_hdcp defines for the remaining structs

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/display: use drm defines for MAX CASCADE MASK
Bhawanpreet Lakha [Thu, 24 Oct 2019 20:07:43 +0000 (16:07 -0400)]
drm/amd/display: use drm defines for MAX CASCADE MASK

[Why]
drm already has this define

[How]
drm Mask is 0x08 vs 0x0800. The reason is because drm mask
works on a byte.        ^^
                 =======||
                 ||
Since the first byte is always zero we can ignore it and only check the
second byte.

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/display: add and use defines from drm_hdcp.h
Bhawanpreet Lakha [Mon, 21 Oct 2019 18:40:55 +0000 (14:40 -0400)]
drm/amd/display: add and use defines from drm_hdcp.h

[Why]
These defines/macros exist already no need to redefine them

[How]
Use the defines/macros from drm_hdcp.h

-we share the rxstatus between HDMI and DP (2 bytes), But upstream
defines/macros for HDMI are for 1 byte. So we need to create a separate
rxstatus for HDMI

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/display: Refactor HDCP encryption status update
Bhawanpreet Lakha [Wed, 4 Sep 2019 20:52:20 +0000 (16:52 -0400)]
drm/amd/display: Refactor HDCP encryption status update

[Why]
The old way was to poll PSP and update the properties. But due to a
limitation in the PSP interface this doesn't work for MST.

[How]
According to PSP if set_encryption return success, the link is encrypted
and the only way it will not be is if we get a link loss(which we handle
already).

So this method should be good enough to report HDCP status.

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/display: add force Type0/1 flag
Bhawanpreet Lakha [Thu, 29 Aug 2019 19:26:54 +0000 (15:26 -0400)]
drm/amd/display: add force Type0/1 flag

[Why]
Before we had a disable_type1 flag, this forced HDCP 2.2 to type0
There was no way to force type1.

[How]
Remove disable_type1 flag and instead add a flag to force type0/1.

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/display: Refactor HDCP to handle multiple displays per link
Bhawanpreet Lakha [Wed, 28 Aug 2019 19:10:03 +0000 (15:10 -0400)]
drm/amd/display: Refactor HDCP to handle multiple displays per link

[Why]
We need to do this to support HDCP over MST

Currently we save a display per link, in a MST case we need to save
multiple displays per link.

[How]
We can create an array per link to cache the displays, but it
complicates the design. Instead we can use the module to cache the
displays.

Now we will always add all the displays to the module, but we use the
adjustment flag to disable hdcp on all of them before they are added.

When we want to enable hdcp we just query the display(cache), remove
it then add it back with different adjustments. Its the similar for
disable.

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/display: Handle hdcp2.2 type0/1 in dm
Bhawanpreet Lakha [Fri, 16 Aug 2019 18:49:05 +0000 (14:49 -0400)]
drm/amd/display: Handle hdcp2.2 type0/1 in dm

[Why]
HDCP 2.2 uses type0 and type1 content type. This is passed to the receiver
to stream the proper content.

For example, in a MST case if the main
device is HDCP2.2 capable but the secondary device is only 1.4 capabale
we can use Type0

Type0 content: use HDCP 1.4 or HDCP2.2 type0
Type1 content: Only use HDCP 2.2 type1

[How]
We use the "hdcp content type" property in drm. We use the
disable_type1 flag in hdcp module to select the type based on the
properties.

For updating the property we use the same logic as 1.4, but now we
consider content_type as well and update the property if the
requirements are met

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/display: Enable HDCP 2.2
Bhawanpreet Lakha [Tue, 23 Jul 2019 15:25:10 +0000 (11:25 -0400)]
drm/amd/display: Enable HDCP 2.2

[Why]
HDCP 2.2 was disabled, we need to enable it

[How]
-Update display topology to support 2.2
-Unset hdcp2.disable in update_config
-Change logic of event_update_property, now we set the property to be
ENABLED for any level of encryption (2.2 or 1.4).

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/display: Change ERROR to WARN for HDCP module
Bhawanpreet Lakha [Wed, 18 Sep 2019 15:24:39 +0000 (11:24 -0400)]
drm/amd/display: Change ERROR to WARN for HDCP module

[Why]
HDCP is a bit finicky so we try it 3 times, this leads to a case where
if we fail the first time and pass the second time the error is still
shown in dmesg for the first failed attempt.

This leads to false positive errors.

[How]
Change the logging from ERROR to WARNING. Warnings are still shown in dmesg
to know what went wrong.

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/display: Add logging for HDCP2.2
Bhawanpreet Lakha [Wed, 18 Sep 2019 15:24:09 +0000 (11:24 -0400)]
drm/amd/display: Add logging for HDCP2.2

[Why]
We need to log the state changes for 2.2
This patch extends the existing logging functions to handle
HDCP2.2.

[How]
We do this by adding if/else in the defines, and output the log
 based on the hdcp version

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/display: Add execution and transition states for HDCP2.2
Bhawanpreet Lakha [Wed, 18 Sep 2019 15:18:15 +0000 (11:18 -0400)]
drm/amd/display: Add execution and transition states for HDCP2.2

The module works like a state machine

                                    +-------------+
                            ------> | Execution.c | ------
                            |       +-------------+       |
                            |                             V
    +----+              +--------+                 +--------------+
    | DM |    ----->    | Hdcp.c |  <------------  | Transition.c |
    +----+    <-----    +--------+                 +--------------+

This patch adds the execution and transition files for 2.2

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/display: Add DDC handles for HDCP2.2
Bhawanpreet Lakha [Wed, 18 Sep 2019 15:23:07 +0000 (11:23 -0400)]
drm/amd/display: Add DDC handles for HDCP2.2

[Why]
We need these to read and write to aux/i2c, during
authentication

[How]
Create read/write functions for all the steps
(Eg, h_prime, paring_info etc)

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/display: Add PSP block to verify HDCP2.2 steps
Bhawanpreet Lakha [Wed, 18 Sep 2019 15:19:51 +0000 (11:19 -0400)]
drm/amd/display: Add PSP block to verify HDCP2.2 steps

[Why]
All the HDCP transactions should be verified using PSP

[How]
This patch adds the psp calls we need to verify the steps

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/display: Add Navi10 DMUB VBIOS code
Nicholas Kazlauskas [Mon, 4 Nov 2019 20:36:16 +0000 (15:36 -0500)]
drm/amd/display: Add Navi10 DMUB VBIOS code

[Why]
We need some extra dmub_cmd_type for NV10

[How]
Add command table functions in DMUB firmware.

Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Xiong Yan <Xiong.Yan@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/display: Add DSC 422Native debug option
Ilya Bakoulin [Thu, 3 Oct 2019 21:35:32 +0000 (17:35 -0400)]
drm/amd/display: Add DSC 422Native debug option

[Why]
Need to be able to enable native 422 for debugging purposes.

[How]
Add new dc_debug_options bool and check it in the get_dsc_enc_caps
function.

Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/display: Use a temporary copy of the current state when updating DSC config
Nikola Cornij [Mon, 4 Nov 2019 22:44:23 +0000 (17:44 -0500)]
drm/amd/display: Use a temporary copy of the current state when updating DSC config

[why]
When updating DSC config, a new config has to be validated before proceeding
with applying the update. Validation, however, modifies the current state.
This means DSC config validation would affect pipe re-assignment, causing
intermittent screen corruption issues when ODM is required for DSC.

[how]
- Use a copy of the current state for modified DSC config validation
- Set the update type to FULL_UPDATE to correctly validate and set the
  actual state used for committing the streams

Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/display: Spin for DMCUB PHY init in DC
Nicholas Kazlauskas [Tue, 5 Nov 2019 17:51:51 +0000 (12:51 -0500)]
drm/amd/display: Spin for DMCUB PHY init in DC

[Why]
DCN will hang if we access registers before PHY init is done.

So we need to spin or abort.

[How]
On hardware with DMCUB running and working we shouldn't time out
waiting for this to finish and we shouldn't hit the spin cycle.

If there's no hardware support then we should exit out of the function
early assuming that PHY init was already done elsewhere.

If we hit the timeout then there's likely a bug in firmware or software
and we need to debug - add errors and asserts as appropriate.

Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/display: DML Validation Dump/Check with Logging
Jaehyun Chung [Thu, 31 Oct 2019 19:53:24 +0000 (15:53 -0400)]
drm/amd/display: DML Validation Dump/Check with Logging

[Why]
Need validation that we are programming the expected values (rq, ttu, dlg)
from DML. This debug feature will output logs if we are programming
incorrect values and may help differentiate DAL issues from HW issues.

[How]
Dump relevant registers for each pipe with active stream. Compare current
reg values with the converted DML output. Log mismatches when found.

Signed-off-by: Jaehyun Chung <jaehyun.chung@amd.com>
Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/display: cleanup of function pointer tables
Anthony Koo [Tue, 29 Oct 2019 19:05:56 +0000 (15:05 -0400)]
drm/amd/display: cleanup of function pointer tables

[Why]
It is becoming increasingly hard to figure out which
function is called on the different DCN versions

[How]
1. Make function pointer table init in its own init.c file
2. Remove other scenarios in hwseq.c file that need to
include headers of other DCN versions. (If needed,
it should have been done via the function pointers)

Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/display: Don't spin forever waiting for DMCUB phy/auto init
Nicholas Kazlauskas [Mon, 4 Nov 2019 18:32:46 +0000 (13:32 -0500)]
drm/amd/display: Don't spin forever waiting for DMCUB phy/auto init

[Why]
It's an interface violation to use infinite loops within DMUB
service functions and we'll lock up the kernel by doing so.

[How]
Revert the function back to its intended functionality.
Move the infinite loops into DC/DM as necessary.

Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Sun peng Li <Sunpeng.Li@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/display: Avoid conflict between HDR multiplier and 3dlut
Michael Strauss [Sun, 3 Nov 2019 14:35:03 +0000 (09:35 -0500)]
drm/amd/display: Avoid conflict between HDR multiplier and 3dlut

[WHY]
There can be a conflict between OS HDR multiplier and 3dlut HDR
multiplier, which are both sent to DC.

[HOW]
Instead of having dc determine which HDR multiplier to use, make the
decision in dm and send only the intended value in a surface update.
Store the current OS HDR multiplier and determine whether to use it or
the 3dlut's multiplier before sending the surface update to dc. Send
multiplier to dc in fixed31_32 format, dc then converts it to hw format.

Signed-off-by: Michael Strauss <michael.strauss@amd.com>
Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/display: add debugfs sdp hook up function for Navi
David (Dingchen) Zhang [Thu, 31 Oct 2019 18:36:51 +0000 (14:36 -0400)]
drm/amd/display: add debugfs sdp hook up function for Navi

[why]
need to send immediate SDP message via debugfs on Navi board.

[how]
hook up the DCN1x encoder function of sending immediate sdp
message to DCN2.

Signed-off-by: David (Dingchen) Zhang <dingchen.zhang@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/display: 3.2.60
Aric Cyr [Mon, 4 Nov 2019 13:31:14 +0000 (08:31 -0500)]
drm/amd/display: 3.2.60

Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/display: Add debug trace for dmcub FW autoload.
Yongqiang Sun [Sat, 26 Oct 2019 14:19:40 +0000 (10:19 -0400)]
drm/amd/display: Add debug trace for dmcub FW autoload.

[Why & How]
1. Add trace code enum for easy debugging.
2. Add trace during uC boot up, including loading phy FW
   and dmcu FW.
3. Change cache memory type back to write back,
   since write through has issue when resume from S0i3 100% hang after
   3.2ms.
4. Change CW3 base address to hard code value to avoid memory overlap
   with cw1.
5. Change polling phy init done to infinite loop to avoid dcn hang when
   dmcub uC stalled.
6. Add dmcub FW dis-assembly file to repositatory for debug purpose.

Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/display: Adjust DML workaround threshold
Joshua Aberback [Fri, 1 Nov 2019 21:29:20 +0000 (17:29 -0400)]
drm/amd/display: Adjust DML workaround threshold

[Why]
There is a case where the margin is between 50 and 60, but applying the
workaround causes a hang. By increasing the threshold, we are blocking more
cases from switching p-state during active, but those cases will fall back
to switching during blank, which is fine.

[How]
 - increase required margin from 50 to 60

Signed-off-by: Joshua Aberback <joshua.aberback@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/display: add color space option when sending link test pattern
Wenjing Liu [Tue, 15 Oct 2019 19:12:57 +0000 (15:12 -0400)]
drm/amd/display: add color space option when sending link test pattern

[why]
In the TEST_MSIC dpcd register field definition, the test equipment
has the option to choose between YCbCr601 or YCbCr709.
We will apply corresponding YCbCr coefficient based on this test
request.

[how]
Add a new input parameter in dc_link_dp_set_test_pattern to allow the
selection between different color space.

Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com>
Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/display: cleanup of construct and destruct funcs
Anthony Koo [Fri, 1 Nov 2019 01:39:39 +0000 (21:39 -0400)]
drm/amd/display: cleanup of construct and destruct funcs

[Why]
Too many construct functions which makes searching
difficult, especially on some debuggers.

[How]
Append all construct and destruct functions with dcn
number and object type to make each construct function
name unique

Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/display: Fix debugfs on MST connectors
Mikita Lipski [Thu, 31 Oct 2019 20:09:01 +0000 (16:09 -0400)]
drm/amd/display: Fix debugfs on MST connectors

[why]
Previous patch allowed to initialize debugfs entries on both MST
and SST connectors, but MST connectors get registered much later
which exposed an issue of debugfs entries being initialized in the
same folder.

[how]
Return SST debugfs entries' initialization back to where it was.
For MST connectors we should initialize debugfs entries in connector
register function after the connector is registered.

Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/display: revert change causing DTN hang for RV
Samson Tam [Thu, 31 Oct 2019 19:27:28 +0000 (15:27 -0400)]
drm/amd/display: revert change causing DTN hang for RV

[Why]
Hanging on RV for DTN driver verifier

[How]
Roll back change and investigate further

Signed-off-by: Samson Tam <Samson.Tam@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/display: Clean up some code with unused registers
Anthony Koo [Mon, 28 Oct 2019 15:45:14 +0000 (11:45 -0400)]
drm/amd/display: Clean up some code with unused registers

[Why]
Unused register in the code

[How]
Remove unused register

Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/display: Connect DIG FE to its BE before link training starts
Nikola Cornij [Tue, 29 Oct 2019 19:49:28 +0000 (15:49 -0400)]
drm/amd/display: Connect DIG FE to its BE before link training starts

[why]
In SST mode no idle pattern will be generated after link training if
DIG FE is not connected to DIG BE.

Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/display: Add debugfs initalization on mst connectors
Mikita Lipski [Tue, 29 Oct 2019 15:43:05 +0000 (11:43 -0400)]
drm/amd/display: Add debugfs initalization on mst connectors

[why]
We were missing debugfs files on MST connectors as the files
weren't initialized.

[how]
Move connector debugfs initialization into connoctor's
init helper function so it will be called by both SST and MST
connectors. Also move connector registration so it will be
registered before we create the entries.

Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/display: Add DMUB param to load inst const from driver
Nicholas Kazlauskas [Wed, 30 Oct 2019 13:02:39 +0000 (09:02 -0400)]
drm/amd/display: Add DMUB param to load inst const from driver

[Why]
By default we shouldn't be trying to write secure registers during
DMUB hardware init.

[How]
Add a parameter to control whether we put the DMCUB into secure reset
and attempt to load CW0/CW1.

Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/display: Add DMUB service function check if hw initialized
Nicholas Kazlauskas [Tue, 29 Oct 2019 18:23:55 +0000 (14:23 -0400)]
drm/amd/display: Add DMUB service function check if hw initialized

[Why]
We want to avoid reprogramming the cache window when possible.

We don't need to worry about it for S3 but we *do* need to worry about
it for S4 resume.

DM can check whether hardware should be reinitialized or store software
state when going to S4 to know whether we need to reprogram hardware.

[How]
Add helpers to the DMUB service to check hardware initialization state.

DM will hook it up later.

Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/display: Changes in dc to allow full update in some cases
Alvin Lee [Thu, 24 Oct 2019 19:45:44 +0000 (15:45 -0400)]
drm/amd/display: Changes in dc to allow full update in some cases

Changes in dc to allow for different cases where full update is
required.

Signed-off-by: Alvin Lee <alvin.lee2@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/display: Fix stereo with DCC enabled
Samson Tam [Thu, 24 Oct 2019 01:36:29 +0000 (21:36 -0400)]
drm/amd/display: Fix stereo with DCC enabled

[Why]
When sending DCC with Stereo, DCC gets enabled but the meta addresses
are 0. This happens momentarily before the meta addresses are populated
with a valid address.

[How]
Add call validate_dcc_with_meta_address() in
copy_surface_update_to_plane() to check for surface address and DCC
change.
When DCC has changed, check if DCC enable is true but meta address is 0.
If so, we turn DCC enable to false. When surface address has changed, we
check if DCC enable is false but meta address is not 0. If so, we turn
DCC enable back to true.  This will restore DCC enable to the proper
setting once the meta address is valid.

Signed-off-by: Samson Tam <Samson.Tam@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/display: 3.2.59
Aric Cyr [Mon, 28 Oct 2019 12:50:33 +0000 (08:50 -0400)]
drm/amd/display: 3.2.59

Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/display: Fix incorrect deep color setting in YCBCR420 modes
Stylon Wang [Fri, 20 Sep 2019 07:40:55 +0000 (15:40 +0800)]
drm/amd/display: Fix incorrect deep color setting in YCBCR420 modes

[Why]
HDMI 2.0 HF-VSDB in EDID defines supported color depths in YCBCR420 modes.
But we did not honor these bit masks when choosing pixel encoding.
HDMI 2.0 compliance tests with deep color and YCBCR420 failed as a result.

[How]
Cap color depth based on y420_dc_modes from EDID.

Signed-off-by: Stylon Wang <stylon.wang@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/display: Update background color in bottommost mpcc
Hugo Hu [Fri, 25 Oct 2019 07:33:15 +0000 (15:33 +0800)]
drm/amd/display: Update background color in bottommost mpcc

[Why]
Background color only takes effect in bottommost mpcc.

[How]
Update background color in bottommost mpcc.

Signed-off-by: Hugo Hu <hugo.hu@amd.com>
Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/display: Add hubp clock status in DTN log for Navi
Leo (Hanghong) Ma [Fri, 25 Oct 2019 13:40:13 +0000 (09:40 -0400)]
drm/amd/display: Add hubp clock status in DTN log for Navi

[Why]
For debug purpose, we need to check HUBP_CLOCK_ENABLE in DTN
log debugfs on Navi.

[How]
Add related register read in dcn20_hubp.c.

Signed-off-by: Leo (Hanghong) Ma <hanghong.ma@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/display: Renoir chroma viewport WA Read the correct register
Joseph Gravenor [Thu, 24 Oct 2019 17:55:10 +0000 (13:55 -0400)]
drm/amd/display: Renoir chroma viewport WA Read the correct register

[why]
Before we were reading registers specific to luma size, which caused a black line
to appear on the screen from time to time, as although the luma row height
is generally the same as the chroma row height for the video case, it will sometimes
be one more

[how]
Read the register specific for the chroma size

Signed-off-by: Joseph Gravenor <joseph.gravenor@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/display: Renoir chroma viewport WA change formula
Joseph Gravenor [Thu, 17 Oct 2019 15:56:34 +0000 (11:56 -0400)]
drm/amd/display: Renoir chroma viewport WA change formula

[why]
we want to increase the pte row plus 1 line if chroma viewport
height is integer multiple of the pte row height

[how]
instead of ceiling viewport height, we floor it. this allows
us to accommodate both cases: those where the chroma viewport
height is integer multiple of the pte row height and those where
it is not

Signed-off-by: Joseph Gravenor <joseph.gravenor@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/display: add automated audio test support
abdoulaye berthe [Fri, 26 Jul 2019 15:25:43 +0000 (11:25 -0400)]
drm/amd/display: add automated audio test support

Signed-off-by: abdoulaye berthe <abdoulaye.berthe@amd.com>
Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amdgpu/dm: Do not throw an error for a display with no audio
Chris Wilson [Thu, 14 Nov 2019 20:44:13 +0000 (20:44 +0000)]
drm/amdgpu/dm: Do not throw an error for a display with no audio

An old display with no audio may not have an EDID with a CEA block, or
it may simply be too old to support audio. This is not a driver error,
so don't flag it as such.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=112140
References: ae2a3495973e ("drm/amd: be quiet when no SAD block is found")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Harry Wentland <harry.wentland@amd.com>
Cc: Jean Delvare <jdelvare@suse.de>
Cc: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/display: remove set but not used variable 'min_content'
zhengbin [Thu, 14 Nov 2019 12:36:27 +0000 (20:36 +0800)]
drm/amd/display: remove set but not used variable 'min_content'

Fixes gcc '-Wunused-but-set-variable' warning:

drivers/gpu/drm/amd/display/modules/color/color_gamma.c: In function build_freesync_hdr:
drivers/gpu/drm/amd/display/modules/color/color_gamma.c:830:20: warning: variable min_content set but not used [-Wunused-but-set-variable]

It is not used since commit 50575eb5b339 ("drm/amd/display:
Only use EETF when maxCL > max display")

Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: zhengbin <zhengbin13@huawei.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/display: remove set but not used variable 'bp' in bios_parser.c
zhengbin [Thu, 14 Nov 2019 12:36:26 +0000 (20:36 +0800)]
drm/amd/display: remove set but not used variable 'bp' in bios_parser.c

Fixes gcc '-Wunused-but-set-variable' warning:

drivers/gpu/drm/amd/display/dc/bios/bios_parser.c: In function bios_get_board_layout_info:
drivers/gpu/drm/amd/display/dc/bios/bios_parser.c:2743:22: warning: variable bp set but not used [-Wunused-but-set-variable]

It is introduced by commit 1eeedbcc20d6 ("drm/amd/display:
get board layout for edid emulation"), but never used,
so remove it.

Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: zhengbin <zhengbin13@huawei.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/display: remove set but not used variable 'bp' in bios_parser2.c
zhengbin [Thu, 14 Nov 2019 12:36:25 +0000 (20:36 +0800)]
drm/amd/display: remove set but not used variable 'bp' in bios_parser2.c

Fixes gcc '-Wunused-but-set-variable' warning:

drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c: In function bios_get_board_layout_info:
drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c:1826:22: warning: variable bp set but not used [-Wunused-but-set-variable]

It is introduced by commit 1eeedbcc20d6 ("drm/amd/display:
get board layout for edid emulation"), but never used,
so remove it.

Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: zhengbin <zhengbin13@huawei.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/display: remove set but not used variable 'old_plane_crtc'
zhengbin [Thu, 14 Nov 2019 12:36:24 +0000 (20:36 +0800)]
drm/amd/display: remove set but not used variable 'old_plane_crtc'

Fixes gcc '-Wunused-but-set-variable' warning:

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c: In function dm_determine_update_type_for_commit:
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c:6516:36: warning: variable old_plane_crtc set but not used [-Wunused-but-set-variable]

It is introduced by commit a87fa9938749 ("drm/amd/display:
Build stream update and plane updates in dm"), but never used,
so remove it.

Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: zhengbin <zhengbin13@huawei.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amdgpu/nv: add asic func for fetching vbios from rom directly
Alex Deucher [Wed, 13 Nov 2019 19:27:54 +0000 (14:27 -0500)]
drm/amdgpu/nv: add asic func for fetching vbios from rom directly

Needed as a fallback if the vbios can't be fetched by other means.

Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amdgpu/soc15: move struct definition around to align with other soc15 asics
Alex Deucher [Tue, 15 Oct 2019 20:21:27 +0000 (16:21 -0400)]
drm/amdgpu/soc15: move struct definition around to align with other soc15 asics

Move reset_method next to reset callback to match the struct layout and
the other definition in this file.

Reviewed-by: Yong Zhao <Yong.Zhao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amdgpu: put flush_delayed_work at first
Yintian Tao [Mon, 18 Nov 2019 08:06:00 +0000 (16:06 +0800)]
drm/amdgpu: put flush_delayed_work at first

There is one regression from 042f3d7b745cd76aa
To put flush_delayed_work after adev->shutdown = true
which will make amdgpu_ih_process not response the irq
At last, all ib ring tests will be failed just like below

[drm] amdgpu: finishing device.
[drm] Fence fallback timer expired on ring gfx
[drm] Fence fallback timer expired on ring comp_1.0.0
[drm] Fence fallback timer expired on ring comp_1.1.0
[drm] Fence fallback timer expired on ring comp_1.2.0
[drm] Fence fallback timer expired on ring comp_1.3.0
[drm] Fence fallback timer expired on ring comp_1.0.1
amdgpu 0000:00:07.0: [drm:amdgpu_ib_ring_tests [amdgpu]] *ERROR* IB test failed on comp_1.1.1 (-110).
amdgpu 0000:00:07.0: [drm:amdgpu_ib_ring_tests [amdgpu]] *ERROR* IB test failed on comp_1.2.1 (-110).
amdgpu 0000:00:07.0: [drm:amdgpu_ib_ring_tests [amdgpu]] *ERROR* IB test failed on comp_1.3.1 (-110).
amdgpu 0000:00:07.0: [drm:amdgpu_ib_ring_tests [amdgpu]] *ERROR* IB test failed on sdma0 (-110).
amdgpu 0000:00:07.0: [drm:amdgpu_ib_ring_tests [amdgpu]] *ERROR* IB test failed on sdma1 (-110).
amdgpu 0000:00:07.0: [drm:amdgpu_ib_ring_tests [amdgpu]] *ERROR* IB test failed on uvd_enc_0.0 (-110).
amdgpu 0000:00:07.0: [drm:amdgpu_ib_ring_tests [amdgpu]] *ERROR* IB test failed on vce0 (-110).
[drm:amdgpu_device_delayed_init_work_handler [amdgpu]] *ERROR* ib ring test failed (-110).

v2: replace cancel_delayed_work_sync() with flush_delayed_work()

Signed-off-by: Yintian Tao <yttao@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amdgpu/vcn2.5: fix the enc loop with hw fini
Leo Liu [Fri, 15 Nov 2019 22:10:34 +0000 (17:10 -0500)]
drm/amdgpu/vcn2.5: fix the enc loop with hw fini

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amdkfd: remove set but not used variable 'top_dev'
zhengbin [Thu, 14 Nov 2019 03:20:25 +0000 (11:20 +0800)]
drm/amdkfd: remove set but not used variable 'top_dev'

Fixes gcc '-Wunused-but-set-variable' warning:

drivers/gpu/drm/amd/amdkfd/kfd_iommu.c: In function kfd_iommu_device_init:
drivers/gpu/drm/amd/amdkfd/kfd_iommu.c:65:30: warning: variable top_dev set but not used [-Wunused-but-set-variable]

Reported-by: Hulk Robot <hulkci@huawei.com>
Fixes: 1ae99eab34f9 ("drm/amdkfd: Initialize HSA_CAP_ATS_PRESENT capability in topology codes")
Signed-off-by: zhengbin <zhengbin13@huawei.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/powerplay: correct fine grained dpm force level setting
Evan Quan [Thu, 14 Nov 2019 08:58:31 +0000 (16:58 +0800)]
drm/amd/powerplay: correct fine grained dpm force level setting

For fine grained dpm, there is only two levels supported. However
to reflect correctly the current clock frequency, there is an
intermediate level faked. Thus on forcing level setting, we
need to treat level 2 correctly as level 1.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/powerplay: issue no PPSMC_MSG_GetCurrPkgPwr on unsupported ASICs
Evan Quan [Thu, 14 Nov 2019 07:30:39 +0000 (15:30 +0800)]
drm/amd/powerplay: issue no PPSMC_MSG_GetCurrPkgPwr on unsupported ASICs

Otherwise, the error message prompted will confuse user.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/powerplay: issue BTC on Navi during SMU setup
Evan Quan [Tue, 12 Nov 2019 06:18:54 +0000 (14:18 +0800)]
drm/amd/powerplay: issue BTC on Navi during SMU setup

RunBTC is added for Navi ASIC on hardware setup.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/powerplay: avoid DPM reenable process on Navi1x ASICs V2
Evan Quan [Mon, 11 Nov 2019 09:15:02 +0000 (17:15 +0800)]
drm/amd/powerplay: avoid DPM reenable process on Navi1x ASICs V2

Otherwise, without RLC reinitialization, the DPM reenablement
will fail. That affects the custom pptable uploading.

V2: setting/clearing uploading_custom_pp_table in
    smu_sys_set_pp_table()

Reported-by: Matt Coffin <mcoffin13@gmail.com>
Signed-off-by: Evan Quan <evan.quan@amd.com>
Tested-by: Matt Coffin <mcoffin13@gmail.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amdgpu: enable Arcturus JPEG2.5 block
Leo Liu [Mon, 11 Nov 2019 15:33:57 +0000 (10:33 -0500)]
drm/amdgpu: enable Arcturus JPEG2.5 block

It also doen't care about FW loading type, so enabling it directly.

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amdgpu: enable Arcturus CG for VCN and JPEG blocks
Leo Liu [Mon, 11 Nov 2019 15:27:03 +0000 (10:27 -0500)]
drm/amdgpu: enable Arcturus CG for VCN and JPEG blocks

Arcturus VCN and JPEG only got CG support, and no PG support

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amdgpu: move JPEG2.5 out from VCN2.5
Leo Liu [Mon, 11 Nov 2019 14:56:32 +0000 (09:56 -0500)]
drm/amdgpu: move JPEG2.5 out from VCN2.5

And clean up the duplicated stuff

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amdgpu: enable JPEG2.0 for Navi1x and Renoir
Leo Liu [Fri, 8 Nov 2019 20:01:42 +0000 (15:01 -0500)]
drm/amdgpu: enable JPEG2.0 for Navi1x and Renoir

By adding JPEG IP block to the family

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amdgpu: add driver support for JPEG2.0 and above
Leo Liu [Fri, 8 Nov 2019 20:00:58 +0000 (15:00 -0500)]
drm/amdgpu: add driver support for JPEG2.0 and above

By using JPEG IP block type

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amdgpu: enable JPEG2.0 dpm
Leo Liu [Tue, 12 Nov 2019 16:57:36 +0000 (11:57 -0500)]
drm/amdgpu: enable JPEG2.0 dpm

By using its own enabling function

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/powerplay: set JPEG to SMU dpm
Leo Liu [Fri, 8 Nov 2019 19:38:08 +0000 (14:38 -0500)]
drm/amd/powerplay: set JPEG to SMU dpm

By using its own IP block type.

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/powerplay: add JPEG power control for Renoir
Leo Liu [Fri, 8 Nov 2019 19:33:10 +0000 (14:33 -0500)]
drm/amd/powerplay: add JPEG power control for Renoir

By using its own JPEG PowerUp and PowerDown messages

v2: add argument to PowerDownJpeg message

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/powerplay: add Powergate JPEG for Renoir
Leo Liu [Fri, 8 Nov 2019 19:22:06 +0000 (14:22 -0500)]
drm/amd/powerplay: add Powergate JPEG for Renoir

Similar to SDMA, VCN etc.

v2: add argument to both PowerUpJpeg and PowerDownJpeg messages

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/powerplay: add JPEG power control for Navi1x
Leo Liu [Fri, 8 Nov 2019 19:11:01 +0000 (14:11 -0500)]
drm/amd/powerplay: add JPEG power control for Navi1x

By separating the JPEG power feature, and using its
own PowerUp and PowerDown messages

v2: remove PowerUpJpeg message argument

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/powerplay: add JPEG Powerplay interface
Leo Liu [Fri, 8 Nov 2019 18:54:33 +0000 (13:54 -0500)]
drm/amd/powerplay: add JPEG Powerplay interface

It will be used for different SMU specific to HW

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amdgpu: add PG and CG for JPEG2.0
Leo Liu [Mon, 11 Nov 2019 20:09:25 +0000 (15:09 -0500)]
drm/amdgpu: add PG and CG for JPEG2.0

And enable them for Navi1x and Renoir

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amdgpu: add JPEG PG and CG interface
Leo Liu [Fri, 8 Nov 2019 18:17:52 +0000 (13:17 -0500)]
drm/amdgpu: add JPEG PG and CG interface

From JPEG2.0, it will use its own PG/CG

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amdgpu: remove unnecessary JPEG2.0 code from VCN2.0
Leo Liu [Fri, 8 Nov 2019 18:30:15 +0000 (13:30 -0500)]
drm/amdgpu: remove unnecessary JPEG2.0 code from VCN2.0

They are no longer needed, using from JPEG2.0 instead.

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amdgpu: add JPEG v2.0 function supports
Leo Liu [Fri, 8 Nov 2019 18:26:46 +0000 (13:26 -0500)]
drm/amdgpu: add JPEG v2.0 function supports

It got separated from VCN2.0 with a new jpeg_v2_0_ip_block

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amdgpu: add JPEG common functions to amdgpu_jpeg
Leo Liu [Fri, 8 Nov 2019 18:12:05 +0000 (13:12 -0500)]
drm/amdgpu: add JPEG common functions to amdgpu_jpeg

They will be used for JPEG2.0 and later.

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amdgpu: add JPEG IP block type
Leo Liu [Fri, 8 Nov 2019 17:44:54 +0000 (12:44 -0500)]
drm/amdgpu: add JPEG IP block type

From VCN2.0, JPEG2.0 is a separated IP block.

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amdgpu: use the JPEG structure for general driver support
Leo Liu [Fri, 8 Nov 2019 15:23:14 +0000 (10:23 -0500)]
drm/amdgpu: use the JPEG structure for general driver support

JPEG1.0 will be functional along with VCN1.0

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amdgpu: separate JPEG1.0 code out from VCN1.0
Leo Liu [Fri, 8 Nov 2019 15:17:06 +0000 (10:17 -0500)]
drm/amdgpu: separate JPEG1.0 code out from VCN1.0

For VCN1.0, the separation is just in code wise, JPEG1.0 HW is still
included in the VCN1.0 HW.

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>