The watermarks it should calculate against are the old optimal watermarks.
The currently active crtc watermarks are pure fiction, and are invalid in
case of a nonblocking modeset, page flip enabling/disabling planes or any
other reason.
When the crtc is disabled or during a modeset the intermediate watermarks
don't need to be programmed separately, and could be directly assigned
to the optimal watermarks.
Changes since v1:
- Use intel_atomic_get_old_crtc_state. (ville)
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171019151341.4579-2-maarten.lankhorst@linux.intel.com
[mlankhorst: Add cc stable and bugzilla link, since previous patch doesn't fix issue by itself] Cc: stable@vger.kernel.org #v4.8+
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102373
(cherry picked from commit b6b178a77210055b153dbc175e4468bd3c7122df) Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Joonas Lahtinen [Mon, 23 Oct 2017 15:32:09 +0000 (18:32 +0300)]
drm/i915: Disable lazy PPGTT page table optimization for vGPU
When running under virtualization (vGPU active), we must disable
the lazy PPGTT page table initialization optimization introduced by
commit 14826673247e ("drm/i915: Only initialize partially filled
pagetables").
We must do this because GVT-g makes unduly assumptions about guest
behaviour, which this optimization breaks. This results in following
looking errors in the host:
ERROR gvt: guest page write error -22, gfn 0x7ada8, pa 0x7ada89a8, var 0x6, len 1
The real fix is to not to depend on i915 driver behaviour, but instead
either rely on only the contracts that i915 has with the hardware, or
add some paravirtualization. While the real fix is en route, it won't
be finished in time for 4.15, so the best option is to disable the
optimization for now when vGPU is active to avoid breaking 4.15 guests
in existing VM environments.
Fixes: 14826673247e ("drm/i915: Only initialize partially filled pagetables") Suggested-by: Xiaolin Zhang <xiaolin.zhang@intel.com> Signed-off-by: Xiaolin Zhang <xiaolin.zhang@intel.com>
[Joonas: Rewrote the commit message and added tags.] Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Zhenyu Wang <zhenyuw@linux.intel.com> Cc: Zhi Wang <zhi.a.wang@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Matthew Auld <matthew.auld@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Chris Wilson <chris@chris-wilson.co.uk> Acked-by: Zhenyu Wang <zhenyuw@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171023153209.10527-1-joonas.lahtinen@linux.intel.com
(cherry picked from commit 22a8a4fc93b14b5a8cfc785edbdc6f7bd98bffb6) Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Chris Wilson [Tue, 24 Oct 2017 11:55:01 +0000 (12:55 +0100)]
drm/i915/execlists: Remove the priority "optimisation"
Originally we set the priority to max upon inserting the request into
the execlists queue (and removing it from the scheduler lists). We could
then use the prio==INT_MAX as a shortcut within execlists_schedule() to
detect the end of the dependency chain. Since commit 1f181225f8ec
("drm/i915/execlists: Keep request->priority for its lifetime") this is
no longer true as we use the request completion as an indicator the
schedule dependency chain is complete instead. (This allows us to then
reschedule requests even when its context is in flight.) However, this
makes the GEM_BUG_ON() inside execlists_schedule() racy as we may change
the rq->prio at the same time. As the assertion is useful, let's keep
the assertion and remove the micro-optimisation.
Chris Wilson [Mon, 23 Oct 2017 21:32:36 +0000 (22:32 +0100)]
drm/i915: Filter out spurious execlists context-switch interrupts
Back in commit a4b2b01523a8 ("drm/i915: Don't mark an execlists
context-switch when idle") we noticed the presence of late
context-switch interrupts. We were able to filter those out by looking
at whether the ELSP remained active, but in commit beecec901790
("drm/i915/execlists: Preemption!") that became problematic as we now
anticipate receiving a context-switch event for preemption while ELSP
may be empty. To restore the spurious interrupt suppression, add a
counter for the expected number of pending context-switches and skip if
we do not need to handle this interrupt to make forward progress.
v2: Don't forget to switch on for preempt.
v3: Reduce the counter to a on/off boolean tracker. Declare the HW as
active when we first submit, and idle after the final completion event
(with which we confirm the HW says it is idle), and track each source
of activity separately. With a finite number of sources, it should aide
us in debugging which gets stuck.
Fixes: beecec901790 ("drm/i915/execlists: Preemption!") Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Michal Winiarski <michal.winiarski@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Arkadiusz Hiler <arkadiusz.hiler@intel.com> Cc: Mika Kuoppala <mika.kuoppala@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171023213237.26536-3-chris@chris-wilson.co.uk Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
(cherry picked from commit 4a118ecbe99c93cf9f9582e83a88d03f18d6cb84) Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Dave Airlie [Mon, 6 Nov 2017 06:18:59 +0000 (16:18 +1000)]
Merge branch 'drm-next-4.15' of git://people.freedesktop.org/~agd5f/linux into drm-next
some more amd/ttm fixes.
* 'drm-next-4.15' of git://people.freedesktop.org/~agd5f/linux:
drm/ttm: Downgrade pr_err to pr_debug for memory allocation failures
drm/ttm: Always and only destroy bo->ttm_resv in ttm_bo_release_list
drm/amd/amdgpu: Enabling ACP clock in hw_init (v2)
drm/amdgpu/virt: don't dereference undefined 'module' struct
Michel Dänzer [Fri, 3 Nov 2017 15:00:35 +0000 (16:00 +0100)]
drm/ttm: Downgrade pr_err to pr_debug for memory allocation failures
Memory allocation failure should generally be handled gracefully by
callers. In particular, with transparent hugepage support, attempts
to allocate huge pages can fail under memory pressure, but the callers
fall back to allocating individual pages instead. In that case, there
would be spurious
[TTM] Unable to get page %u
error messages in dmesg.
Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Michel Dänzer [Fri, 3 Nov 2017 15:00:35 +0000 (16:00 +0100)]
drm/ttm: Always and only destroy bo->ttm_resv in ttm_bo_release_list
Fixes a use-after-free due to a race condition in
ttm_bo_cleanup_refs_and_unlock, which allows one task to reserve a BO
and destroy its ttm_resv while another task is waiting for it to signal
in reservation_object_wait_timeout_rcu.
v2:
* Always initialize bo->ttm_resv in ttm_bo_init_reserved
(Christian König)
Fixes: 0d2bd2ae045d "drm/ttm: fix memory leak while individualizing BOs" Reviewed-by: Chunming Zhou <david1.zhou@amd.com> # v1 Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/amdgpu: Enabling ACP clock in hw_init (v2)
Enabling of ACP in hw_init does away with requirement of order
of probe on designware_i2s and acp dma driver. designware_i2s
reads i2s registers and this use to fail if acp dma driver was not probed
prior to it.
Dave Airlie [Fri, 3 Nov 2017 19:43:44 +0000 (05:43 +1000)]
Merge tag 'drm-intel-next-2017-10-23' of git://anongit.freedesktop.org/drm/drm-intel into drm-next
This time really the last i915 batch for v4.15:
- PSR state tracking in crtc state (Ville)
- Fix eviction when the GGTT is idle but full (Chris)
- BDW DP aux channel timeout fix (James)
- LSPCON detection fixes (Shashank)
- Use for_each_pipe to iterate over pipes (Mika Kahola)
- Replace *_reference/unreference() or *_ref/unref with _get/put() (Harsha)
- Refactoring and preparation for DDI encoder type cleanup (Ville)
- Broadwell DDI FDI buf translation fix (Chris)
- Read CSB and CSB write pointer from HWSP in GVT-g VM if available (Weinan)
- GuC/HuC firmware loader refactoring (Michal)
- Make shrinking more effective and not stall so much (Chris)
- Cannonlake PLL fixes (Rodrigo)
- DP MST connector error propagation fixes (James)
- Convert timers to use timer_setup (Kees Cook)
- Skylake plane enable/disable unification (Juha-Pekka)
- Fix to actually free driver internal objects when requested (Chris)
- DDI buf trans refactoring (Ville)
- Skip waking the device to service pwrite (Chris)
- Improve DSI VBT backlight parsing abstraction (Madhav)
- Cannonlake VBT DDC pin mapping fix (Rodrigo)
* tag 'drm-intel-next-2017-10-23' of git://anongit.freedesktop.org/drm/drm-intel: (87 commits)
drm/i915: Update DRIVER_DATE to 20171023
drm/i915/cnl: Map VBT DDC Pin to BSpec DDC Pin.
drm/i915: Let's use more enum intel_dpll_id pll_id.
drm/i915: Use existing DSI backlight ports info
drm/i915: Parse DSI backlight/cabc ports.
drm/i915: Skip waking the device to service pwrite
drm/i915/crt: split compute_config hook by platforms
drm/i915: remove g4x lowfreq_avail and has_pipe_cxsr
drm/i915: Drop the redundant hdmi prefix/suffix from a lot of variables
drm/i915: Unify error handling for missing DDI buf trans tables
drm/i915: Centralize the SKL DDI A/E vs. B/C/D buf trans handling
drm/i915: Kill off the BXT buf_trans default_index
drm/i915: Pass encoder type to cnl_ddi_vswing_sequence() explicitly
drm/i915: Integrate BXT into intel_ddi_dp_voltage_max()
drm/i915: Pass the level to intel_prepare_hdmi_ddi_buffers()
drm/i915: Pass the encoder type explicitly to skl_set_iboost()
drm/i915: Extract intel_ddi_get_buf_trans_hdmi()
drm/i915: Relocate intel_ddi_get_buf_trans_*() functions
drm/i915: Flush the idle-worker for debugfs/i915_drop_caches
drm/i915: adjust get_crtc_fence_y_offset() to use base.y instead of crtc.y
...
Accessing the THIS_MODULE directly is only possible when modules
are enabled, otherwise we get a build failure:
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c: In function 'amdgpu_virt_init_data_exchange':
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c:331:20: error: dereferencing pointer to incomplete type 'struct module'
Further, THIS_MODULE is NULL when the driver is built-in, so the
code would likely cause a NULL pointer dereference.
This adds an #ifdef check to avoid the compile-time error, plus
a NULL pointer check before dereferencing THIS_MODULE. It might
be better to find a way to avoid using the module version
altogether.
Fixes: 2dc8f81e4f82 ("drm/amdgpu: SR-IOV data exchange between PF&VF") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Reviewed-By: Xiangliang Yu <Xiangliang.Yu@amd.com>
Dave Airlie [Thu, 2 Nov 2017 23:17:08 +0000 (09:17 +1000)]
Merge branch 'linux-4.15' of git://github.com/skeggsb/linux into drm-next
nouveau next fixes.
Fixes arm32 build.
* 'linux-4.15' of git://github.com/skeggsb/linux:
drm/nouveau/bios/timing: mark expected switch fall-throughs
drm/nouveau/devinit/nv04: mark expected switch fall-throughs
drm/nouveau/bios: make const arrays hwsq_signature and edid_sig static
drm/nouveau/core/memory: fix missing mutex unlock
drm/nouveau/mmu: swap out round for ALIGN
Dave Airlie [Thu, 2 Nov 2017 19:12:24 +0000 (05:12 +1000)]
Merge tag 'drm-amdkfd-next-2017-11-02' of git://people.freedesktop.org/~gabbayo/linux into drm-next
- Usermode Events
The current events code implemented some data structures (waitqueue, fifo)
that were already implemented in the kernel. The patches below addresses
this issue by replacing them with the standard kernel implementation.
In addition, they simplify allocation of events IDs and memory for the events.
The patches also increase the maximum number of events while maintaining
compatibility with the older userspace library.
- Remove radeon support
Because Kaveri is fully supported in amdgpu and because current and future
versions of userspace libraries will only support amdgpu, we removed radeon
support from kfd. Current users can move to amdgpu while using the same
userspace libraries.
- Various bug fixes and cleanups
* tag 'drm-amdkfd-next-2017-11-02' of git://people.freedesktop.org/~gabbayo/linux: (26 commits)
drm/amdkfd: Minor cleanups
drm/amdkfd: Update queue_count before mapping queues
drm/amdkfd: Cleanup DQM ASIC-specific ops
drm/amdkfd: Register/Deregister process on qpd resolution
drm/amdkfd: Fix debug unregister procedure on process termination
drm/amdkfd: Avoid calling amd_iommu_unbind_pasid() when suspending
drm/amdkfd: Disable CP/SDMA ring/doorbell in MQD
drm/amdkfd: Clean up the data structure in kfd_process
drm/radeon: deprecate and remove KFD interface
drm/amdkfd: use a high priority workqueue for IH work
drm/amdkfd: wait only for IH work on IH exit
drm/amdkfd: increase IH num entries to 8192
drm/amdkfd: use standard kernel kfifo for IH
drm/amdkfd: increase limit of signal events to 4096 per process
drm/amdkfd: Make event limit dependent on user mode mapping size
drm/amdkfd: Use IH context ID for signal lookup
drm/amdkfd: Simplify event ID and signal slot management
drm/amdkfd: Simplify events page allocator
drm/amdkfd: Use wait_queue_t to implement event waiting
drm/amdkfd: remove redundant kfd_event_waiter.input_index
...
Dave Airlie [Thu, 2 Nov 2017 19:10:37 +0000 (05:10 +1000)]
Merge branch 'drm-next-4.15' of git://people.freedesktop.org/~agd5f/linux into drm-next
Some amdgpu/ttm fixes.
* 'drm-next-4.15' of git://people.freedesktop.org/~agd5f/linux:
drm/amd/powerplay: wrong control mode cause the fan spins faster unnecessarily
drm/amd/powerplay: fix memory leak of hardcoded pptable
drm/amdgpu:add fw-vram-usage for atomfirmware
drm/radeon: fix atombios on big endian
drm/ttm:fix memory leak due to individualize
drm/amdgpu: fix error handling in amdgpu_bo_do_create
drm/ttm: once more fix ttm_buffer_object_transfer
drm/amd/powerplay: change ASIC temperature reading on Vega10
Dave Airlie [Thu, 2 Nov 2017 04:00:35 +0000 (14:00 +1000)]
Merge branch 'linux-4.15' of git://github.com/skeggsb/linux into drm-next
- Pascal temperature sensor support
- Improved BAR2 handling, greatly reduces time required to suspend
- Rework of the MMU code
- Allows us to properly support Pascal's new MMU layout (implemented)
- Lays the groundwork for improved userspace APIs later
- Misc other fixes
* 'linux-4.15' of git://github.com/skeggsb/linux: (151 commits)
drm/nouveau/gr/gf100-: don't prevent module load if firmware missing
drm/nouveau/mmu: remove old vmm frontend
drm/nouveau: improve selection of GPU page size
drm/nouveau: switch over to new memory and vmm interfaces
drm/nouveau: remove unused nouveau_fence_work()
drm/nouveau: queue delayed unmapping of VMAs on client workqueue
drm/nouveau: implement per-client delayed workqueue with fence support
drm/nouveau: determine memory class for each client
drm/nouveau: pass handle of vmm object to channel allocation ioctls
drm/nouveau: switch to vmm limit
drm/nouveau: allocate vmm object for every client
drm/nouveau: replace use of cpu_coherent with memory types
drm/nouveau: use nvif_mmu_type to determine BAR1 caching
drm/nouveau: fetch memory type indices that we care about for ttm
drm/nouveau: consolidate handling of dma mask
drm/nouveau: check kind validity against mmu object
drm/nouveau: allocate mmu object for every client
drm/nouveau: remove trivial cases of nvxx_device() usage
drm/nouveau/mmu: define user interfaces to mmu vmm opertaions
drm/nouveau/mmu: define user interfaces to mmu memory allocation
...
Ben Skeggs [Tue, 31 Oct 2017 17:56:19 +0000 (03:56 +1000)]
drm/nouveau: check kind validity against mmu object
This is already handled in the top-level gem_new() ioctl in another manner,
but this will be removed in a future commit.
Ideally we'd not need to check up-front at all, and let the VMM code handle
error checking, but there are paths in the current BO management code where
this isn't possible due to map() not always being called during BO creation,
and map() calls not being allowed to fail during buffer migration.
Ben Skeggs [Tue, 31 Oct 2017 17:56:19 +0000 (03:56 +1000)]
drm/nouveau: remove explicit unmaps
If the VMA is being deleted, we don't need to explicity unmap first
anymore. The MMU code will automatically merge the operations into
a single page tree walk.
Ben Skeggs [Tue, 31 Oct 2017 17:56:19 +0000 (03:56 +1000)]
drm/nouveau/mmu: implement new vmm frontend
These are the new priviledged interfaces to the VMM backends, and expose
some functionality that wasn't previously available.
It's now possible to allocate a chunk of address-space (even all of it),
without causing page tables to be allocated up-front, and then map into
it at arbitrary locations. This is the basic primitive used to support
features such as sparse mapping, or to allow userspace control over its
own address-space, or HMM (where the GPU driver isn't in control of the
address-space layout).
Rather than being tied to a subtle combination of memory object and VMA
properties, arguments that control map flags (ro, kind, etc) are passed
explicitly at map time.
The compatibility hacks to implement the old frontend on top of the new
driver backends have been replaced with something similar to implement
the old frontend's interfaces on top of the new frontend.
Ben Skeggs [Tue, 31 Oct 2017 17:56:19 +0000 (03:56 +1000)]
drm/nouveau/mmu/gp100,gp10b: implement new vmm backend
Adds support for:
- 64KiB/2MiB big page sizes (128KiB not supported by HW with new PT layout).
- System-memory PTs.
- LPTE "invalid" state.
- (Tegra) Use of video memory aperture.
- Sparse PDEs/PTEs.
- Additional blocklinear kinds.
- 49-bit address-space.
GP100 supports an entirely new 5-level page table layout that provides
an expanded 49-bit address-space. It also supports the layout present
on previous generations, which we've been making do with until now.
This commit implements support for the new layout, and enables it by
default.
Ben Skeggs [Tue, 31 Oct 2017 17:56:19 +0000 (03:56 +1000)]
drm/nouveau/mmu/gk104,gk20a: implement new vmm backend
Adds support for:
- 64KiB big page size.
- System-memory PTs.
- LPTE "invalid" state.
- (Tegra) Use of video memory aperture.
Adds support for marking LPTEs invalid, resulting in the corresponding
SPTEs being ignored, which is supposed to speed up TLB invalidates.
On The Tegra side, this will switch to using the video memory aperture
for all mappings. The HW will still target non-coherent system memory,
but this aperture needs to be selected in order to support compression.
Tegra's instmem backend somewhat cheated to get this effect previously.
Ben Skeggs [Tue, 31 Oct 2017 17:56:19 +0000 (03:56 +1000)]
drm/nouveau/mmu: implement new vmm backend
This is the common code to support a rework of the VMM backends.
It adds support for more than 2 levels of page table nesting, which
is required to be able to support GP100's MMU layout.
Sparse mappings (that don't cause MMU faults when accessed) are now
supported, where the backend provides it.
Dual-PT handling had to become more sophisticated to support sparse,
but this also allows us to support an optimisation the MMU provides
on GK104 and newer.
Certain operations can now be combined into a single page tree walk
to avoid some overhead, but also enables optimsations like skipping
PTE unmap writes when the PT will be destroyed anyway.
The old backend has been hacked up to forward requests onto the new
backend, if present, so that it's possible to bisect between issues
in the backend changes vs the upcoming frontend changes.
Until the new frontend has been merged, new backends will leak BAR2
page tables on module unload. This is expected, and it's not worth
the effort of hacking around this as it doesn't effect runtime.
Ben Skeggs [Tue, 31 Oct 2017 17:56:19 +0000 (03:56 +1000)]
drm/nouveau/ltc/gm200: limit NV_MMU_PTE_COMPTAGLINE bits to 16 where required
If NV_PFB_MMU_CTRL_USE_FULL_COMP_TAG_LINE is TRUE, then the last bit of
NV_MMU_PTE_COMPTAGLINE is re-purposed to select the upper/lower half of
a compression tag when using 64KiB big pages.
Ben Skeggs [Tue, 31 Oct 2017 17:56:19 +0000 (03:56 +1000)]
drm/nouveau/mmu: implement base for new vm management
This is the first chunk of the new VMM code that provides the structures
needed to describe a GPU virtual address-space layout, as well as common
interfaces to handle VMM creation, and connecting instances to a VMM.
The constructor now allocates the PD itself, rather than having the user
handle that manually. This won't/can't be used until after all backends
have been ported to these interfaces, so a little bit of memory will be
wasted on Fermi and newer for a couple of commits in the series.
Compatibility has been hacked into the old code to allow each GPU backend
to be ported individually.
GP100 "big" (which is a funny name, when it supports "even bigger") page
tables are small enough that we want to be able to suballocate them from
a larger block of memory.
This builds on the previous page table cache interfaces so that the VMM
code doesn't need to know the difference.
Ben Skeggs [Tue, 31 Oct 2017 17:56:19 +0000 (03:56 +1000)]
drm/nouveau/mmu: implement page table cache
Builds up and maintains a small cache of each page table size in order
to reduce the frequency of expensive allocations, particularly in the
pathological case where an address range ping-pongs between allocated
and free.
Ben Skeggs [Tue, 31 Oct 2017 17:56:19 +0000 (03:56 +1000)]
drm/nouveau: allocate vram with nvkm_ram_get()
This will cause a subtle behaviour change on GPUs that are in mixed-memory
configurations in that VRAM in the degraded section of VRAM will no longer
be used for TTM buffer objects.
That section of VRAM is not meant to be used for displayable/compressed
surfaces, and we have no reliable way with the current interfaces to be
able to make that decision properly.
Ben Skeggs [Tue, 31 Oct 2017 17:56:19 +0000 (03:56 +1000)]
drm/nouveau/fb/ram: add interface to allocate vram as an nvkm_memory object
Upcoming MMU changes use nvkm_memory as its basic representation of memory,
so we need to be able to allocate VRAM like this.
The code is basically identical to the current chipset-specific allocators,
minus support for compression tags (which will be handled elsewhere anyway).
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