Enable peak profiling mode shader/memory clocks reporting for swsmu
framework.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Mon, 5 Dec 2022 07:34:39 +0000 (15:34 +0800)]
drm/amd/pm: drop unused SMU v13 API
The API is not in use. And it's unlikely to be used in
the future either.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
The missing DPCD definitions from DP2.0 spec is as follows:
DOWNSPREAD_CTRL (107h):
FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE (bit 6)
For sink devices that support Adaptive-Sync operation
and Panel Replay
DPRX_FEATURE_ENUMERATION_LIST_CONT_1 (2214h):
ADAPTIVE_SYNC_SDP_SUPPORTED (bit 0)
Bit to check sink device has Adaptive-Sync capability
AS_SDP_FIRST_HALF_LINE_OR_3840_PIXEL_CYCLE_WINDOW_NOT_SUPPORTED (bit 1)
A sink device that clears this bit will generate VSync pulse
leading edge of the HDMI output on the line count at which
Adaptive-Sync SDP is received as long as source device transmits
Adaptive-Sync SDP either in first line or first 3840 pixel cycles
of the line whichever occurs first.
VSC_EXT_SDP_FRAMEWORK_VERSION_1_SUPPORTED (bit 4)
Bit to check sink device has SDP framework version 1 capability
Signed-off-by: Sung Joon Kim <Sungjoon.Kim@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/radeon: Replace 1-element arrays with flexible-array members
One-element arrays are deprecated, and we are replacing them with
flexible array members instead. So, replace one-element array with
flexible-array member in structs _ATOM_DISPLAY_OBJECT_PATH,
_ATOM_DISPLAY_OBJECT_PATH_TABLE, _ATOM_OBJECT_TABLE, GOP_VBIOS_CONTENT
_ATOM_GPIO_VOLTAGE_OBJECT_V3 and refactor the rest of the code accordingly.
It's worth mentioning that doing a build before/after this patch
results in no binary output differences.
This helps with the ongoing efforts to tighten the FORTIFY_SOURCE
routines on memcpy() and help us make progress towards globally
enabling -fstrict-flex-arrays=3 [1].
Alvin Lee [Thu, 1 Dec 2022 23:50:57 +0000 (18:50 -0500)]
drm/amd/display: Block FPO / SubVP (DRR) on HDMI VRR configs
[Description]
- Current policy does not support HDMI VRR by default, so we
cannot enable FPO / SubVP (DRR) cases
Reviewed-by: Nevenko Stupar <Nevenko.Stupar@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Jasdeep Dhillon <jdhillon@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aric Cyr [Mon, 5 Dec 2022 04:00:32 +0000 (23:00 -0500)]
drm/amd/display: 3.2.216
This version brings along following fixes:
-Fix array index out of bound error
-Speed up DML fast vadlaite
-Implement multiple secure display
-MST HDCP for multiple display
-Add DPIA notification
-Add support for three new square pattern variant
Fangzhi Zuo [Tue, 22 Nov 2022 16:14:06 +0000 (11:14 -0500)]
drm/amd/display: Demote Error Level When ODM Transition Supported
[Why && How]
On dcn32, HW supports odm transition in fast update. Hence this
error message is considered false positive. Downgrade the error level
to avoid catching unnecessary attention.
Wenjing Liu [Tue, 22 Nov 2022 23:06:28 +0000 (18:06 -0500)]
drm/amd/display: add support for three new square pattern variants from DP2.1 specs
[why]
DP2.1 specs has brought 3 new variants of sqaure patterns with different
pre-shoot and de-emphasis equalization requirements. The commit adds
logic to identify these variants and apply corresponding eqaulization
requirements into hardware lane settings.
Reviewed-by: George Shen <George.Shen@amd.com> Acked-by: Jasdeep Dhillon <jdhillon@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dillon Varone [Tue, 29 Nov 2022 20:59:20 +0000 (15:59 -0500)]
drm/amd/display: run subvp validation with supported vlevel
[WHY]
Subvp portion validation currently assumes that if vlevel provided does not
support pstate, then none will, and so subvp is not used.
[HOW]
After get vlevel, use lowest vlevel that supports pstate if it
exists, and use that for subvp validation.
Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Jasdeep Dhillon <jdhillon@amd.com> Signed-off-by: Dillon Varone <Dillon.Varone@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alvin Lee [Fri, 2 Dec 2022 16:10:48 +0000 (11:10 -0500)]
drm/amd/display: Clear link res when merging a pipe split
[Description]
- When merging a pipe that was previously pipe split, we need
to also clear the link resources or the next stream/plane that
uses the pipe may have an incorrect link resource state
Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com> Reviewed-by: Nevenko Stupar <Nevenko.Stupar@amd.com> Acked-by: Jasdeep Dhillon <jdhillon@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Roman Li [Thu, 1 Dec 2022 14:49:23 +0000 (09:49 -0500)]
drm/amd/display: Clear MST topology if it fails to resume
[Why]
In case of failure to resume MST topology after suspend, an emtpty
mst tree prevents further mst hub detection on the same connector.
That causes the issue with MST hub hotplug after it's been unplug in
suspend.
[How]
Stop topology manager on the connector after detecting DM_MST failure.
Reviewed-by: Wayne Lin <Wayne.Lin@amd.com> Acked-by: Jasdeep Dhillon <jdhillon@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Wenjing Liu [Thu, 24 Nov 2022 21:40:53 +0000 (16:40 -0500)]
drm/amd/display: use encoder type independent hwss instead of accessing enc directly
[why]
in dc_link_dp there still exist a few places where we call dio encoders
without checking current enabled encoder type.
The change is to make these places to call hwss equivalent functions so
it won't mistakenly program a wrong type encoder.
Reviewed-by: George Shen <George.Shen@amd.com> Acked-by: Jasdeep Dhillon <jdhillon@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Chris Park <Chris.Park@amd.com> Acked-by: Jasdeep Dhillon <jdhillon@amd.com> Signed-off-by: Leo (Hanghong) Ma <hanghong.ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Roman Li [Thu, 1 Dec 2022 14:06:42 +0000 (09:06 -0500)]
drm/amd/display: Fix potential null-deref in dm_resume
[Why]
Fixing smatch error:
dm_resume() error: we previously assumed 'aconnector->dc_link' could be null
[How]
Check if dc_link null at the beginning of the loop,
so further checks can be dropped.
Reported-by: kernel test robot <lkp@intel.com> Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by: Wayne Lin <Wayne.Lin@amd.com> Acked-by: Jasdeep Dhillon <jdhillon@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Ian Chen [Mon, 28 Nov 2022 08:17:34 +0000 (16:17 +0800)]
drm/amd/display: Revert Reduce delay when sink device not able to ACK 00340h write
[WHY]
It causes regression AMD source will not write DPCD 340.
Reviewed-by: Wayne Lin <Wayne.Lin@amd.com> Acked-by: Jasdeep Dhillon <jdhillon@amd.com> Signed-off-by: Ian Chen <ian.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alvin Lee [Sat, 3 Dec 2022 19:41:03 +0000 (14:41 -0500)]
drm/amd/display: Block subvp if center timing is in use
[Description]
- FW scheduling algorithm doesn't take into account of it's
a center timing
- This affects where the subvp mclk switch can be scheduled
(prevents HUBP vline interrupt from coming in if scheduled
incorrectly)
- Block subvp center timing cases for now
Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Jasdeep Dhillon <jdhillon@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Ilya Bakoulin [Thu, 24 Nov 2022 18:58:49 +0000 (13:58 -0500)]
drm/amd/display: Speed up DML fast_validate path
[Why]
Iterating over every voltage state when we need to validate thousands of
configurations all at once (i.e. display hotplug) can take a significant
amount of time.
[How]
Check just the highest voltage state when fast_validate is true to
verify whether the configuration can work at all, then do a proper
validation including all voltage states later when fast_validate is false.
Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Jasdeep Dhillon <jdhillon@amd.com> Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alan Liu [Thu, 24 Nov 2022 12:24:15 +0000 (20:24 +0800)]
drm/amd/display: Fix when disabling secure_display
[Why]
Fix problems when we disable secure_display.
[How]
- Reset secure display context after disabled
- A secure_display_context is dedicate to a crtc, so we set the crtc for
it when we create the context.
Reviewed-by: Wayne Lin <Wayne.Lin@amd.com> Acked-by: Jasdeep Dhillon <jdhillon@amd.com> Signed-off-by: Alan Liu <HaoPing.Liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
Current secure display only work with single display, now make it
work with multiple displays.
[How]
Create secure_display_context for each crtc instance to store its
own Region of Interest (ROI) information.
v2: squash in warning fix (Alex)
Reviewed-by: Wayne Lin <Wayne.Lin@amd.com> Acked-by: Jasdeep Dhillon <jdhillon@amd.com> Signed-off-by: Alan Liu <HaoPing.Liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This causes problem for KFD because when we overcommit we accidentially
bind the BO to GTT for moving it into VRAM. We also need to make sure
that this is done only as fallback after trying to evict first.
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Luben Tuikov [Wed, 14 Dec 2022 08:56:03 +0000 (03:56 -0500)]
drm/amdgpu: Remove unnecessary domain argument
Remove the "domain" argument to amdgpu_bo_create_kernel_at() since this
function takes an "offset" argument which is the offset off of VRAM, and as
such allocation always takes place in VRAM. Thus, the "domain" argument is
unnecessary.
Cc: Alex Deucher <Alexander.Deucher@amd.com> Cc: Christian König <christian.koenig@amd.com> Cc: AMD Graphics <amd-gfx@lists.freedesktop.org> Signed-off-by: Luben Tuikov <luben.tuikov@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Luben Tuikov [Sat, 10 Dec 2022 07:51:19 +0000 (02:51 -0500)]
drm/amdgpu: Fix size validation for non-exclusive domains (v4)
Fix amdgpu_bo_validate_size() to check whether the TTM domain manager for the
requested memory exists, else we get a kernel oops when dereferencing "man".
v2: Make the patch standalone, i.e. not dependent on local patches.
v3: Preserve old behaviour and just check that the manager pointer is not
NULL.
v4: Complain if GTT domain requested and it is uninitialized--most likely a
bug.
Cc: Alex Deucher <Alexander.Deucher@amd.com> Cc: Christian König <christian.koenig@amd.com> Cc: AMD Graphics <amd-gfx@lists.freedesktop.org> Signed-off-by: Luben Tuikov <luben.tuikov@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Luben Tuikov [Mon, 12 Dec 2022 17:04:42 +0000 (12:04 -0500)]
drm/amdgpu: Check if fru_addr is not NULL (v2)
Always check if fru_addr is not NULL. This commit also fixes a "smatch"
warning.
v2: Add a Fixes tag.
Cc: Alex Deucher <Alexander.Deucher@amd.com> Cc: Dan Carpenter <error27@gmail.com> Cc: kernel test robot <lkp@intel.com> Cc: AMD Graphics <amd-gfx@lists.freedesktop.org> Fixes: afbe5d1e4bd7c7 ("drm/amdgpu: Bug-fix: Reading I2C FRU data on newer ASICs") Signed-off-by: Luben Tuikov <luben.tuikov@amd.com> Reviewed-by: Kent Russell <kent.russell@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Fri, 25 Nov 2022 16:04:25 +0000 (17:04 +0100)]
drm/amdgpu: rework reserved VMID handling
Instead of reserving a VMID for a single process allow that many
processes use the reserved ID. This allows for proper isolation
between the processes.
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Fri, 25 Nov 2022 15:45:09 +0000 (16:45 +0100)]
drm/amdgpu: stop waiting for the VM during unreserve
This is completely pointless since the VMID always stays allocated until
the VM is idle.
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Fri, 25 Nov 2022 15:42:45 +0000 (16:42 +0100)]
drm/amdgpu: cleanup SPM support a bit
This should probably not access job->vm and also emit the SPM switch
under the conditional execute.
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Fri, 25 Nov 2022 15:04:25 +0000 (16:04 +0100)]
drm/amdgpu: fix GDS/GWS/OA switch handling
Bas pointed out that this isn't working as expected and could cause
crashes. Fix the handling by storing the marker that a switch is needed
inside the job instead.
Reported-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Felix Kuehling [Thu, 22 Apr 2021 01:09:54 +0000 (21:09 -0400)]
drm/amdgpu: Add notifier lock for KFD userptrs
Add a per-process MMU notifier lock for processing notifiers from
userptrs. Use that lock to properly synchronize page table updates with
MMU notifiers.
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Xiaogang Chen<Xiaogang.Chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Wed, 16 Nov 2022 14:45:36 +0000 (15:45 +0100)]
drm/amdgpu: WARN when freeing kernel memory during suspend
When buffers are freed during suspend there is no guarantee that
they can be re-allocated during resume.
The PSP subsystem seems to be quite buggy regarding this, so add
a WARN_ON() to point out those bugs.
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexdeucher@amd.com> Tested-by: Guilherme G. Piccoli <gpiccoli@igalia.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Wed, 7 Dec 2022 07:47:30 +0000 (08:47 +0100)]
drm/amdgpu: fixx NULL pointer deref in gmc_v9_0_get_vm_pte
We not only need to make sure that we have a BO, but also that the BO
has some backing store.
Fixes: d1a372af1c3d ("drm/amdgpu: Set MTYPE in PTE based on BO flags") Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Luben Tuikov <luben.tuikov@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Shikang Fan [Thu, 8 Dec 2022 11:53:14 +0000 (19:53 +0800)]
drm/amdgpu: Add an extra evict_resource call during device_suspend.
- evict_resource is taking too long causing sriov full access mode timeout.
So, add an extra evict_resource in the beginning as an early evict.
Signed-off-by: Shikang Fan <shikang.fan@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Wed, 7 Dec 2022 16:08:53 +0000 (11:08 -0500)]
drm/amdgpu: make display pinning more flexible (v2)
Only apply the static threshold for Stoney and Carrizo.
This hardware has certain requirements that don't allow
mixing of GTT and VRAM. Newer asics do not have these
requirements so we should be able to be more flexible
with where buffers end up.
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2270
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2291
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2255 Acked-by: Luben Tuikov <luben.tuikov@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
There is a spelling mistake in the struct field dram_clk_chanage. Fix it.
Signed-off-by: Colin Ian King <colin.i.king@gmail.com> Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yang Wang [Mon, 5 Dec 2022 13:16:26 +0000 (21:16 +0800)]
drm/amdgpu: fix mmhub register base coding error
fix MMHUB register base coding error.
Fixes: ec6837591f992 ("drm/amdgpu/gmc10: program the smallK fragment size") Signed-off-by: Yang Wang <KevinYang.Wang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
Tim Huang [Mon, 5 Dec 2022 06:33:25 +0000 (14:33 +0800)]
drm/amdgpu: add tmz support for GC IP v11.0.4
Add tmz support for GC 11.0.4.
Signed-off-by: Tim Huang <tim.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tim Huang [Mon, 5 Dec 2022 06:18:23 +0000 (14:18 +0800)]
drm/amdgpu: enable GFX Clock Gating control for GC IP v11.0.4
Enable GFX IP v11.0.4 CG gate/ungate control.
Signed-off-by: Tim Huang <tim.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tim Huang [Mon, 5 Dec 2022 05:55:36 +0000 (13:55 +0800)]
drm/amdgpu: enable GFX Power Gating for GC IP v11.0.4
Enable GFX Power Gating control for GC IP v11.0.4.
Signed-off-by: Tim Huang <tim.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tim Huang [Mon, 5 Dec 2022 03:24:37 +0000 (11:24 +0800)]
drm/amdgpu: enable GFX IP v11.0.4 CG support
Add CG support for GFX/MC/HDP/ATHUB/IH/BIF.
Signed-off-by: Tim Huang <tim.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jiadong Zhu [Mon, 5 Dec 2022 01:55:32 +0000 (09:55 +0800)]
drm/amdgpu: Make amdgpu_ring_mux functions as static
lkp robot reported missing-prototypes and unused-but-set-variable warnings on
some functions of amdgpu_mcbp_mux.c. Make them static and remove the unused
variable.
Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Jiadong Zhu <Jiadong.Zhu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Thu, 24 Nov 2022 07:26:40 +0000 (08:26 +0100)]
drm/amdgpu: generally allow over-commit during BO allocation
We already fallback to a dummy BO with no backing store when we
allocate GDS,GWS and OA resources and to GTT when we allocate VRAM.
Drop all those workarounds and generalize this for GTT as well. This
fixes ENOMEM issues with runaway applications which try to allocate/free
GTT in a loop and are otherwise only limited by the CPU speed.
The CS will wait for the cleanup of freed up BOs to satisfy the
various domain specific limits and so effectively throttle those
buggy applications down to a sane allocation behavior again.
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Arunpravin Paneer Selvam <Arunpravin.PaneerSelvam@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aurabindo Pillai [Sat, 26 Nov 2022 00:13:41 +0000 (19:13 -0500)]
drm/amd/display: fix array index out of bound error in DCN32 DML
[Why&How]
LinkCapacitySupport array is indexed with the number of voltage states and
not the number of max DPPs. Fix the error by changing the array
declaration to use the correct (larger) array size of total number of
voltage states.
drm/amd/display: Add debug option to skip PSR CRTC disable
[Why]
It's currently tied to Z10 support, and is required for Z10, but
we can still support Z10 display off without PSR.
We currently need to skip the PSR CRTC disable to prevent stuttering
and underflow from occuring during PSR-SU.
[How]
Add a debug option to allow specifying this separately.
Reviewed-by: Robin Chen <robin.chen@amd.com> Acked-by: Stylon Wang <stylon.wang@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Zhongwei [Tue, 22 Nov 2022 06:28:41 +0000 (14:28 +0800)]
drm/amd/display: correct DML calc error of UrgentLatency
[Why]
The input UrgentLatency in CalculateUrgentBurstFactor
of prefect check is wrong.
[How]
Correct to the correct one to keep same as HW formula
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Stylon Wang <stylon.wang@amd.com> Signed-off-by: Zhongwei <Zhongwei.Zhang@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Charlene Liu [Fri, 25 Nov 2022 05:38:17 +0000 (00:38 -0500)]
drm/amd/display: correct static_screen_event_mask
[why]
HW register bit define changed.
Reviewed-by: Zhan Liu <Zhan.Liu@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Stylon Wang <stylon.wang@amd.com> Signed-off-by: Charlene Liu <Charlene.Liu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alvin Lee [Fri, 25 Nov 2022 03:36:26 +0000 (22:36 -0500)]
drm/amd/display: Ensure commit_streams returns the DC return code
[Description]
- Ensure dc_commit_streams returns the correct return code so any
failures can be handled properly in DM layer
- If set timings fail and we have to remove MPO planes, do so
unconditionally but make sure to mark for removal so we report
the VSYNC and prevent timeout
- Failure to remove MPO plane results in set timings failure due
to lack of resources
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Stylon Wang <stylon.wang@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Paul Hsieh [Thu, 24 Nov 2022 05:03:26 +0000 (13:03 +0800)]
drm/amd/display: read invalid ddc pin status cause engine busy
[Why]
There is no DDC_6 pin on new asic cause the mapping table is
incorrect. When app try to access DDC_VGA port, driver read
an invalid ddc pin status and report engine busy.
[How]
Add dummy DDC_6 pin to align gpio structure.
Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com> Acked-by: Stylon Wang <stylon.wang@amd.com> Signed-off-by: Paul Hsieh <Paul.Hsieh@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dillon Varone [Wed, 23 Nov 2022 19:15:00 +0000 (14:15 -0500)]
drm/amd/display: Bypass DET swath fill check for max clocks
[Description]
If validating for max voltage level (therefore max clocks) always pass over
the DET swath fill latency hiding check.
Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com> Acked-by: Stylon Wang <stylon.wang@amd.com> Signed-off-by: Dillon Varone <Dillon.Varone@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dillon Varone [Wed, 23 Nov 2022 15:44:16 +0000 (10:44 -0500)]
drm/amd/display: Disable uclk pstate for subvp pipes
[Description]
When subvp is in use, main pipes should block unintended natural uclk pstate
changes to prevent disruption to the state machine.
Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com> Acked-by: Stylon Wang <stylon.wang@amd.com> Signed-off-by: Dillon Varone <Dillon.Varone@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Michael Strauss [Thu, 17 Nov 2022 15:40:46 +0000 (10:40 -0500)]
drm/amd/display: Fix DCN2.1 default DSC clocks
[WHY]
Low dscclk in high vlevels blocks some DSC modes.
[HOW]
Update dscclk to 1/3 of dispclk.
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Stylon Wang <stylon.wang@amd.com> Signed-off-by: Michael Strauss <michael.strauss@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
David Galiffi [Fri, 18 Nov 2022 22:35:22 +0000 (17:35 -0500)]
drm/amd/display: Enable dp_hdmi21_pcon support
[Why]
It is not enabled for DCN3.0.1, 3.0.2, 3.0.3.
[How]
Add `dc->caps.dp_hdmi21_pcon_support = true` to these DCN versions.
Reviewed-by: Martin Leung <Martin.Leung@amd.com> Acked-by: Stylon Wang <stylon.wang@amd.com> Signed-off-by: David Galiffi <David.Galiffi@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: prevent seamless boot on displays that don't have the preferred dig
Seamless boot requires VBIOS to select dig matching to link order wise. A significant
amount of dal logic makes assumption we are using preferred dig for eDP and if this
isn't the case then seamless boot is not supported.
Reviewed-by: Martin Leung <Martin.Leung@amd.com> Acked-by: Stylon Wang <stylon.wang@amd.com> Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aurabindo Pillai [Mon, 21 Nov 2022 20:48:23 +0000 (15:48 -0500)]
drm/amd/display: trigger timing sync only if TG is running
[Why&How]
If the timing generator isnt running, it does not make sense to trigger
a sync on the corresponding OTG. Check this condition before starting.
Otherwise, this will cause error like:
*ERROR* GSL: Timeout on reset trigger!
Fixes: dc55b106ad477c ("drm/amd/display: Disable phantom OTG after enable for plane disable") Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com> Acked-by: Stylon Wang <stylon.wang@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chris Park [Thu, 5 May 2022 05:55:52 +0000 (01:55 -0400)]
drm/amd/display: Remove DTB DTO on CLK update
[Why]
DTB DTO is programmed more correctly during
link enable. Programming them on CLK update
which may arrive frequently and sporadically
per flip throws off DTB DTO.
[How]
Remove DTB DTO programming on clock update.
Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com> Acked-by: Jasdeep Dhillon <jdhillon@amd.com> Signed-off-by: Chris Park <Chris.Park@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 1 Dec 2022 21:41:52 +0000 (16:41 -0500)]
drm/amdgpu: add GART, GPUVM, and GTT to glossary
Add definitions to clarify GPU virtual memory.
v2: clarify the terms a bit more
Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Luben Tuikov <luben.tuikov@amd.com> Suggested-by: Peter Maucher <bellosilicio@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Link: https://lore.kernel.org/r/20221201214153.8453-1-alexander.deucher@amd.com
Prike Liang [Thu, 1 Dec 2022 03:17:31 +0000 (11:17 +0800)]
drm/amdgpu/sdma_v4_0: turn off SDMA ring buffer in the s2idle suspend
In the SDMA s0ix save process requires to turn off SDMA ring buffer for
avoiding the SDMA in-flight request, otherwise will suffer from SDMA page
fault which causes by page request from in-flight SDMA ring accessing at
SDMA restore phase.
Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2248 Cc: stable@vger.kernel.org # 6.0,5.15+ Fixes: f8f4e2a51834 ("drm/amdgpu: skipping SDMA hw_init and hw_fini for S0ix.") Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Tested-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Trigger Mid-Command Buffer Preemption according to the priority of the software
rings and the hw fence signalling condition.
The muxer saves the locations of the indirect buffer frames from the software
ring together with the fence sequence number in its fifo queue, and pops out
those records when the fences are signalled. The locations are used to resubmit
packages in preemption scenarios by coping the chunks from the software ring.
v2: Update comment style.
v3: Fix conflict caused by previous modifications.
v4: Remove unnecessary prints.
v5: Fix corner cases for resubmission cases.
v6: Refactor functions for resubmission, calling fence_process in irq handler.
v7: Solve conflict for removing amdgpu_sw_ring.c.
v8: Add time threshold to judge if preemption request is needed.
v9: Correct comment spelling. Set fence emit timestamp before rsu assignment.
Cc: Christian Koenig <Christian.Koenig@amd.com> Cc: Luben Tuikov <Luben.Tuikov@amd.com> Cc: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com> Cc: Michel Dänzer <michel@daenzer.net> Signed-off-by: Jiadong.Zhu <Jiadong.Zhu@amd.com> Acked-by: Luben Tuikov <luben.tuikov@amd.com> Acked-by: Huang Rui <ray.huang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Modify unmap_queue format for gfx9 (v6)
1. Modify the unmap_queue package on gfx9. Add trailing fence to track the
preemption done.
2. Modify emit_ce_meta emit_de_meta functions for the resumed ibs.
v2: Restyle code not to use ternary operator.
v3: Modify code format.
v4: Enable Mid-Command Buffer Preemption for gfx9 by default.
v5: Optimize the flag bit set for emit_fence.
v6: Modify log message for preemption timeout.
Cc: Christian Koenig <Christian.Koenig@amd.com> Cc: Michel Dänzer <michel@daenzer.net> Cc: Luben Tuikov <Luben.Tuikov@amd.com> Signed-off-by: Jiadong.Zhu <Jiadong.Zhu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Add software ring callbacks for gfx9 (v8)
Set ring functions with software ring callbacks on gfx9.
The software ring could be tested by debugfs_test_ib case.
v2: Set sw_ring 2 to enable software ring by default.
v3: Remove the parameter for software ring enablement.
v4: Use amdgpu_ring_init/fini for software rings.
v5: Update for code format. Fix conflict.
v6: Remove unnecessary checks and enable software ring on gfx9 by default.
v7: Use static array for software ring names and priorities.
v8: Stop creating software rings if no gfx ring existed.
Cc: Christian Koenig <Christian.Koenig@amd.com> Cc: Luben Tuikov <Luben.Tuikov@amd.com> Cc: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com> Cc: Michel Dänzer <michel@daenzer.net> Cc: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Jiadong.Zhu <Jiadong.Zhu@amd.com> Acked-by: Luben Tuikov <luben.tuikov@amd.com> Acked-by: Huang Rui <ray.huang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
The software ring is created to support priority context while there is only
one hardware queue for gfx.
Every software ring has its fence driver and could be used as an ordinary ring
for the GPU scheduler.
Multiple software rings are bound to a real ring with the ring muxer. The
packages committed on the software ring are copied to the real ring.
v2: Use array to store software ring entry.
v3: Remove unnecessary prints.
v4: Remove amdgpu_ring_sw_init/fini functions,
using gtt for sw ring buffer for later dma copy
optimization.
v5: Allocate ring entry dynamically in the muxer.
v6: Update comments for the ring muxer.
v7: Modify for function naming.
v8: Combine software ring functions into amdgpu_ring_mux.c
v9: Use kernel-doc comment on the get_rptr function.
Cc: Christian Koenig <Christian.Koenig@amd.com> Cc: Luben Tuikov <Luben.Tuikov@amd.com> Cc: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com> Cc: Michel Dänzer <michel@daenzer.net> Signed-off-by: Jiadong.Zhu <Jiadong.Zhu@amd.com> Acked-by: Huang Rui <ray.huang@amd.com> Acked-by: Luben Tuikov <luben.tuikov@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hamza Mahfooz [Tue, 15 Nov 2022 16:58:45 +0000 (11:58 -0500)]
drm/amd/display: add FB_DAMAGE_CLIPS support
Currently, userspace doesn't have a way to communicate selective updates
to displays. So, enable support for FB_DAMAGE_CLIPS for DCN ASICs newer
than DCN301, convert DRM damage clips to dc dirty rectangles and fill
them into dirty_rects in fill_dc_dirty_rects().
Reviewed-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Peter Maucher [Thu, 1 Dec 2022 15:38:20 +0000 (16:38 +0100)]
drm/amdgpu: improve GART and GTT documentation
Document difference between amdgpu.gartsize and amdgpu.gttsize
module parameters, as initially explained by Alex Deucher here:
https://lists.freedesktop.org/archives/dri-devel/2022-October/375358.html
v2: minor cleanups (Alex)
Signed-off-by: Peter Maucher <bellosilicio@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Mon, 28 Nov 2022 15:38:53 +0000 (10:38 -0500)]
drm/amd/display: use the proper fb offset for DM
This fixes DMCU initialization in APU GPU passthrough. The
DMCU needs the GPU physical address, not the CPU physical
address. This ends up working out on bare metal because
we always use the physical address, but doesn't work in
passthrough because the addresses are different.
Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Liu [Tue, 29 Nov 2022 23:53:18 +0000 (18:53 -0500)]
drm/amdgpu: enable Vangogh VCN indirect sram mode
So that uses PSP to initialize HW.
Fixes: 0c2c02b66c672e ("drm/amdgpu/vcn: add firmware support for dimgrey_cavefish") Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
The fence is only tracking if the HuC load is in progress or not and
doesn't distinguish between already loaded, not supported or disabled,
so we can always initialize it to completed, no matter the actual
support. We already do that for most platforms, but we skip it on
GTs that lack VCS engines (e.g. MTL root GT), so fix that. Note that the
cleanup is already unconditional.
While at it, move the init/fini to helper functions.