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12 months agoMerge tag 'pull-tcg-20230525' of https://gitlab.com/rth7680/qemu into staging
Richard Henderson [Thu, 25 May 2023 18:11:52 +0000 (11:11 -0700)]
Merge tag 'pull-tcg-20230525' of https://gitlab.com/rth7680/qemu into staging

tcg/mips:
  - Constant formation improvements
  - Replace MIPS_BE with HOST_BIG_ENDIAN
  - General cleanups
tcg/riscv:
  - Improve setcond
  - Support movcond
  - Support Zbb, Zba

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# gpg:                using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg:                issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate]

* tag 'pull-tcg-20230525' of https://gitlab.com/rth7680/qemu: (23 commits)
  tcg/riscv: Support CTZ, CLZ from Zbb
  tcg/riscv: Implement movcond
  tcg/riscv: Improve setcond expansion
  tcg/riscv: Support CPOP from Zbb
  tcg/riscv: Support REV8 from Zbb
  tcg/riscv: Support rotates from Zbb
  tcg/riscv: Use ADD.UW for guest address generation
  tcg/riscv: Support ADD.UW, SEXT.B, SEXT.H, ZEXT.H from Zba+Zbb
  tcg/riscv: Support ANDN, ORN, XNOR from Zbb
  tcg/riscv: Probe for Zba, Zbb, Zicond extensions
  disas/riscv: Decode czero.{eqz,nez}
  tcg/mips: Replace MIPS_BE with HOST_BIG_ENDIAN
  tcg/mips: Use qemu_build_not_reached for LO/HI_OFF
  tcg/mips: Try three insns with shift and add in tcg_out_movi
  tcg/mips: Try tb-relative addresses in tcg_out_movi
  tcg/mips: Aggressively use the constant pool for n64 calls
  tcg/mips: Use the constant pool for 64-bit constants
  tcg/mips: Split out tcg_out_movi_two
  tcg/mips: Split out tcg_out_movi_one
  tcg/mips: Create and use TCG_REG_TB
  ...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agoMerge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
Richard Henderson [Thu, 25 May 2023 15:36:10 +0000 (08:36 -0700)]
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging

* hot-unplug fixes for ioport
* purge qatomic_mb_read/set from monitor
* build system fixes
* OHCI fix from gitlab
* provide EPYC-Rome CPU model not susceptible to XSAVES erratum

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# gpg: Signature made Thu 25 May 2023 01:21:37 AM PDT
# gpg:                using RSA key F13338574B662389866C7682BFFBD25F78C7AE83
# gpg:                issuer "pbonzini@redhat.com"
# gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [undefined]
# gpg:                 aka "Paolo Bonzini <pbonzini@redhat.com>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
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* tag 'for-upstream' of https://gitlab.com/bonzini/qemu:
  monitor: do not use mb_read/mb_set
  monitor: extract request dequeuing to a new function
  monitor: introduce qmp_dispatcher_co_wake
  monitor: cleanup fetching of QMP requests
  monitor: cleanup detection of qmp_dispatcher_co shutting down
  monitor: do not use mb_read/mb_set for suspend_cnt
  monitor: add more *_locked() functions
  monitor: allow calling monitor_resume under mon_lock
  monitor: use QEMU_LOCK_GUARD a bit more
  softmmu/ioport.c: make MemoryRegionPortioList owner of portio_list MemoryRegions
  softmmu/ioport.c: QOMify MemoryRegionPortioList
  softmmu/ioport.c: allocate MemoryRegionPortioList ports on the heap
  usb/ohci: Set pad to 0 after frame update
  meson: move -no-pie from linker to compiler
  meson: fix rule for qemu-ga installer
  meson.build: Fix glib -Wno-unused-function workaround
  target/i386: EPYC-Rome model without XSAVES

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agotcg/riscv: Support CTZ, CLZ from Zbb
Richard Henderson [Wed, 26 Apr 2023 13:21:55 +0000 (14:21 +0100)]
tcg/riscv: Support CTZ, CLZ from Zbb

Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agotcg/riscv: Implement movcond
Richard Henderson [Wed, 26 Apr 2023 10:59:55 +0000 (11:59 +0100)]
tcg/riscv: Implement movcond

Implement with and without Zicond.  Without Zicond, we were letting
the middle-end expand to a 5 insn sequence; better to use a branch
over a single insn.

Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agotcg/riscv: Improve setcond expansion
Richard Henderson [Wed, 26 Apr 2023 08:38:32 +0000 (09:38 +0100)]
tcg/riscv: Improve setcond expansion

Split out a helper function, tcg_out_setcond_int, which does not
always produce the complete boolean result, but returns a set of
flags to do so.

Based on 21af16198425, the same improvement for loongarch64.

Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agotcg/riscv: Support CPOP from Zbb
Richard Henderson [Wed, 26 Apr 2023 08:16:11 +0000 (09:16 +0100)]
tcg/riscv: Support CPOP from Zbb

Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agotcg/riscv: Support REV8 from Zbb
Richard Henderson [Tue, 25 Apr 2023 16:04:53 +0000 (17:04 +0100)]
tcg/riscv: Support REV8 from Zbb

Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agotcg/riscv: Support rotates from Zbb
Richard Henderson [Tue, 25 Apr 2023 15:34:07 +0000 (16:34 +0100)]
tcg/riscv: Support rotates from Zbb

Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agotcg/riscv: Use ADD.UW for guest address generation
Richard Henderson [Tue, 25 Apr 2023 15:19:44 +0000 (16:19 +0100)]
tcg/riscv: Use ADD.UW for guest address generation

The instruction is a combined zero-extend and add.
Use it for exactly that.

Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agotcg/riscv: Support ADD.UW, SEXT.B, SEXT.H, ZEXT.H from Zba+Zbb
Richard Henderson [Tue, 25 Apr 2023 15:04:16 +0000 (16:04 +0100)]
tcg/riscv: Support ADD.UW, SEXT.B, SEXT.H, ZEXT.H from Zba+Zbb

Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agotcg/riscv: Support ANDN, ORN, XNOR from Zbb
Richard Henderson [Tue, 25 Apr 2023 14:47:34 +0000 (15:47 +0100)]
tcg/riscv: Support ANDN, ORN, XNOR from Zbb

Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agotcg/riscv: Probe for Zba, Zbb, Zicond extensions
Richard Henderson [Tue, 25 Apr 2023 14:29:03 +0000 (15:29 +0100)]
tcg/riscv: Probe for Zba, Zbb, Zicond extensions

Define a useful subset of the extensions.  Probe for them
via compiler pre-processor feature macros and SIGILL.

Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agodisas/riscv: Decode czero.{eqz,nez}
Richard Henderson [Wed, 26 Apr 2023 12:33:05 +0000 (13:33 +0100)]
disas/riscv: Decode czero.{eqz,nez}

Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agotcg/mips: Replace MIPS_BE with HOST_BIG_ENDIAN
Richard Henderson [Wed, 17 May 2023 13:56:44 +0000 (06:56 -0700)]
tcg/mips: Replace MIPS_BE with HOST_BIG_ENDIAN

Since e03b56863d2b, which replaced HOST_WORDS_BIGENDIAN
with HOST_BIG_ENDIAN, there is no need to define a second
symbol which is [0,1].

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agotcg/mips: Use qemu_build_not_reached for LO/HI_OFF
Richard Henderson [Mon, 28 Nov 2022 20:31:56 +0000 (12:31 -0800)]
tcg/mips: Use qemu_build_not_reached for LO/HI_OFF

The new(ish) macro produces a compile-time error instead
of a link-time error.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agotcg/mips: Try three insns with shift and add in tcg_out_movi
Richard Henderson [Fri, 6 Aug 2021 21:18:25 +0000 (11:18 -1000)]
tcg/mips: Try three insns with shift and add in tcg_out_movi

These sequences are inexpensive to test.  Maxing out at three insns
results in the same space as a load plus the constant pool entry.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agotcg/mips: Try tb-relative addresses in tcg_out_movi
Richard Henderson [Fri, 6 Aug 2021 21:30:35 +0000 (11:30 -1000)]
tcg/mips: Try tb-relative addresses in tcg_out_movi

These addresses are often loaded by the qemu_ld/st slow path,
for loading the retaddr value.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agotcg/mips: Aggressively use the constant pool for n64 calls
Richard Henderson [Fri, 6 Aug 2021 23:17:20 +0000 (13:17 -1000)]
tcg/mips: Aggressively use the constant pool for n64 calls

Repeated calls to a single helper are common -- especially
the ones for softmmu memory access.  Prefer the constant pool
to longer sequences to increase sharing.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agotcg/mips: Use the constant pool for 64-bit constants
Richard Henderson [Fri, 6 Aug 2021 23:07:41 +0000 (13:07 -1000)]
tcg/mips: Use the constant pool for 64-bit constants

During normal processing, the constant pool is accessible via
TCG_REG_TB.  During the prologue, it is accessible via TCG_REG_T9.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agotcg/mips: Split out tcg_out_movi_two
Richard Henderson [Fri, 6 Aug 2021 22:14:53 +0000 (12:14 -1000)]
tcg/mips: Split out tcg_out_movi_two

Emit all 32-bit signed constants, which can be loaded in two insns.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agotcg/mips: Split out tcg_out_movi_one
Richard Henderson [Fri, 6 Aug 2021 22:02:59 +0000 (12:02 -1000)]
tcg/mips: Split out tcg_out_movi_one

Emit all constants that can be loaded in exactly one insn.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agotcg/mips: Create and use TCG_REG_TB
Richard Henderson [Fri, 6 Aug 2021 19:28:31 +0000 (09:28 -1000)]
tcg/mips: Create and use TCG_REG_TB

This vastly reduces the size of code generated for 64-bit addresses.
The code for exit_tb, for instance, where we load a (tagged) pointer
to the current TB, goes from

0x400aa9725c:  li       v0,64
0x400aa97260:  dsll     v0,v0,0x10
0x400aa97264:  ori      v0,v0,0xaa9
0x400aa97268:  dsll     v0,v0,0x10
0x400aa9726c:  j        0x400aa9703c
0x400aa97270:  ori      v0,v0,0x7083

to

0x400aa97240:  j        0x400aa97040
0x400aa97244:  daddiu   v0,s6,-189

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agotcg/mips: Unify TCG_GUEST_BASE_REG tests
Richard Henderson [Fri, 6 Aug 2021 17:13:46 +0000 (07:13 -1000)]
tcg/mips: Unify TCG_GUEST_BASE_REG tests

In tcg_out_qemu_ld/st, we already check for guest_base matching int16_t.
Mirror that when setting up TCG_GUEST_BASE_REG in the prologue.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agotcg/mips: Move TCG_GUEST_BASE_REG to S7
Richard Henderson [Fri, 6 Aug 2021 17:10:57 +0000 (07:10 -1000)]
tcg/mips: Move TCG_GUEST_BASE_REG to S7

No functional change; just moving the saved reserved regs to the end.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agotcg/mips: Move TCG_AREG0 to S8
Richard Henderson [Fri, 6 Aug 2021 17:08:54 +0000 (07:08 -1000)]
tcg/mips: Move TCG_AREG0 to S8

No functional change; just moving the saved reserved regs to the end.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agomonitor: do not use mb_read/mb_set
Paolo Bonzini [Wed, 15 Mar 2023 11:34:01 +0000 (12:34 +0100)]
monitor: do not use mb_read/mb_set

Instead of relying on magic memory barriers, document the pattern that
is being used.  It is the one based on Dekker's algorithm, and in this
case it is embodied as follows:

    enqueue request;              sleeping = true;
    smp_mb();                     smp_mb();
    if (sleeping) kick();         if (!have a request) yield();

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
12 months agomonitor: extract request dequeuing to a new function
Paolo Bonzini [Fri, 3 Mar 2023 12:51:58 +0000 (13:51 +0100)]
monitor: extract request dequeuing to a new function

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
12 months agomonitor: introduce qmp_dispatcher_co_wake
Paolo Bonzini [Fri, 3 Mar 2023 12:51:44 +0000 (13:51 +0100)]
monitor: introduce qmp_dispatcher_co_wake

This makes it possible to turn qmp_dispatcher_co_busy into a static
variable.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
12 months agomonitor: cleanup fetching of QMP requests
Paolo Bonzini [Fri, 3 Mar 2023 11:51:33 +0000 (12:51 +0100)]
monitor: cleanup fetching of QMP requests

Use a continue statement so that "after going to sleep" is treated the same
way as "after processing a request".  Pull the monitor_lock critical
section out of monitor_qmp_requests_pop_any_with_lock() and protect
qmp_dispatcher_co_shutdown with the monitor_lock.

The two changes are complex to separate because monitor_qmp_dispatcher_co()
previously had a complicated logic to check for shutdown both before
and after going to sleep.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
12 months agomonitor: cleanup detection of qmp_dispatcher_co shutting down
Paolo Bonzini [Fri, 3 Mar 2023 11:45:29 +0000 (12:45 +0100)]
monitor: cleanup detection of qmp_dispatcher_co shutting down

Instead of overloading qmp_dispatcher_co_busy, make the coroutine
pointer NULL.  This will make things break spectacularly if somebody
tries to start a request after monitor_cleanup().

AIO_WAIT_WHILE_UNLOCKED() does not need qatomic_mb_read(), because
the macro contains all the necessary memory barriers.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
12 months agomonitor: do not use mb_read/mb_set for suspend_cnt
Paolo Bonzini [Fri, 3 Mar 2023 12:32:13 +0000 (13:32 +0100)]
monitor: do not use mb_read/mb_set for suspend_cnt

Clean up monitor_event to just use monitor_suspend/monitor_resume,
using mon->mux_out to protect against incorrect nesting (especially
on startup).

The only remaining case of reading suspend_cnt is in the can_read
callback, which is just advisory and can use qatomic_read.

As an extra benefit, mux_out is now simply protected by mon_lock.
Also, moving the prompt to the beginning of the main loop removes
it from the output in some error cases where QEMU does not actually
start successfully.  It is not a full fix and it would be nice to
also remove the monitor heading, but this is already a small (though
unintentional) improvement.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
12 months agomonitor: add more *_locked() functions
Paolo Bonzini [Wed, 17 May 2023 12:46:49 +0000 (14:46 +0200)]
monitor: add more *_locked() functions

Allow flushing and printing to the monitor while mon->mon_lock is
held.  This will help cleaning up the locking of mon->mux_out and
mon->suspend_cnt.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
12 months agomonitor: allow calling monitor_resume under mon_lock
Paolo Bonzini [Wed, 17 May 2023 15:19:03 +0000 (17:19 +0200)]
monitor: allow calling monitor_resume under mon_lock

Move monitor_resume()'s call to readline_show_prompt() outside the
potentially locked section.  Reuse the existing monitor_accept_input()
bottom half for this purpose.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
12 months agomonitor: use QEMU_LOCK_GUARD a bit more
Paolo Bonzini [Wed, 17 May 2023 12:47:55 +0000 (14:47 +0200)]
monitor: use QEMU_LOCK_GUARD a bit more

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
12 months agosoftmmu/ioport.c: make MemoryRegionPortioList owner of portio_list MemoryRegions
Mark Cave-Ayland [Wed, 19 Apr 2023 15:16:52 +0000 (16:16 +0100)]
softmmu/ioport.c: make MemoryRegionPortioList owner of portio_list MemoryRegions

Currently when portio_list MemoryRegions are freed using portio_list_destroy() the RCU
thread segfaults generating a backtrace similar to that below:

    #0 0x5555599a34b6 in phys_section_destroy ../softmmu/physmem.c:996
    #1 0x5555599a37a3 in phys_sections_free ../softmmu/physmem.c:1011
    #2 0x5555599b24aa in address_space_dispatch_free ../softmmu/physmem.c:2430
    #3 0x55555996a283 in flatview_destroy ../softmmu/memory.c:292
    #4 0x55555a2cb9fb in call_rcu_thread ../util/rcu.c:284
    #5 0x55555a29b71d in qemu_thread_start ../util/qemu-thread-posix.c:541
    #6 0x7ffff4a0cea6 in start_thread nptl/pthread_create.c:477
    #7 0x7ffff492ca2e in __clone (/lib/x86_64-linux-gnu/libc.so.6+0xfca2e)

The problem here is that portio_list_destroy() unparents the portio_list
MemoryRegions causing them to be freed immediately, however the flatview
still has a reference to the MemoryRegion and so causes a use-after-free
segfault when the RCU thread next updates the flatview.

Solve the lifetime issue by making MemoryRegionPortioList the owner of the
portio_list MemoryRegions, and then reparenting them to the portio_list
owner. This ensures that they can be accessed as QOM children via the
portio_list owner, yet the MemoryRegionPortioList owns the refcount.

Update portio_list_destroy() to unparent the MemoryRegion from the
portio_list owner (while keeping mrpio->mr live until finalization of the
MemoryRegionPortioList), so that the portio_list MemoryRegions remain
allocated until flatview_destroy() removes the final refcount upon the
next flatview update.

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20230419151652.362717-4-mark.cave-ayland@ilande.co.uk>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
12 months agosoftmmu/ioport.c: QOMify MemoryRegionPortioList
Mark Cave-Ayland [Wed, 19 Apr 2023 15:16:51 +0000 (16:16 +0100)]
softmmu/ioport.c: QOMify MemoryRegionPortioList

The aim of QOMification is so that the lifetime of the MemoryRegionPortioList
structure can be managed using QOM's in-built refcounting instead of having to
handle this manually.

Due to the use of an opaque pointer it isn't possible to model the new
TYPE_MEMORY_REGION_PORTIO_LIST directly using QOM properties, however since
use of the new object is restricted to the portio API we can simply set the
opaque pointer (and the heap-allocated port list) internally.

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20230419151652.362717-3-mark.cave-ayland@ilande.co.uk>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
12 months agosoftmmu/ioport.c: allocate MemoryRegionPortioList ports on the heap
Mark Cave-Ayland [Wed, 19 Apr 2023 15:16:50 +0000 (16:16 +0100)]
softmmu/ioport.c: allocate MemoryRegionPortioList ports on the heap

In order to facilitate a conversion of MemoryRegionPortioList to a QOM object
move the allocation of MemoryRegionPortioList ports to the heap instead of
using a variable-length member at the end of the MemoryRegionPortioList
structure.

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20230419151652.362717-2-mark.cave-ayland@ilande.co.uk>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
12 months agousb/ohci: Set pad to 0 after frame update
Paolo Bonzini [Tue, 23 May 2023 15:58:40 +0000 (17:58 +0200)]
usb/ohci: Set pad to 0 after frame update

When the OHCI controller's framenumber is incremented, HccaPad1 register
should be set to zero (Ref OHCI Spec 4.4)

ReactOS uses hccaPad1 to determine if the OHCI hardware is running,
consequently it fails this check in current qemu master.

Signed-off-by: Ryan Wendland <wendland@live.com.au>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1048
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
12 months agomeson: move -no-pie from linker to compiler
Paolo Bonzini [Mon, 22 May 2023 08:05:33 +0000 (10:05 +0200)]
meson: move -no-pie from linker to compiler

The large comment in the patch says it all; the -no-pie flag is broken and
this is why it was not included in QEMU_LDFLAGS before commit a988b4c5614
("build: move remaining compiler flag tests to meson", 2023-05-18).  And
some distros made things even worse, so we have to add it to the compiler
command line.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1664
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
12 months agomeson: fix rule for qemu-ga installer
Paolo Bonzini [Mon, 22 May 2023 07:19:03 +0000 (09:19 +0200)]
meson: fix rule for qemu-ga installer

The bindir variable is not available in the "glib" variable, which is an internal
dependency (created with "declare_dependency").  Use glib_pc instead, which contains
the variable as it is instantiated from glib-2.0.pc.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
12 months agomeson.build: Fix glib -Wno-unused-function workaround
Nicolas Saenz Julienne [Wed, 24 May 2023 17:31:23 +0000 (17:31 +0000)]
meson.build: Fix glib -Wno-unused-function workaround

We want to only enable '-Wno-unused-function' if glib's version is
smaller than '2.57.2' and has a G_DEFINE_AUTOPTR_CLEANUP_FUNC()
implementation that doesn't take into account unused functions. But the
compilation test isn't working as intended as '-Wunused-function' isn't
enabled while running it.

Let's enable it.

Fixes: fc9a809e0d28 ("build: move glib detection and workarounds to meson")
Signed-off-by: Nicolas Saenz Julienne <nsaenz@amazon.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20230524173123.66483-1-nsaenz@amazon.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
12 months agotarget/i386: EPYC-Rome model without XSAVES
Maksim Davydov [Wed, 24 May 2023 21:37:48 +0000 (00:37 +0300)]
target/i386: EPYC-Rome model without XSAVES

Based on the kernel commit "b0563468ee x86/CPU/AMD: Disable XSAVES on
AMD family 0x17", host system with EPYC-Rome can clear XSAVES capability
bit. In another words, EPYC-Rome host without XSAVES can occur. Thus, we
need an EPYC-Rome cpu model (without this feature) that matches the
solution of fixing this erratum

Signed-off-by: Maksim Davydov <davydov-max@yandex-team.ru>
Message-Id: <20230524213748.8918-1-davydov-max@yandex-team.ru>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
12 months agoMerge tag 'pull-vfio-20230524' of https://github.com/legoater/qemu into staging
Richard Henderson [Wed, 24 May 2023 21:23:41 +0000 (14:23 -0700)]
Merge tag 'pull-vfio-20230524' of https://github.com/legoater/qemu into staging

vfio queue:

* Fix for a memory corruption due to an extra free
* Fix for a compile breakage

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# gpg: Signature made Wed 24 May 2023 01:17:34 AM PDT
# gpg:                using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: A0F6 6548 F048 95EB FE6B  0B60 51A3 43C7 CFFB ECA1

* tag 'pull-vfio-20230524' of https://github.com/legoater/qemu:
  util/vfio-helpers: Use g_file_read_link()
  vfio/pci: Fix a use-after-free issue

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agoAdd Kubernetes runner configuration
Camilla Conte [Mon, 22 May 2023 17:41:54 +0000 (18:41 +0100)]
Add Kubernetes runner configuration

Custom values for the gitlab-runner Helm chart.
See https://wiki.qemu.org/Testing/CI/KubernetesRunners.

Signed-off-by: Camilla Conte <cconte@redhat.com>
Message-Id: <20230522174153.46801-6-cconte@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agoAdd CI variable RUNNER_TAG
Camilla Conte [Mon, 22 May 2023 17:41:53 +0000 (18:41 +0100)]
Add CI variable RUNNER_TAG

This allows to set a job tag dynamically.
We need this to be able to select the Kubernetes runner.
See https://wiki.qemu.org/Testing/CI/KubernetesRunners.

Signed-off-by: Camilla Conte <cconte@redhat.com>
Message-Id: <20230522174153.46801-5-cconte@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agoAdd loop over docker info
Camilla Conte [Mon, 22 May 2023 17:41:52 +0000 (18:41 +0100)]
Add loop over docker info

Wait for docker info to return successfuly to ensure that
the docker server (daemon) started.
This is needed for jobs running on Kubernetes.
See https://wiki.qemu.org/Testing/CI/KubernetesRunners.

Signed-off-by: Camilla Conte <cconte@redhat.com>
Message-Id: <20230522174153.46801-4-cconte@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agoUse docker "stable" tag
Camilla Conte [Mon, 22 May 2023 17:41:51 +0000 (18:41 +0100)]
Use docker "stable" tag

Use the same tag in all jobs.

Signed-off-by: Camilla Conte <cconte@redhat.com>
Message-Id: <20230522174153.46801-3-cconte@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agoRemove redundant CI variables
Camilla Conte [Mon, 22 May 2023 17:41:50 +0000 (18:41 +0100)]
Remove redundant CI variables

These are not needed when using gitlab.com shared runners.

Signed-off-by: Camilla Conte <cconte@redhat.com>
Message-Id: <20230522174153.46801-2-cconte@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agoutil/vfio-helpers: Use g_file_read_link()
Akihiko Odaki [Tue, 23 May 2023 02:39:12 +0000 (11:39 +0900)]
util/vfio-helpers: Use g_file_read_link()

When _FORTIFY_SOURCE=2, glibc version is 2.35, and GCC version is
12.1.0, the compiler complains as follows:

In file included from /usr/include/features.h:490,
                 from /usr/include/bits/libc-header-start.h:33,
                 from /usr/include/stdint.h:26,
                 from /usr/lib/gcc/aarch64-unknown-linux-gnu/12.1.0/include/stdint.h:9,
                 from /home/alarm/q/var/qemu/include/qemu/osdep.h:94,
                 from ../util/vfio-helpers.c:13:
In function 'readlink',
    inlined from 'sysfs_find_group_file' at ../util/vfio-helpers.c:116:9,
    inlined from 'qemu_vfio_init_pci' at ../util/vfio-helpers.c:326:18,
    inlined from 'qemu_vfio_open_pci' at ../util/vfio-helpers.c:517:9:
/usr/include/bits/unistd.h:119:10: error: argument 2 is null but the corresponding size argument 3 value is 4095 [-Werror=nonnull]
  119 |   return __glibc_fortify (readlink, __len, sizeof (char),
      |          ^~~~~~~~~~~~~~~

This error implies the allocated buffer can be NULL. Use
g_file_read_link(), which allocates buffer automatically to avoid the
error.

Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Cédric Le Goater <clg@redhat.com>
12 months agovfio/pci: Fix a use-after-free issue
Zhenzhong Duan [Wed, 17 May 2023 02:46:51 +0000 (10:46 +0800)]
vfio/pci: Fix a use-after-free issue

vbasedev->name is freed wrongly which leads to garbage VFIO trace log.
Fix it by allocating a dup of vbasedev->name and then free the dup.

Fixes: 2dca1b37a760 ("vfio/pci: add support for VF token")
Suggested-by: Alex Williamson <alex.williamson@redhat.com>
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Reviewed-by: Matthew Rosato <mjrosato@linux.ibm.com>
Acked-by: Alex Williamson <alex.williamson@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Cédric Le Goater <clg@redhat.com>
12 months agoMerge tag 'pull-tcg-20230523-3' of https://gitlab.com/rth7680/qemu into staging
Richard Henderson [Wed, 24 May 2023 01:57:46 +0000 (18:57 -0700)]
Merge tag 'pull-tcg-20230523-3' of https://gitlab.com/rth7680/qemu into staging

util: Host cpu detection for x86 and aa64
util: Use cpu detection for bufferiszero
migration: Use cpu detection for xbzrle
tcg: Replace and remove cpu_atomic_{ld,st}o*
host/include: Split qemu/atomic128.h
tcg: Remove DEBUG_DISAS
tcg: Remove USE_TCG_OPTIMIZATIONS

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* tag 'pull-tcg-20230523-3' of https://gitlab.com/rth7680/qemu: (28 commits)
  tcg: Remove USE_TCG_OPTIMIZATIONS
  tcg: Remove DEBUG_DISAS
  qemu/atomic128: Add runtime test for FEAT_LSE2
  qemu/atomic128: Improve cmpxchg fallback for atomic16_set
  tcg: Split out tcg/debug-assert.h
  accel/tcg: Correctly use atomic128.h in ldst_atomicity.c.inc
  qemu/atomic128: Split atomic16_read
  accel/tcg: Eliminate #if on HAVE_ATOMIC128 and HAVE_CMPXCHG128
  accel/tcg: Remove prot argument to atomic_mmu_lookup
  accel/tcg: Remove cpu_atomic_{ld,st}o_*_mmu
  target/s390x: Always use cpu_atomic_cmpxchgl_be_mmu in do_csst
  target/s390x: Use cpu_{ld,st}*_mmu in do_csst
  accel/tcg: Unify cpu_{ld,st}*_{be,le}_mmu
  target/s390x: Use tcg_gen_qemu_{ld,st}_i128 for LPQ, STPQ
  target/ppc: Use tcg_gen_qemu_{ld,st}_i128 for LQARX, LQ, STQ
  include/qemu: Move CONFIG_ATOMIC128_OPT handling to atomic128.h
  meson: Fix detect atomic128 support with optimization
  include/host: Split out atomic128-ldst.h
  include/host: Split out atomic128-cas.h
  util: Add cpuinfo-aarch64.c
  ...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agotcg: Remove USE_TCG_OPTIMIZATIONS
Richard Henderson [Sat, 1 Apr 2023 23:08:38 +0000 (16:08 -0700)]
tcg: Remove USE_TCG_OPTIMIZATIONS

This is always defined, and the optimization pass is
essential to producing reasonable code.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agotcg: Remove DEBUG_DISAS
Richard Henderson [Sat, 1 Apr 2023 23:06:47 +0000 (16:06 -0700)]
tcg: Remove DEBUG_DISAS

This had been set since the beginning, is never undefined,
and it would seem to be harmful to debugging to do so.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agoqemu/atomic128: Add runtime test for FEAT_LSE2
Richard Henderson [Sat, 20 May 2023 02:22:25 +0000 (19:22 -0700)]
qemu/atomic128: Add runtime test for FEAT_LSE2

With FEAT_LSE2, load and store of int128 is directly supported.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agoqemu/atomic128: Improve cmpxchg fallback for atomic16_set
Richard Henderson [Sat, 20 May 2023 03:53:16 +0000 (20:53 -0700)]
qemu/atomic128: Improve cmpxchg fallback for atomic16_set

Use __sync_bool_compare_and_swap_16 to control the loop,
rather than a separate comparison.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agotcg: Split out tcg/debug-assert.h
Richard Henderson [Tue, 28 Mar 2023 01:02:33 +0000 (18:02 -0700)]
tcg: Split out tcg/debug-assert.h

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agoaccel/tcg: Correctly use atomic128.h in ldst_atomicity.c.inc
Richard Henderson [Sat, 20 May 2023 01:32:44 +0000 (18:32 -0700)]
accel/tcg: Correctly use atomic128.h in ldst_atomicity.c.inc

Remove the locally defined load_atomic16 and store_atomic16,
along with HAVE_al16 and HAVE_al16_fast in favor of the
routines defined in atomic128.h.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agoqemu/atomic128: Split atomic16_read
Richard Henderson [Sat, 20 May 2023 01:30:28 +0000 (18:30 -0700)]
qemu/atomic128: Split atomic16_read

Create both atomic16_read_ro and atomic16_read_rw.
Previously we pretended that we had atomic16_read in system mode,
because we "know" that all ram is always writable to the host.
Now, expose read-only and read-write versions all of the time.

For aarch64, do not fall back to __atomic_read_16 even if
supported by the compiler, to work around a clang bug.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agoaccel/tcg: Eliminate #if on HAVE_ATOMIC128 and HAVE_CMPXCHG128
Richard Henderson [Sat, 20 May 2023 01:02:19 +0000 (18:02 -0700)]
accel/tcg: Eliminate #if on HAVE_ATOMIC128 and HAVE_CMPXCHG128

These symbols will shortly become dynamic runtime tests and
therefore not appropriate for the preprocessor.  Use the
matching CONFIG_* symbols for that purpose.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agoaccel/tcg: Remove prot argument to atomic_mmu_lookup
Richard Henderson [Sat, 20 May 2023 00:54:18 +0000 (17:54 -0700)]
accel/tcg: Remove prot argument to atomic_mmu_lookup

Now that load/store are gone, we're always passing
PAGE_READ | PAGE_WRITE for RMW atomic operations.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agoaccel/tcg: Remove cpu_atomic_{ld,st}o_*_mmu
Richard Henderson [Sat, 20 May 2023 00:45:47 +0000 (17:45 -0700)]
accel/tcg: Remove cpu_atomic_{ld,st}o_*_mmu

Atomic load/store of 128-byte quantities is now handled
by cpu_{ld,st}16_mmu.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agotarget/s390x: Always use cpu_atomic_cmpxchgl_be_mmu in do_csst
Richard Henderson [Sat, 20 May 2023 00:41:32 +0000 (17:41 -0700)]
target/s390x: Always use cpu_atomic_cmpxchgl_be_mmu in do_csst

Eliminate the CONFIG_USER_ONLY specialization.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: David Hildenbrand <david@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agotarget/s390x: Use cpu_{ld,st}*_mmu in do_csst
Richard Henderson [Sat, 20 May 2023 00:38:41 +0000 (17:38 -0700)]
target/s390x: Use cpu_{ld,st}*_mmu in do_csst

Use cpu_ld16_mmu and cpu_st16_mmu to eliminate the special case,
and change all of the *_data_ra functions to match.

Note that we check the alignment of both compare and store
pointers at the top of the function, so MO_ALIGN* may be
safely removed from the individual memory operations.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: David Hildenbrand <david@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agoaccel/tcg: Unify cpu_{ld,st}*_{be,le}_mmu
Richard Henderson [Sat, 20 May 2023 00:29:27 +0000 (17:29 -0700)]
accel/tcg: Unify cpu_{ld,st}*_{be,le}_mmu

With the current structure of cputlb.c, there is no difference
between the little-endian and big-endian entry points, aside
from the assert.  Unify the pairs of functions.

The only use of the functions with explicit endianness was in
target/sparc64, and that was only to satisfy the assert: the
correct endianness is already built into memop.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agotarget/s390x: Use tcg_gen_qemu_{ld,st}_i128 for LPQ, STPQ
Richard Henderson [Fri, 19 May 2023 22:47:06 +0000 (15:47 -0700)]
target/s390x: Use tcg_gen_qemu_{ld,st}_i128 for LPQ, STPQ

No need to roll our own, as this is now provided by tcg.
This was the last use of retxl, so remove that too.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: David Hildenbrand <david@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agotarget/ppc: Use tcg_gen_qemu_{ld,st}_i128 for LQARX, LQ, STQ
Richard Henderson [Fri, 19 May 2023 22:22:12 +0000 (15:22 -0700)]
target/ppc: Use tcg_gen_qemu_{ld,st}_i128 for LQARX, LQ, STQ

No need to roll our own, as this is now provided by tcg.
This was the last use of retxl, so remove that too.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agoinclude/qemu: Move CONFIG_ATOMIC128_OPT handling to atomic128.h
Richard Henderson [Thu, 18 May 2023 19:02:16 +0000 (19:02 +0000)]
include/qemu: Move CONFIG_ATOMIC128_OPT handling to atomic128.h

Not only the routines in ldst_atomicity.c.inc need markup,
but also the ones in the headers.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agomeson: Fix detect atomic128 support with optimization
Richard Henderson [Fri, 19 May 2023 19:01:36 +0000 (19:01 +0000)]
meson: Fix detect atomic128 support with optimization

Silly typo: sizeof(16) != 16.

Fixes: e61f1efeb730 ("meson: Detect atomic128 support with optimization")
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agoinclude/host: Split out atomic128-ldst.h
Richard Henderson [Thu, 18 May 2023 15:37:08 +0000 (08:37 -0700)]
include/host: Split out atomic128-ldst.h

Separates the aarch64-specific portion into its own file.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agoinclude/host: Split out atomic128-cas.h
Richard Henderson [Thu, 18 May 2023 15:22:51 +0000 (08:22 -0700)]
include/host: Split out atomic128-cas.h

Separates the aarch64-specific portion into its own file.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agoutil: Add cpuinfo-aarch64.c
Richard Henderson [Thu, 18 May 2023 03:50:45 +0000 (03:50 +0000)]
util: Add cpuinfo-aarch64.c

Move the code from tcg/.  The only use of these bits so far
is with respect to the atomicity of tcg operations.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agomigration: Build migration_files once
Richard Henderson [Thu, 18 May 2023 03:05:43 +0000 (20:05 -0700)]
migration: Build migration_files once

The items in migration_files are built for libmigration and included
info softmmu_ss from there; no need to also include them directly.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agomigration/xbzrle: Use i386 host/cpuinfo.h
Richard Henderson [Thu, 18 May 2023 03:00:30 +0000 (20:00 -0700)]
migration/xbzrle: Use i386 host/cpuinfo.h

Perform the function selection once, and only if CONFIG_AVX512_OPT
is enabled.  Centralize the selection to xbzrle.c, instead of
spreading the init across 3 files.

Remove xbzrle-bench.c.  The benefit of being able to benchmark
the different implementations is less important than not peeking
into the internals of the implementation.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agomigration/xbzrle: Shuffle function order
Richard Henderson [Thu, 18 May 2023 02:24:46 +0000 (19:24 -0700)]
migration/xbzrle: Shuffle function order

Place the CONFIG_AVX512BW_OPT block at the top,
which will aid function selection in the next patch.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agoutil/bufferiszero: Use i386 host/cpuinfo.h
Richard Henderson [Thu, 18 May 2023 02:10:59 +0000 (19:10 -0700)]
util/bufferiszero: Use i386 host/cpuinfo.h

Use cpuinfo_init() during init_accel(), and the variable cpuinfo
during test_buffer_is_zero_next_accel().  Adjust the logic that
cycles through the set of accelerators for testing.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agotcg/i386: Use host/cpuinfo.h
Richard Henderson [Thu, 18 May 2023 01:17:34 +0000 (18:17 -0700)]
tcg/i386: Use host/cpuinfo.h

Use the CPUINFO_* bits instead of the individual boolean
variables that we had been using.  Remove all of the init
code that was moved over to cpuinfo-i386.c.

Note that have_avx512* check both AVX512{F,VL}, as we had
previously done during tcg_target_init.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agoutil: Add i386 CPUINFO_ATOMIC_VMOVDQU
Richard Henderson [Thu, 18 May 2023 04:16:05 +0000 (21:16 -0700)]
util: Add i386 CPUINFO_ATOMIC_VMOVDQU

Add a bit to indicate when VMOVDQU is also atomic if aligned.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agoutil: Add cpuinfo-i386.c
Richard Henderson [Thu, 18 May 2023 04:12:08 +0000 (21:12 -0700)]
util: Add cpuinfo-i386.c

Add cpuinfo.h for i386 and x86_64, and the initialization
for that in util/.  Populate that with a slightly altered
copy of the tcg host probing code.  Other uses of cpuid.h
will be adjusted one patch at a time.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agoutil: Introduce host-specific cpuinfo.h
Richard Henderson [Thu, 18 May 2023 00:48:34 +0000 (17:48 -0700)]
util: Introduce host-specific cpuinfo.h

The entire contents of the header is host-specific, but the
existence of such a header is not, which could prevent some
host specific ifdefs at the top of the file for the include.

Add host/include/{arch,generic} to the project arguments.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agoMerge tag 'mem-2023-05-23' of https://github.com/davidhildenbrand/qemu into staging
Richard Henderson [Tue, 23 May 2023 17:57:25 +0000 (10:57 -0700)]
Merge tag 'mem-2023-05-23' of https://github.com/davidhildenbrand/qemu into staging

Hi,

"Host Memory Backends" and "Memory devices" queue ("mem"):
- New "offset" option for memory-backend-file

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# gpg: Signature made Tue 23 May 2023 07:47:58 AM PDT
# gpg:                using RSA key 1BD9CAAD735C4C3A460DFCCA4DDE10F700FF835A
# gpg:                issuer "david@redhat.com"
# gpg: Good signature from "David Hildenbrand <david@redhat.com>" [unknown]
# gpg:                 aka "David Hildenbrand <davidhildenbrand@gmail.com>" [undefined]
# gpg:                 aka "David Hildenbrand <hildenbr@in.tum.de>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 1BD9 CAAD 735C 4C3A 460D  FCCA 4DDE 10F7 00FF 835A

* tag 'mem-2023-05-23' of https://github.com/davidhildenbrand/qemu:
  hostmem-file: add offset option

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agohostmem-file: add offset option
Alexander Graf [Mon, 3 Apr 2023 22:14:21 +0000 (22:14 +0000)]
hostmem-file: add offset option

Add an option for hostmem-file to start the memory object at an offset
into the target file. This is useful if multiple memory objects reside
inside the same target file, such as a device node.

In particular, it's useful to map guest memory directly into /dev/mem
for experimentation.

To make this work consistently, also fix up all places in QEMU that
expect fd offsets to be 0.

Signed-off-by: Alexander Graf <graf@amazon.com>
Message-Id: <20230403221421.60877-1-graf@amazon.com>
Acked-by: Markus Armbruster <armbru@redhat.com>
Acked-by: Peter Xu <peterx@redhat.com>
Reviewed-by: David Hildenbrand <david@redhat.com>
Signed-off-by: David Hildenbrand <david@redhat.com>
12 months agoMerge tag 'net-pull-request' of https://github.com/jasowang/qemu into staging
Richard Henderson [Tue, 23 May 2023 13:22:12 +0000 (06:22 -0700)]
Merge tag 'net-pull-request' of https://github.com/jasowang/qemu into staging

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# gpg: Good signature from "Jason Wang (Jason Wang on RedHat) <jasowang@redhat.com>" [undefined]
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# Primary key fingerprint: 215D 46F4 8246 689E C77F  3562 EF04 965B 398D 6211

* tag 'net-pull-request' of https://github.com/jasowang/qemu: (50 commits)
  rtl8139: fix large_send_mss divide-by-zero
  docs/system/devices/igb: Note igb is tested for DPDK
  MAINTAINERS: Add a reviewer for network packet abstractions
  vmxnet3: Do not depend on PC
  igb: Clear-on-read ICR when ICR.INTA is set
  igb: Notify only new interrupts
  e1000e: Notify only new interrupts
  igb: Implement Tx timestamp
  igb: Implement Rx PTP2 timestamp
  igb: Implement igb-specific oversize check
  igb: Filter with the second VLAN tag for extended VLAN
  igb: Strip the second VLAN tag for extended VLAN
  igb: Implement Tx SCTP CSO
  igb: Implement Rx SCTP CSO
  igb: Use UDP for RSS hash
  igb: Implement MSI-X single vector mode
  tests/qtest/libqos/igb: Set GPIE.Multiple_MSIX
  hw/net/net_rx_pkt: Enforce alignment for eth_header
  net/eth: Always add VLAN tag
  net/eth: Use void pointers
  ...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agortl8139: fix large_send_mss divide-by-zero
Stefan Hajnoczi [Thu, 13 Apr 2023 17:19:46 +0000 (13:19 -0400)]
rtl8139: fix large_send_mss divide-by-zero

If the driver sets large_send_mss to 0 then a divide-by-zero occurs.
Even if the division wasn't a problem, the for loop that emits MSS-sized
packets would never terminate.

Solve these issues by skipping offloading when large_send_mss=0.

This issue was found by OSS-Fuzz as part of Alexander Bulekov's device
fuzzing work. The reproducer is:

  $ cat << EOF | ./qemu-system-i386 -display none -machine accel=qtest, -m \
  512M,slots=1,maxmem=0xffff000000000000 -machine q35 -nodefaults -device \
  rtl8139,netdev=net0 -netdev user,id=net0 -device \
  pc-dimm,id=nv1,memdev=mem1,addr=0xb800a64602800000 -object \
  memory-backend-ram,id=mem1,size=2M  -qtest stdio
  outl 0xcf8 0x80000814
  outl 0xcfc 0xe0000000
  outl 0xcf8 0x80000804
  outw 0xcfc 0x06
  write 0xe0000037 0x1 0x04
  write 0xe00000e0 0x2 0x01
  write 0x1 0x1 0x04
  write 0x3 0x1 0x98
  write 0xa 0x1 0x8c
  write 0xb 0x1 0x02
  write 0xc 0x1 0x46
  write 0xd 0x1 0xa6
  write 0xf 0x1 0xb8
  write 0xb800a646028c000c 0x1 0x08
  write 0xb800a646028c000e 0x1 0x47
  write 0xb800a646028c0010 0x1 0x02
  write 0xb800a646028c0017 0x1 0x06
  write 0xb800a646028c0036 0x1 0x80
  write 0xe00000d9 0x1 0x40
  EOF

Buglink: https://gitlab.com/qemu-project/qemu/-/issues/1582
Closes: https://gitlab.com/qemu-project/qemu/-/issues/1582
Cc: qemu-stable@nongnu.org
Cc: Peter Maydell <peter.maydell@linaro.org>
Fixes: 6d71357a3b65 ("rtl8139: honor large send MSS value")
Reported-by: Alexander Bulekov <alxndr@bu.edu>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Alexander Bulekov <alxndr@bu.edu>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
12 months agodocs/system/devices/igb: Note igb is tested for DPDK
Akihiko Odaki [Tue, 23 May 2023 02:43:39 +0000 (11:43 +0900)]
docs/system/devices/igb: Note igb is tested for DPDK

Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
12 months agoMAINTAINERS: Add a reviewer for network packet abstractions
Akihiko Odaki [Tue, 23 May 2023 02:43:38 +0000 (11:43 +0900)]
MAINTAINERS: Add a reviewer for network packet abstractions

I have made significant changes for network packet abstractions so add
me as a reviewer.

Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Jason Wang <jasowang@redhat.com>
12 months agovmxnet3: Do not depend on PC
Akihiko Odaki [Tue, 23 May 2023 02:43:37 +0000 (11:43 +0900)]
vmxnet3: Do not depend on PC

vmxnet3 has no dependency on PC, and VMware Fusion actually makes it
available on Apple Silicon according to:
https://kb.vmware.com/s/article/90364

Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Jason Wang <jasowang@redhat.com>
12 months agoigb: Clear-on-read ICR when ICR.INTA is set
Akihiko Odaki [Tue, 23 May 2023 02:43:36 +0000 (11:43 +0900)]
igb: Clear-on-read ICR when ICR.INTA is set

For GPIE.NSICR, Section 7.3.2.1.2 says:
> ICR bits are cleared on register read. If GPIE.NSICR = 0b, then the
> clear on read occurs only if no bit is set in the IMS or at least one
> bit is set in the IMS and there is a true interrupt as reflected in
> ICR.INTA.

e1000e does similar though it checks for CTRL_EXT.IAME, which does not
exist on igb.

Suggested-by: Sriram Yagnaraman <sriram.yagnaraman@est.tech>
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
12 months agoigb: Notify only new interrupts
Akihiko Odaki [Tue, 23 May 2023 02:43:35 +0000 (11:43 +0900)]
igb: Notify only new interrupts

This follows the corresponding change for e1000e. This fixes:
tests/avocado/netdev-ethtool.py:NetDevEthtool.test_igb

Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
12 months agoe1000e: Notify only new interrupts
Akihiko Odaki [Tue, 23 May 2023 02:43:34 +0000 (11:43 +0900)]
e1000e: Notify only new interrupts

In MSI-X mode, if there are interrupts already notified but not cleared
and a new interrupt arrives, e1000e incorrectly notifies the notified
ones again along with the new one.

To fix this issue, replace e1000e_update_interrupt_state() with
two new functions: e1000e_raise_interrupts() and
e1000e_lower_interrupts(). These functions don't only raise or lower
interrupts, but it also performs register writes which updates the
interrupt state. Before it performs a register write, these function
determines the interrupts already raised, and compares with the
interrupts raised after the register write to determine the interrupts
to notify.

The introduction of these functions made tracepoints which assumes that
the caller of e1000e_update_interrupt_state() performs register writes
obsolete. These tracepoints are now removed, and alternative ones are
added to the new functions.

Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
12 months agoigb: Implement Tx timestamp
Akihiko Odaki [Tue, 23 May 2023 02:43:33 +0000 (11:43 +0900)]
igb: Implement Tx timestamp

Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Sriram Yagnaraman <sriram.yagnaraman@est.tech>
Signed-off-by: Jason Wang <jasowang@redhat.com>
12 months agoigb: Implement Rx PTP2 timestamp
Akihiko Odaki [Tue, 23 May 2023 02:43:32 +0000 (11:43 +0900)]
igb: Implement Rx PTP2 timestamp

Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
12 months agoigb: Implement igb-specific oversize check
Akihiko Odaki [Tue, 23 May 2023 02:43:31 +0000 (11:43 +0900)]
igb: Implement igb-specific oversize check

igb has a configurable size limit for LPE, and uses different limits
depending on whether the packet is treated as a VLAN packet.

Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Sriram Yagnaraman <sriram.yagnaraman@est.tech>
Signed-off-by: Jason Wang <jasowang@redhat.com>
12 months agoigb: Filter with the second VLAN tag for extended VLAN
Akihiko Odaki [Tue, 23 May 2023 02:43:30 +0000 (11:43 +0900)]
igb: Filter with the second VLAN tag for extended VLAN

Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
12 months agoigb: Strip the second VLAN tag for extended VLAN
Akihiko Odaki [Tue, 23 May 2023 02:43:29 +0000 (11:43 +0900)]
igb: Strip the second VLAN tag for extended VLAN

Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
12 months agoigb: Implement Tx SCTP CSO
Akihiko Odaki [Tue, 23 May 2023 02:43:28 +0000 (11:43 +0900)]
igb: Implement Tx SCTP CSO

Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Sriram Yagnaraman <sriram.yagnaraman@est.tech>
Signed-off-by: Jason Wang <jasowang@redhat.com>
12 months agoigb: Implement Rx SCTP CSO
Akihiko Odaki [Tue, 23 May 2023 02:43:27 +0000 (11:43 +0900)]
igb: Implement Rx SCTP CSO

Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Sriram Yagnaraman <sriram.yagnaraman@est.tech>
Signed-off-by: Jason Wang <jasowang@redhat.com>
12 months agoigb: Use UDP for RSS hash
Akihiko Odaki [Tue, 23 May 2023 02:43:26 +0000 (11:43 +0900)]
igb: Use UDP for RSS hash

e1000e does not support using UDP for RSS hash, but igb does.

Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Sriram Yagnaraman <sriram.yagnaraman@est.tech>
Signed-off-by: Jason Wang <jasowang@redhat.com>
12 months agoigb: Implement MSI-X single vector mode
Akihiko Odaki [Tue, 23 May 2023 02:43:25 +0000 (11:43 +0900)]
igb: Implement MSI-X single vector mode

Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Sriram Yagnaraman <sriram.yagnaraman@est.tech>
Signed-off-by: Jason Wang <jasowang@redhat.com>
12 months agotests/qtest/libqos/igb: Set GPIE.Multiple_MSIX
Akihiko Odaki [Tue, 23 May 2023 02:43:24 +0000 (11:43 +0900)]
tests/qtest/libqos/igb: Set GPIE.Multiple_MSIX

GPIE.Multiple_MSIX is not set by default, and needs to be set to get
interrupts from multiple MSI-X vectors.

Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Sriram Yagnaraman <sriram.yagnaraman@est.tech>
Signed-off-by: Jason Wang <jasowang@redhat.com>
12 months agohw/net/net_rx_pkt: Enforce alignment for eth_header
Akihiko Odaki [Tue, 23 May 2023 02:43:23 +0000 (11:43 +0900)]
hw/net/net_rx_pkt: Enforce alignment for eth_header

eth_strip_vlan and eth_strip_vlan_ex refers to ehdr_buf as struct
eth_header. Enforce alignment for the structure.

Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Sriram Yagnaraman <sriram.yagnaraman@est.tech>
Signed-off-by: Jason Wang <jasowang@redhat.com>