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7 years agoclk: Hi3660: register fixed_rate_clks with CLK_OF_DECLARE_DRIVER
Leo Yan [Mon, 22 May 2017 04:52:27 +0000 (12:52 +0800)]
clk: Hi3660: register fixed_rate_clks with CLK_OF_DECLARE_DRIVER

The timer will register into system at very early phase at kernel boot;
if timer needs to use clock, the clock should be get ready in function
of_clk_init() so later the timer driver probe can retrieve clock
successfully. This is finished in below flow on arm64:

  start_kernel()
    `-> time_init()
          `-> of_clk_init(NULL)    => register timer's clock
          `-> clocksource_probe()  => register timer

On Hi3660 the sp804 timer uses clock "osc32k", this clock is registered
as platform driver rather than CLK_OF_DECLARE_DRIVER method. As result,
sp804 timer probe returns failure due if cannot bind clock properly.

To fix the failure, this patch is to split crgctrl clocks into two
subsets. One part is for fixed_rate_clks which includes pre-defined
fixed rate clocks, and "osc32k" clock is in this category; So we change
their registration to CLK_OF_DECLARE_DRIVER method, as result the clocks
can be registered ahead with function of_clk_init() and timer driver can
bind timer clock successfully; the rest of the crgctrl clocks are still
registered by the probe of the platform driver.

This patch also adds checking for all crgctrl clocks registration and
print out log if any clock has failure.

Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
7 years agoMerge tag 'meson-clk-for-4.13-2' of git://github.com/BayLibre/clk-meson into clk...
Stephen Boyd [Fri, 16 Jun 2017 22:01:46 +0000 (15:01 -0700)]
Merge tag 'meson-clk-for-4.13-2' of git://github.com/BayLibre/clk-meson into clk-next

Pull Amlogic clk driver updates from Jerome Brunet:

 * Expose more clock gate on meson8 (SAR ADC, RNG, USB, SDIO, ETH)
 * Add new compatible to the meson8 clock controller for meson8b
 * Add missing parents to gxbb clk81

* tag 'meson-clk-for-4.13-2' of git://github.com/BayLibre/clk-meson:
  clk: meson: gxbb: add all clk81 parents
  clk: meson: meson8b: add compatibles for Meson8 and Meson8m2
  clk: meson8b: export the ethernet gate clock
  clk: meson8b: export the USB clocks
  clk: meson8b: export the gate clock for the HW random number generator
  clk: meson8b: export the SDIO clock
  clk: meson8b: export the SAR ADC clocks

7 years agoMerge branch 'for-4.13-ti-clkctrl' of https://github.com/t-kristo/linux-pm into clk...
Stephen Boyd [Fri, 16 Jun 2017 21:52:02 +0000 (14:52 -0700)]
Merge branch 'for-4.13-ti-clkctrl' of https://github.com/t-kristo/linux-pm into clk-next

* 'for-4.13-ti-clkctrl' of https://github.com/t-kristo/linux-pm:
  clk: ti: omap4: add clkctrl clock data
  dt-bindings: clk: add omap4 clkctrl definitions
  clk: ti: add support for clkctrl clocks
  Documentation: dt-bindings: Add binding documentation for TI clkctrl clocks

7 years agoclk: sunxi-ng: Staticize ccu_mux_helper_unapply_prediv()
Stephen Boyd [Fri, 16 Jun 2017 21:50:41 +0000 (14:50 -0700)]
clk: sunxi-ng: Staticize ccu_mux_helper_unapply_prediv()

It isn't used outside of this file right now.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
7 years agoMerge tag 'sunxi-clk-for-4.13' of https://git.kernel.org/pub/scm/linux/kernel/git...
Stephen Boyd [Fri, 16 Jun 2017 21:45:27 +0000 (14:45 -0700)]
Merge tag 'sunxi-clk-for-4.13' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-next

Pull Allwinner clock patches from Maxime Ripard:

Some new clock units are supported, for the display clocks unsed in the
newer SoCs, and the A83T PRCM.

There is also a bunch of minor fixes for clocks that are not used by
anyone, and reworks needed by drivers that will land in 4.13.

* tag 'sunxi-clk-for-4.13' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: (21 commits)
  clk: sunxi-ng: Move all clock types to a library
  clk: sunxi-ng: a83t: Add support for A83T's PRCM
  dt-bindings: clock: sunxi-ccu: Add compatible string for A83T PRCM
  clk: sunxi-ng: select SUNXI_CCU_MULT for sun8i-a83t
  clk: sunxi-ng: a83t: Fix audio PLL divider offset
  clk: sunxi-ng: a83t: Fix PLL lock status register offset
  clk: sunxi-ng: Add driver for A83T CCU
  clk: sunxi-ng: Support multiple variable pre-dividers
  dt-bindings: clock: sunxi-ccu: Add compatible string for A83T CCU
  clk: sunxi-ng: de2: fix wrong pointer passed to PTR_ERR()
  clk: sunxi-ng: sun5i: Export video PLLs
  clk: sunxi-ng: mux: Re-adjust parent rate
  clk: sunxi-ng: mux: Change pre-divider application function prototype
  clk: sunxi-ng: mux: split out the pre-divider computation code
  clk: sunxi-ng: mux: Don't just rely on the parent for CLK_SET_RATE_PARENT
  clk: sunxi-ng: div: Switch to divider_round_rate
  clk: sunxi-ng: Pass the parent and a pointer to the clocks round rate
  clk: divider: Make divider_round_rate take the parent clock
  clk: sunxi-ng: explicitly include linux/spinlock.h
  clk: sunxi-ng: add support for DE2 CCU
  ...

7 years agoclk: meson: gxbb: add all clk81 parents
Jerome Brunet [Thu, 8 Jun 2017 13:55:45 +0000 (15:55 +0200)]
clk: meson: gxbb: add all clk81 parents

Remove the FIXME on clk81 mux and add all the documented parents

Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
7 years agoMerge branch 'next/headers' into next/drivers
Jerome Brunet [Fri, 16 Jun 2017 18:32:36 +0000 (18:32 +0000)]
Merge branch 'next/headers' into next/drivers

7 years agoclk: ti: omap4: add clkctrl clock data
Tero Kristo [Thu, 9 Feb 2017 09:34:23 +0000 (11:34 +0200)]
clk: ti: omap4: add clkctrl clock data

Add data for omap4 clkctrl clocks, and register it within the clkctrl
driver.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
7 years agodt-bindings: clk: add omap4 clkctrl definitions
Tero Kristo [Thu, 9 Feb 2017 09:33:04 +0000 (11:33 +0200)]
dt-bindings: clk: add omap4 clkctrl definitions

Contains offsets for all omap4 clkctrl main and optional clocks.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
7 years agoclk: ti: add support for clkctrl clocks
Tero Kristo [Thu, 9 Feb 2017 09:27:11 +0000 (11:27 +0200)]
clk: ti: add support for clkctrl clocks

Previously, hwmod core has been used for controlling the hwmod level
clocks directly. This has certain drawbacks, like being unable to share
the clocks for multiple users, missing usecounting and generally being
totally incompatible with the common clock framework.

This patch adds support for clkctrl clocks for addressing the above
issues. These support the modulemode handling, which will replace the
direct hwmod clkctrl linkage. Any optional clocks are also supported,
gate, mux and divider.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
7 years agoDocumentation: dt-bindings: Add binding documentation for TI clkctrl clocks
Tony Lindgren [Mon, 23 Jan 2017 22:17:02 +0000 (14:17 -0800)]
Documentation: dt-bindings: Add binding documentation for TI clkctrl clocks

Texas Instruments omap variant SoCs starting with omap4 have a clkctrl
clock controller instance for each interconnect target module. The clkctrl
controls functional and interface clocks for the module.

The clkctrl clocks are currently handled by arch/arm/mach-omap2 hwmod code.
With this binding and a related clock device driver we can start moving the
clkctrl clock handling to live in drivers/clk/ti.

Note that this binding allows keeping the clockdomain related parts out of
drivers/clock. The CLKCTCTRL and DYNAMICDEP registers can be handled by
a separate driver in drivers/soc/ti and genpd. If the clockdomain driver
needs to know it's clocks, we can just set the the clkctrl device
instances to be children of the related clockdomain device.

Each clkctrl clock can have multiple optional gate clocks, and multiple
optional mux clocks. To represent this in device tree, it seems that
it is best done using four clock cells #clock-cells = <2> property.

The reasons for using #clock-cells = <2> are:

1. We need to specify the clkctrl offset from the instance base. Otherwise
   we end up with a large number of device tree nodes that need to be
   patched when new clocks are discovered in a clkctrl clock with minor
   hardware revision changes for example

2. On omap5 CM_L3INIT_USB_HOST_HS_CLKCTRL has ten OPTFCLKEN bits. So we
   need to use a separate cell for optional gate clocks to avoid address
   space conflicts

There is probably no need to list input clocks for each clkctrl clock
instance in the binding. If we want to add them, the standard clocks
binding can be used for that.

For hardware reference, see omap4430 TRM "Table 3-1312. L4PER_CM2 Registers
Mapping Summary" for example. It shows one instance of a clkctrl clock
controller with multiple clkctrl registers.

Cc: Paul Walmsley <paul@pwsan.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
7 years agoMerge branch 'clk-fixes' into clk-next
Stephen Boyd [Wed, 14 Jun 2017 23:48:21 +0000 (16:48 -0700)]
Merge branch 'clk-fixes' into clk-next

* clk-fixes:
  clk: sunxi-ng: a64: Export PLL_PERIPH0 clock for the PRCM
  clk: sunxi-ng: h3: Export PLL_PERIPH0 clock for the PRCM
  dt-bindings: clock: sunxi-ccu: Add pll-periph to PRCM's needed clocks
  clk: sunxi-ng: enable SUNXI_CCU_MP for PRCM
  clk: sunxi-ng: v3s: Fix usb otg device reset bit
  clk: sunxi-ng: a31: Correct lcd1-ch1 clock register offset

7 years agoMerge tag 'sunxi-clk-fixes-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel...
Stephen Boyd [Wed, 14 Jun 2017 23:48:03 +0000 (16:48 -0700)]
Merge tag 'sunxi-clk-fixes-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-fixes

Allwinner clock fixes for 4.12

Some fixes that fix some bindings that went in 4.12, fix a few reset and
clock offsets and a build error fix

* tag 'sunxi-clk-fixes-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  clk: sunxi-ng: a64: Export PLL_PERIPH0 clock for the PRCM
  clk: sunxi-ng: h3: Export PLL_PERIPH0 clock for the PRCM
  dt-bindings: clock: sunxi-ccu: Add pll-periph to PRCM's needed clocks
  clk: sunxi-ng: enable SUNXI_CCU_MP for PRCM
  clk: sunxi-ng: v3s: Fix usb otg device reset bit
  clk: sunxi-ng: a31: Correct lcd1-ch1 clock register offset

7 years agoMerge tag 'clk-v4.13-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/snawro...
Stephen Boyd [Wed, 14 Jun 2017 17:36:30 +0000 (10:36 -0700)]
Merge tag 'clk-v4.13-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk into clk-next

Pull samsung clk driver updates from Sylwester Nawrocki

 - conversion to the clk_hw API
 - definitions and fixes of exynos5420 SoC audio subsystem
   related clocks

* tag 'clk-v4.13-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk:
  clk: samsung: exynos542x: Add EPLL rate table
  clk: samsung: Add missing exynos5420 audio related clocks
  clk: samsung: Add enable/disable operation for PLL36XX clocks
  clk: samsung: s5pv210-audss: Convert to the new clk_hw API
  clk: samsung: exynos-clkout: Convert to the new clk_hw API
  clk: samsung: exynos-audss: Convert to the new clk_hw API
  clk: samsung: Convert common drivers to the new clk_hw API
  clk: samsung: Add local variable to match its purpose
  clk: samsung: Remove dead code

7 years agoMerge tag 'v4.13-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git...
Stephen Boyd [Wed, 14 Jun 2017 17:33:04 +0000 (10:33 -0700)]
Merge tag 'v4.13-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next

Pull rockchip clk driver updates from Heiko Stuebner:

One new clock controller for the rk3128 soc, a fixup for the rk3228 cpuclk
table and the usual bunch of some new clock-ids and some clocks marked as
critical.

* tag 'v4.13-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  clk: rockchip: mark some special clk as critical on rk3368
  clk: rockchip: mark noc and some special clk as critical on rk3288
  clk: rockchip: mark noc and some special clk as critical on rk3228
  clk: rockchip: mark pclk_ddrupctl as critical_clock on rk3036
  clk: rockchip: add clock controller for rk3128
  dt-bindings: add bindings for rk3128 clock controller
  clk: rockchip: export more rk3228 clocks ids
  clk: rockchip: add ids for rk3399 testclks used for camera handling
  clk: rockchip: add dt-binding header for rk3128
  clk: rockchip: fix up the RK3228 clk cpu setting table
  clk: rockchip: add clock-ids for more rk3228 clocks
  clk: rockchip: add ids for camera on rk3399

7 years agoclk: keystone: Add sci-clk driver support
Tero Kristo [Tue, 13 Jun 2017 07:09:27 +0000 (10:09 +0300)]
clk: keystone: Add sci-clk driver support

In K2G, the clock handling is done through firmware executing on a
separate core. Linux kernel needs to communicate to the firmware
through TI system control interface to access any power management
related resources, including clocks.

The keystone sci-clk driver does this, by communicating to the
firmware through the TI SCI driver. The driver adds support for
registering clocks through DT, and basic required clock operations
like prepare/get_rate, etc.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
[sboyd@codeaurora.org: Make ti_sci_init_clocks() static]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
7 years agoDocumentation: dt: Add TI SCI clock driver
Tero Kristo [Mon, 22 May 2017 13:01:52 +0000 (16:01 +0300)]
Documentation: dt: Add TI SCI clock driver

Add a clock implementation, TI SCI clock, that will hook to the common
clock framework, and allow each clock to be controlled via TI SCI
protocol.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
7 years agoclk: meson: meson8b: add compatibles for Meson8 and Meson8m2
Martin Blumenstingl [Sun, 4 Jun 2017 18:33:39 +0000 (20:33 +0200)]
clk: meson: meson8b: add compatibles for Meson8 and Meson8m2

The clock controller on Meson8, Meson8b and Meson8m2 is very similar
based on the code from the Amlogic GPL kernel sources. Add separate
compatibles for each SoC to make sure that we can easily implement
all the small differences for each SoC later on.

In general the Meson8 and Meson8m2 seem to be almost identical as they
even share the same mach-meson8 directory in Amlogic's GPL kernel
sources.
The main clocks on Meson8, Meson8b and Meson8m2 are very similar,
because they are all using the same PLL values, 90% of the clock gates
are the same (the actual diffstat of the mach-meson8/clock.c and
mach-meson8b/clock.c files is around 30 to 40 lines, when excluding
all commented out code).
The difference between the Meson8 and Meson8b clock gates seem to be:
- Meson8 has AIU_PCLK, HDMI_RX, VCLK2_ENCT, VCLK2_ENCL, UART3,
  CSI_DIG_CLKIN gates which don't seem to be available on Meson8b
- the gate on Meson8 for bit 7 seems to be named "_1200XXX" instead
  of "PERIPHS_TOP" (on Meson8b)
- Meson8b has a SANA gate which doesn't seem to exist on Meson8 (or
  on Meson8 the same bit is used by the UART3 gate in Amlogic's GPL
  kernel sources)
None of these gates is added for now, since it's unclear whether these
definitions are actually correct (the VCLK2_ENCT gate for example is
defined, but only used in some commented block).

The main difference between all three SoCs seem to be the video (VPU)
clocks. Apart from different supported clock rates (according to vpu.c
in mach-meson8 and mach-meson8b from Amlogic's GPL kernel sources) the
most notable difference is that Meson8m2 has a GP_PLL clock and a mux
(probably the same as on the Meson GX SoCs) to support glitch-free
(clock rate) switching.
None of these VPU clocks are not supported by our mainline meson8b
clock driver yet though.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
7 years agoclk: meson8b: export the ethernet gate clock
Martin Blumenstingl [Sun, 11 Jun 2017 10:16:36 +0000 (12:16 +0200)]
clk: meson8b: export the ethernet gate clock

Export the ethernet gate clock to the dt-bindings.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
7 years agoclk: meson8b: export the USB clocks
Martin Blumenstingl [Sun, 11 Jun 2017 10:16:35 +0000 (12:16 +0200)]
clk: meson8b: export the USB clocks

Export the USB related clocks (for the USB controller and the USB2 PHYs)
so they can be used in the dt-bindings.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
7 years agoclk: meson8b: export the gate clock for the HW random number generator
Martin Blumenstingl [Sun, 11 Jun 2017 10:16:34 +0000 (12:16 +0200)]
clk: meson8b: export the gate clock for the HW random number generator

This exports the clock so it can be used in the dt-bindings.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
7 years agoclk: meson8b: export the SDIO clock
Martin Blumenstingl [Sun, 11 Jun 2017 10:16:33 +0000 (12:16 +0200)]
clk: meson8b: export the SDIO clock

Export the SDIO clock so it can be used in the dt-bindings.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
7 years agoclk: meson8b: export the SAR ADC clocks
Martin Blumenstingl [Sun, 11 Jun 2017 10:16:32 +0000 (12:16 +0200)]
clk: meson8b: export the SAR ADC clocks

Export the clocks for the SAR ADC so they can be used in the
dt-bindings.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
7 years agoclk: samsung: exynos542x: Add EPLL rate table
Sylwester Nawrocki [Fri, 9 Jun 2017 10:46:06 +0000 (12:46 +0200)]
clk: samsung: exynos542x: Add EPLL rate table

A specific clock rate table is added for EPLL so it is possible
to set frequency of the EPLL output clock as multiple of various
audio sampling rates.

Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
7 years agoclk: samsung: Add missing exynos5420 audio related clocks
Sylwester Nawrocki [Thu, 8 Jun 2017 10:03:24 +0000 (12:03 +0200)]
clk: samsung: Add missing exynos5420 audio related clocks

This patch adds missing definitions of mux clocks required for using
EPLL as the audio subsystem root clock on exynos5420/exynos5422 SoCs.

Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Tested-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
7 years agoclk: samsung: Add enable/disable operation for PLL36XX clocks
Sylwester Nawrocki [Thu, 8 Jun 2017 14:17:11 +0000 (16:17 +0200)]
clk: samsung: Add enable/disable operation for PLL36XX clocks

The existing enable/disable ops for PLL35XX are made more generic
and used also for PLL36XX. This fixes issues in the kernel with
PLL36XX PLLs when the PLL has not been already enabled by bootloader.

Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Tested-by: Chanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
7 years agoclk: samsung: s5pv210-audss: Convert to the new clk_hw API
Marek Szyprowski [Mon, 15 May 2017 06:51:04 +0000 (08:51 +0200)]
clk: samsung: s5pv210-audss: Convert to the new clk_hw API

Clock providers should use the new struct clk_hw based API, so convert
Samsung S5PV210 Audio Subsystem clock provider to the new approach.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
7 years agoclk: samsung: exynos-clkout: Convert to the new clk_hw API
Marek Szyprowski [Mon, 24 Apr 2017 06:42:22 +0000 (08:42 +0200)]
clk: samsung: exynos-clkout: Convert to the new clk_hw API

Clock providers should use the new struct clk_hw based API, so convert
Exynos CLKOUT clock provider to the new approach.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
7 years agoclk: samsung: exynos-audss: Convert to the new clk_hw API
Marek Szyprowski [Mon, 15 May 2017 06:50:47 +0000 (08:50 +0200)]
clk: samsung: exynos-audss: Convert to the new clk_hw API

Clock providers should use the new struct clk_hw based API, so convert
Exynos Audio Subsystem clock provider to the new approach.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
7 years agoclk: samsung: Convert common drivers to the new clk_hw API
Marek Szyprowski [Mon, 24 Apr 2017 06:42:20 +0000 (08:42 +0200)]
clk: samsung: Convert common drivers to the new clk_hw API

Clock providers should use the new struct clk_hw based API, so convert
Samsung clock providers and their helper functions to the new approach.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
7 years agoclk: samsung: Add local variable to match its purpose
Marek Szyprowski [Mon, 24 Apr 2017 07:54:12 +0000 (09:54 +0200)]
clk: samsung: Add local variable to match its purpose

Add new variable to avoid using clk pointer for different purposes across
the exynos_register_cpu_clock() function. This will help in future rewrite
for the new clk_hw API.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
7 years agoclk: samsung: Remove dead code
Marek Szyprowski [Mon, 24 Apr 2017 06:42:18 +0000 (08:42 +0200)]
clk: samsung: Remove dead code

samsung_clk_register_pll2550x() function is not used anymore,
so remove its declaration.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
7 years agoclk: sunxi-ng: Move all clock types to a library
Stephen Boyd [Fri, 2 Jun 2017 22:30:06 +0000 (15:30 -0700)]
clk: sunxi-ng: Move all clock types to a library

We've run into kconfig missing dependency errors in the sunxi-ng
code a couple times now. Each time the fix is to find the missing
select statement and add it to the Kconfig entry for a particular
SoC driver. Given that all this code is builtin (non-modular) we
don't need to do this complicated dependency tracking in Kconfig.
Instead we can move all the "library"ish code to be compiled as
lib-y instead of obj-y, let the linker throw away unused code in
the resulting vmlinux, and drop all the Kconfig stuff we use to
track clock types.

Suggested-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
[Maxime: added lib.a to obj-y, added the comment]
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
7 years agoclk: sunxi-ng: a83t: Add support for A83T's PRCM
Chen-Yu Tsai [Fri, 26 May 2017 08:00:24 +0000 (16:00 +0800)]
clk: sunxi-ng: a83t: Add support for A83T's PRCM

The A83T's PRCM has the same set of clocks and resets as the A64.
However, a few dividers are different. And due to the lack of a low
speed 32.768 kHz oscillator, a few of the clock parents are different.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
7 years agodt-bindings: clock: sunxi-ccu: Add compatible string for A83T PRCM
Chen-Yu Tsai [Fri, 26 May 2017 08:00:23 +0000 (16:00 +0800)]
dt-bindings: clock: sunxi-ccu: Add compatible string for A83T PRCM

The A83T's PRCM has the same set of clocks and resets as the A64.
However, a few dividers are different. And due to the lack of a low
speed 32.768 kHz oscillator, a few of the clock parents are different.

The PRCM also has controls for various power domains. These are not
supported yet.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
7 years agoclk: sunxi-ng: select SUNXI_CCU_MULT for sun8i-a83t
Arnd Bergmann [Mon, 22 May 2017 20:29:40 +0000 (22:29 +0200)]
clk: sunxi-ng: select SUNXI_CCU_MULT for sun8i-a83t

We get a link error when CCU_MULT is not set with the
newly added driver:

drivers/clk/sunxi-ng/ccu-sun8i-a83t.o:(.data.__compound_literal.1+0x4): undefined reference to `ccu_mult_ops'
drivers/clk/sunxi-ng/ccu-sun8i-a83t.o:(.data.__compound_literal.3+0x4): undefined reference to `ccu_mult_ops'

Fixes: 46b492116666 ("clk: sunxi-ng: Add driver for A83T CCU")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
7 years agoclk: sunxi-ng: a83t: Fix audio PLL divider offset
Chen-Yu Tsai [Mon, 22 May 2017 06:25:48 +0000 (14:25 +0800)]
clk: sunxi-ng: a83t: Fix audio PLL divider offset

The divider of the audio PLL has an offset of 1.
Fix this in the driver.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
7 years agoclk: sunxi-ng: a83t: Fix PLL lock status register offset
Chen-Yu Tsai [Mon, 22 May 2017 06:25:47 +0000 (14:25 +0800)]
clk: sunxi-ng: a83t: Fix PLL lock status register offset

The offset for the PLL lock status register was incorrectly set to
0x208, which actually points to an unused register. The correct
register offset is 0x20c.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
7 years agoclk: sunxi-ng: Add driver for A83T CCU
Chen-Yu Tsai [Fri, 19 May 2017 07:06:09 +0000 (15:06 +0800)]
clk: sunxi-ng: Add driver for A83T CCU

The A83T clock control unit is a hybrid of some new style clock designs
from the A80, and old style layout from the other Allwinner SoCs.

Like the A80, the SoC does not have a low speed 32.768 kHz oscillator.
Unlike the A80, there is no clock input either. The only low speed clock
available is the internal oscillator which runs at around 16 MHz,
divided by 512, yielding a low speed clock around 31.250 kHz.

Also, the MMC2 module clock supports switching to a "new timing" mode.
This mode divides the clock output by half, and disables the CCU based
clock delays. The MMC controller must be configure to the same mode,
and then use its internal clock delays.

This driver does not support runtime switching of the timing modes.
Instead, the new timing mode is enforced at probe time. Consumers can
check which mode is active by trying to get the current phase delay
of the MMC2 phase clocks, which will return -ENOTSUPP if the new
timing mode is active.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
7 years agoclk: sunxi-ng: Support multiple variable pre-dividers
Chen-Yu Tsai [Fri, 19 May 2017 07:06:08 +0000 (15:06 +0800)]
clk: sunxi-ng: Support multiple variable pre-dividers

On the A83T, the AHB1 clock has a shared pre-divider on the two
PLL-PERIPH clock parents. To support such instances of shared
pre-dividers, this patch extends the mux clock type to support
multiple variable pre-dividers.

As the pre-dividers are only used to calculate the rate, but
do not participate in the factorization process, this is fairly
straightforward.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
7 years agodt-bindings: clock: sunxi-ccu: Add compatible string for A83T CCU
Chen-Yu Tsai [Fri, 19 May 2017 07:06:07 +0000 (15:06 +0800)]
dt-bindings: clock: sunxi-ccu: Add compatible string for A83T CCU

The A83T clock control unit is a hybrid of some new style clock designs
from the A80, and old style layout from the other Allwinner SoCs.

Like the A80, the SoC does not have a low speed 32.768 kHz oscillator.
Unlike the A80, there is no clock input either. The only low speed clock
available is the internal oscillator which runs at around 16 MHz,
divided by 512, yielding a low speed clock around 31.250 kHz.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
7 years agoclk: sunxi-ng: de2: fix wrong pointer passed to PTR_ERR()
Wei Yongjun [Thu, 18 May 2017 15:55:13 +0000 (15:55 +0000)]
clk: sunxi-ng: de2: fix wrong pointer passed to PTR_ERR()

PTR_ERR should access the value just tested by IS_ERR, otherwise
the wrong error code will be returned.

Fixes: b0d9a4bd52bd ("clk: sunxi-ng: add support for DE2 CCU")
Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
7 years agoclk: sunxi-ng: sun5i: Export video PLLs
Maxime Ripard [Wed, 17 May 2017 07:40:37 +0000 (09:40 +0200)]
clk: sunxi-ng: sun5i: Export video PLLs

The video PLLs are used directly by the HDMI controller. Export them so
that we can use them in our DT node.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
7 years agoclk: sunxi-ng: mux: Re-adjust parent rate
Maxime Ripard [Wed, 17 May 2017 07:40:36 +0000 (09:40 +0200)]
clk: sunxi-ng: mux: Re-adjust parent rate

Currently, the parent rate given back to the clock framework in our
request is the original parent rate we calculated before trying to round
the rate of our clock.

This works fine unless our clock also changes its parent rate, in which
case we will simply ignore that change and still use the previous parent
rate.

Create a new function to re-adjust the parent rate to take the pre-dividers
into account, and give that back to the clock framework.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
7 years agoclk: sunxi-ng: mux: Change pre-divider application function prototype
Maxime Ripard [Wed, 17 May 2017 07:40:35 +0000 (09:40 +0200)]
clk: sunxi-ng: mux: Change pre-divider application function prototype

The current function name is a bit confusing, and doesn't really allow to
create an explicit function to reverse the operation.

We also for now change the parent rate through a pointer, while we don't
return anything.

In order to be less confusing, and easier to use for downstream users,
change the function name to something hopefully clearer, and return the
adjusted rate instead of changing the pointer.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
7 years agoclk: sunxi-ng: mux: split out the pre-divider computation code
Maxime Ripard [Wed, 17 May 2017 07:40:34 +0000 (09:40 +0200)]
clk: sunxi-ng: mux: split out the pre-divider computation code

The pre-divider retrieval code was merged into the function to apply the
current pre-divider onto the parent clock rate so that we can use that
adjusted value to do our factors computation.

However, since we'll need to do the reverse operation, we need to split out
that code into a function that will be shared.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
7 years agoclk: sunxi-ng: mux: Don't just rely on the parent for CLK_SET_RATE_PARENT
Maxime Ripard [Wed, 17 May 2017 07:40:33 +0000 (09:40 +0200)]
clk: sunxi-ng: mux: Don't just rely on the parent for CLK_SET_RATE_PARENT

The current code only rely on the parent to change its rate in the case
where CLK_SET_RATE_PARENT is set.

However, some clock rates might be obtained only through a modification of
the parent and the clock divider. Just rely on the round rate of the clocks
to give us the best computation that might be achieved for a given rate.

round_rate functions now need to honor CLK_SET_RATE_PARENT, but either the
functions already do that if they modify the parent, or don't modify the
praents at all.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
7 years agoclk: sunxi-ng: div: Switch to divider_round_rate
Maxime Ripard [Wed, 17 May 2017 07:40:32 +0000 (09:40 +0200)]
clk: sunxi-ng: div: Switch to divider_round_rate

divider_round_rate_parent already evaluates changing the parent rate if
CLK_SET_RATE_PARENT is set. Now that we can do that on muxes too, let's
just use it.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
7 years agoclk: sunxi-ng: Pass the parent and a pointer to the clocks round rate
Maxime Ripard [Wed, 17 May 2017 07:40:31 +0000 (09:40 +0200)]
clk: sunxi-ng: Pass the parent and a pointer to the clocks round rate

The clocks might need to modify their parent clocks. In order to make that
possible, give them access to the parent clock being evaluated, and to a
pointer to the parent rate so that they can modify it if needed.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
7 years agoclk: divider: Make divider_round_rate take the parent clock
Maxime Ripard [Wed, 17 May 2017 07:40:30 +0000 (09:40 +0200)]
clk: divider: Make divider_round_rate take the parent clock

So far, divider_round_rate only considers the parent clock returned by
clk_hw_get_parent.

This works fine on clocks that have a single parents, this doesn't work on
muxes, since we will only consider the first parent, while other parents
may totally be able to provide a better combination.

Clocks in that case cannot use divider_round_rate, so would have to come up
with a very similar logic to work around it. Instead of having to do
something like this, and duplicate that logic everywhere, create a
divider_round_rate parent to allow caller to give an additional parameter
for the parent clock to consider.

Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
7 years agoclk: sunxi-ng: explicitly include linux/spinlock.h
Tobias Klauser [Mon, 15 May 2017 10:23:07 +0000 (12:23 +0200)]
clk: sunxi-ng: explicitly include linux/spinlock.h

ccu_reset.h and ccu_reset.c use spinlock_t and associated functions but
rely on implict inclusion of linux/spinlock.h which means that changes
in other headers could break the build. Thus, add an explicit include.

Signed-off-by: Tobias Klauser <tklauser@distanz.ch>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
7 years agoclk: sunxi-ng: add support for DE2 CCU
Icenowy Zheng [Sun, 14 May 2017 16:30:34 +0000 (00:30 +0800)]
clk: sunxi-ng: add support for DE2 CCU

The "Display Engine 2.0" in Allwinner newer SoCs contains a clock
management unit for its subunits, like the DE CCU in A80.

Add a sunxi-ng style driver for it.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
7 years agodt-bindings: add binding for the Allwinner DE2 CCU
Icenowy Zheng [Sun, 14 May 2017 16:30:33 +0000 (00:30 +0800)]
dt-bindings: add binding for the Allwinner DE2 CCU

Allwinner "Display Engine 2.0" contains some clock controls in it.

In order to add them as clock drivers, we need a device tree binding.
Add the binding here.

Also add the device tree binding headers.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
7 years agoclk: imx7d: Fix the DDR PLL enable bit
Fabio Estevam [Tue, 6 Jun 2017 15:45:54 +0000 (12:45 -0300)]
clk: imx7d: Fix the DDR PLL enable bit

Commit ad14972422899b6 ("clk: imx7d: Fix the powerdown bit location
of PLL DDR") used the incorrect bit for the IMX_PLLV3_DDR_IMX7 case.

Fix it accordingly to avoid a kernel hang.

Reported-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
7 years agoclk: at91: fix clk-generated compilation
Alexandre Belloni [Sun, 4 Jun 2017 22:02:57 +0000 (00:02 +0200)]
clk: at91: fix clk-generated compilation

Fix missing }

Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
7 years agoclk: versatile: delete old RealView clock implementation
Linus Walleij [Fri, 12 May 2017 07:40:49 +0000 (09:40 +0200)]
clk: versatile: delete old RealView clock implementation

The old RealView clock implementation is not used anymore
(nothing in the kernel calls realview_clk_init()) as we have
moved all clocks over to device tree. Delete it.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
7 years agoclk: bcm2835: Minimise clock jitter for PCM clock
Phil Elwell [Thu, 1 Jun 2017 14:14:22 +0000 (15:14 +0100)]
clk: bcm2835: Minimise clock jitter for PCM clock

Fractional clock dividers generate accurate average frequencies but
with jitter, particularly when the integer divisor is small.

Introduce a new metric of clock accuracy to penalise clocks with a good
average but worse jitter compared to clocks with an average which is no
better but with lower jitter. The metric is the ideal rate minus the
worse deviation from that ideal using the nearest integer divisors.

Use this metric for parent selection for clocks requiring low jitter
(currently just PCM).

Signed-off-by: Phil Elwell <phil@raspberrypi.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Acked-by: Stefan Wahren <stefan.wahren@i2se.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
7 years agoclk: bcm2835: Limit PCM clock to OSC and PLLD_PER
Phil Elwell [Thu, 1 Jun 2017 14:14:16 +0000 (15:14 +0100)]
clk: bcm2835: Limit PCM clock to OSC and PLLD_PER

Restrict clock sources for the PCM peripheral to the oscillator and
PLLD_PER because other source may have varying rates or be switched off.
Prevent other sources from being selected by replacing their names in
the list of potential parents with dummy entries (entry index is
significant).

Signed-off-by: Phil Elwell <phil@raspberrypi.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Acked-by: Stefan Wahren <stefan.wahren@i2se.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
7 years agoclk: bcm2835: Correct the prediv logic
Phil Elwell [Mon, 15 May 2017 17:35:04 +0000 (10:35 -0700)]
clk: bcm2835: Correct the prediv logic

If a clock has the prediv flag set, both the integer and fractional
parts must be scaled when calculating the resulting frequency.

Signed-off-by: Phil Elwell <phil@raspberrypi.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
7 years agoMerge branch 'clk-bulk-get' into clk-next
Stephen Boyd [Fri, 2 Jun 2017 22:39:32 +0000 (15:39 -0700)]
Merge branch 'clk-bulk-get' into clk-next

* clk-bulk-get:
  clk: add managed version of clk_bulk_get
  clk: add clk_bulk_get accessories

7 years agoclk: add managed version of clk_bulk_get
Dong Aisheng [Fri, 19 May 2017 13:49:05 +0000 (21:49 +0800)]
clk: add managed version of clk_bulk_get

This patch introduces the managed version of clk_bulk_get.

Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: "Rafael J. Wysocki" <rjw@rjwysocki.net>
Cc: Viresh Kumar <viresh.kumar@linaro.org>
Cc: Mark Brown <broonie@kernel.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Anson Huang <anson.huang@nxp.com>
Cc: Robin Gong <yibin.gong@nxp.com>
Cc: Bai Ping <ping.bai@nxp.com>
Cc: Leonard Crestez <leonard.crestez@nxp.com>
Cc: Octavian Purdila <octavian.purdila@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
7 years agoclk: add clk_bulk_get accessories
Dong Aisheng [Fri, 19 May 2017 13:49:04 +0000 (21:49 +0800)]
clk: add clk_bulk_get accessories

These helper function allows drivers to get several clk consumers in
one operation. If any of the clk cannot be acquired then any clks
that were got will be put before returning to the caller.

This can relieve the driver owners' life who needs to handle many clocks,
as well as each clock error reporting.

Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: "Rafael J. Wysocki" <rjw@rjwysocki.net>
Cc: Viresh Kumar <viresh.kumar@linaro.org>
Cc: Mark Brown <broonie@kernel.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Anson Huang <anson.huang@nxp.com>
Cc: Robin Gong <yibin.gong@nxp.com>
Cc: Bai Ping <ping.bai@nxp.com>
Cc: Leonard Crestez <leonard.crestez@nxp.com>
Cc: Octavian Purdila <octavian.purdila@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
7 years agoclk: meson-gxbb: Add const to some parent name arrays
Stephen Boyd [Fri, 2 Jun 2017 17:57:05 +0000 (10:57 -0700)]
clk: meson-gxbb: Add const to some parent name arrays

These can be marked as const * const.

Cc: Neil Armstrong <narmstrong@baylibre.com>
Cc: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
7 years agoMerge tag 'meson-clk-for-4.13' of git://github.com/BayLibre/clk-meson into clk-next
Stephen Boyd [Fri, 2 Jun 2017 17:51:41 +0000 (10:51 -0700)]
Merge tag 'meson-clk-for-4.13' of git://github.com/BayLibre/clk-meson into clk-next

Pull Amlogic clock driver updates from Jerome Brunet:

 * Expose more i2s and spdif output clocks
 * Expose EE uart and SPICC gate clocks
 * Remove cpu_clk from to gxbb
 * Mark clk81 as critical on gxbb
 * Add CEC EE clocks

* tag 'meson-clk-for-4.13' of git://github.com/BayLibre/clk-meson:
  clk: meson-gxbb: Add EE 32K Clock for CEC
  clk: gxbb: remove CLK_IGNORE_UNUSED from clk81
  clk: meson: meson8b: mark clk81 as critical
  clk: meson: gxbb: remove the "cpu_clk" from the GXBB and GXL driver
  clk: meson-gxbb: un-export the CPU clock
  clk: meson-gxbb: expose UART clocks
  clk: meson-gxbb: expose SPICC gate
  clk: meson-gxbb: expose spdif master clock
  clk: meson-gxbb: expose i2s master clock
  clk: meson-gxbb: expose spdif clock gates

7 years agoclk: palmas: undo preparation of a clock source.
Arvind Yadav [Fri, 28 Apr 2017 13:03:07 +0000 (18:33 +0530)]
clk: palmas: undo preparation of a clock source.

Undo preparation of a clock source, if palmas_clks_init_configure is not
successful.

Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
7 years agoclk: Provide dummy of_clk_get_from_provider() for compile-testing
Geert Uytterhoeven [Fri, 28 Apr 2017 13:08:53 +0000 (15:08 +0200)]
clk: Provide dummy of_clk_get_from_provider() for compile-testing

When CONFIG_ON=n, dummies are provided for of_clk_get() and
of_clk_get_by_name(), but not for of_clk_get_from_provider().

Provide a dummy for the latter, to improve the ability to do
compile-testing.  This requires removing the existing dummy in the
Lantiq clock code.

Fixes: 766e6a4ec602d0c1 ("clk: add DT clock binding support")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Thomas Langer <thomas.langer@intel.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
7 years agoclk: rockchip: mark some special clk as critical on rk3368
Elaine Zhang [Tue, 2 May 2017 07:34:06 +0000 (15:34 +0800)]
clk: rockchip: mark some special clk as critical on rk3368

The jtag clk no driver to handle them.
But this clk need enable,so make it as critical.

The ddrphy/ddrupctl clks no driver to handle them,
Chip design requirements for these clock to always on,

The pmu_hclk_otg0 is Chip design defect, must be always on,

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
7 years agoclk: rockchip: mark noc and some special clk as critical on rk3288
Elaine Zhang [Tue, 2 May 2017 07:34:05 +0000 (15:34 +0800)]
clk: rockchip: mark noc and some special clk as critical on rk3288

The atclk/dbg/jtag/hsic-xin12m/pclk_core clks no driver to handle them.
But this clks need enable,so make it as ignore_unused for now.

The ddrupctl0/ddrupctl1/publ0/publ1 clks no driver to handle them,
Chip design requirements for these clock to always on,

The pmu_hclk_otg0 is Chip design defect, must be always on,

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
7 years agoclk: rockchip: mark noc and some special clk as critical on rk3228
Elaine Zhang [Tue, 2 May 2017 07:34:04 +0000 (15:34 +0800)]
clk: rockchip: mark noc and some special clk as critical on rk3228

The jtag/bus/peri/initmem/rom/stimer/phy clks no driver to handle them.
But this clks need enable,so make it as critical.

The ddrupctl/ddrmon/ddrphy clks no driver to handle them,
Chip design requirements for these clock to always on,

The hclk_otg_pmu is Chip design defect, must be always on,
The new document will update the description of this clock.

All these non-noc/non-arbi clocks,IC suggest always on,
Because it's have some order limitation, between the NOC clock switch
and bus IDLE(or pd on/off).

The software is not very good to solve this constraint.
Always on these clocks, has no effect on the system power consumption.
The new document will update the description of these clock.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
7 years agoclk: rockchip: mark pclk_ddrupctl as critical_clock on rk3036
Elaine Zhang [Tue, 2 May 2017 07:34:03 +0000 (15:34 +0800)]
clk: rockchip: mark pclk_ddrupctl as critical_clock on rk3036

No driver to handle this clk yet, but chip design requiress for this clock
supplying the ddr controller to be always on.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
7 years agoclk: rockchip: add clock controller for rk3128
Elaine Zhang [Fri, 2 Jun 2017 01:47:25 +0000 (09:47 +0800)]
clk: rockchip: add clock controller for rk3128

Add the clock tree definition for the new rk3128 SoC.
And it also applies to the RK3126 SoC.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
7 years agodt-bindings: add bindings for rk3128 clock controller
Elaine Zhang [Fri, 2 Jun 2017 01:47:24 +0000 (09:47 +0800)]
dt-bindings: add bindings for rk3128 clock controller

Add devicetree bindings for Rockchip cru which found on
Rockchip SoCs.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
7 years agoclk: rockchip: export more rk3228 clocks ids
Elaine Zhang [Fri, 28 Apr 2017 07:02:47 +0000 (15:02 +0800)]
clk: rockchip: export more rk3228 clocks ids

This patch exports related BUS/VPU/RGA/HDCP/IEP/TSP/WIFI/
VIO/USB/EFUSE/GPU/CRYPTO clocks for dts reference.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
7 years agoclk: rockchip: add ids for rk3399 testclks used for camera handling
Eddie Cai [Tue, 25 Apr 2017 06:41:10 +0000 (14:41 +0800)]
clk: rockchip: add ids for rk3399 testclks used for camera handling

clk_testout1 and clk_testout2 are used for camera handling, so add their ids.

Signed-off-by: Eddie Cai <eddie.cai.linux@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
7 years agoMerge branch 'v4.13-shared/clkids' into v4.13-clk/next
Heiko Stuebner [Fri, 2 Jun 2017 12:48:32 +0000 (14:48 +0200)]
Merge branch 'v4.13-shared/clkids' into v4.13-clk/next

7 years agoclk: rockchip: add dt-binding header for rk3128
Elaine Zhang [Fri, 2 Jun 2017 01:47:23 +0000 (09:47 +0800)]
clk: rockchip: add dt-binding header for rk3128

Add the dt-bindings header for the rk3128,
that gets shared between the clock controller and
the clock references in the dts.
Add softreset ID for rk3128.
And it also applies to the RK3126 SoC.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
7 years agoMerge tag 'clk-renesas-for-v4.13-tag1' of git://git.kernel.org/pub/scm/linux/kernel...
Michael Turquette [Fri, 2 Jun 2017 05:03:59 +0000 (14:03 +0900)]
Merge tag 'clk-renesas-for-v4.13-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next

clk: renesas: Updates for v4.13

  - Add more module clocks for R-Car H3 ES2.0 and M3-W,
  - Add CPG/MSSR drivers for all supported R-Car Gen2 SoCs, enabling support
    for module resets, which are not supported by the existing driver,
  - Rework Kconfig and Makefile logic,
  - Small fixes and cleanups.

7 years agoclk: Fix __set_clk_rates error print-string
Bryan O'Donoghue [Mon, 15 May 2017 10:58:59 +0000 (11:58 +0100)]
clk: Fix __set_clk_rates error print-string

When failing to set a clock the printout emitted is incorrect.
"u32 rate" is formatted as %d and should be %u whereas "unsigned long
clk_set_rate()" is formatted as %ld and should be %lu as per
Documentation/printk-formats.txt.

Fixes: 2885c3b2a3da ("clk: Show correct information when fail to set clock rate")
Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
7 years agoclk: scpi: fix return type of __scpi_dvfs_round_rate
Sudeep Holla [Thu, 18 May 2017 16:19:28 +0000 (17:19 +0100)]
clk: scpi: fix return type of __scpi_dvfs_round_rate

The frequencies above the maximum value of signed integer(i.e. 2^31 -1)
will overflow with the current code.

This patch fixes the return type of __scpi_dvfs_round_rate from 'int'
to 'unsigned long'.

Fixes: cd52c2a4b5c4 ("clk: add support for clocks provided by SCP(System Control Processor)")
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
7 years agoclk: qoriq: Separate root input clock for core PLLs on ls1012a
Scott Wood [Mon, 20 Mar 2017 02:37:23 +0000 (10:37 +0800)]
clk: qoriq: Separate root input clock for core PLLs on ls1012a

ls1012a has separate input root clocks for core PLLs versus the
platform PLL, with the latter described as sysclk in the hw docs.
If a second input clock, named "coreclk", is present, this clock will be
used for the core PLLs.

Signed-off-by: Scott Wood <oss@buserror.net>
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
7 years agodt-bindings: qoriq-clock: Add coreclk
Scott Wood [Mon, 20 Mar 2017 02:37:22 +0000 (10:37 +0800)]
dt-bindings: qoriq-clock: Add coreclk

ls1012a has separate input root clocks for core PLLs versus the platform
PLL, with the latter described as sysclk in the hw docs.
Update the qoriq-clock binding to allow a second input clock, named
"coreclk".  If present, this clock will be used for the core PLLs.

Signed-off-by: Scott Wood <oss@buserror.net>
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
7 years agoclk: at91: fix clk-generated parenting
Alexandre Belloni [Fri, 12 May 2017 14:25:30 +0000 (16:25 +0200)]
clk: at91: fix clk-generated parenting

clk_generated_startup is called after clk_hw_register. So the first call to
get_parent will not have the correct value (i.e. 0) and because this is
cached, it may never be updated.

Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Fixes: df70aeef6083 ("clk: at91: add generated clock driver")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
7 years agoclk: imx7d: Fix the powerdown bit location of PLL DDR
Fabio Estevam [Mon, 15 May 2017 11:55:05 +0000 (08:55 -0300)]
clk: imx7d: Fix the powerdown bit location of PLL DDR

According to the MX7D Reference Manual the powerdown bit of
CCM_ANALOG_PLL_DDRn register is bit 20, so fix it accordingly.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
7 years agoclk: mvebu: armada-38x: add support for 1866MHz variants
Ralph Sennhauser [Wed, 24 May 2017 14:58:52 +0000 (16:58 +0200)]
clk: mvebu: armada-38x: add support for 1866MHz variants

The Linksys WRT3200ACM CPU is clocked at 1866MHz. Add 1866MHz to the
list of supported CPU frequencies. Also update multiplier and divisor
for the l2clk and ddrclk.

Noticed by the following warning:
[    0.000000] Selected CPU frequency (16) unsupported

Signed-off-by: Ralph Sennhauser <ralph.sennhauser@gmail.com>
Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
7 years agoMerge branch 'clk-ap806' into clk-next
Michael Turquette [Thu, 1 Jun 2017 03:16:35 +0000 (12:16 +0900)]
Merge branch 'clk-ap806' into clk-next

7 years agoclk: mvebu: ap806: introduce a new binding
Gregory CLEMENT [Wed, 31 May 2017 14:07:26 +0000 (16:07 +0200)]
clk: mvebu: ap806: introduce a new binding

As for cp110, the initial intent when the binding of the ap806 system
controller was to have one flat node. The idea being that what is
currently a clock-only driver in drivers would become a MFD driver,
exposing the clock, GPIO and pinctrl functionality. However, after taking
a step back, this would lead to a messy binding. Indeed, a single node
would be a GPIO controller, clock controller, pinmux controller, and
more.

This patch adopts a more classical solution of a top-level syscon node
with sub-nodes for the individual devices. The main benefit will be to
have each functional block associated to its own sub-node where we can
put its own properties.

The introduction of the Armada 7K/8K is still in the early stage so the
plan is to remove the old binding. However, we don't want to break the
device tree compatibility for the few devices already in the field. For
this we still keep the support of the legacy compatible string with a big
warning in the kernel about updating the device tree.

Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/cc8c8c40fa4c4e71133033358992ec38e5aa2be5.1496239589.git-series.gregory.clement@free-electrons.com

7 years agoclk: mvebu: ap806: do not depend anymore of the *-clock-output-names
Gregory CLEMENT [Wed, 31 May 2017 14:07:24 +0000 (16:07 +0200)]
clk: mvebu: ap806: do not depend anymore of the *-clock-output-names

As it was done for the cp110, this patch modifies the way the clock names
are created. The name of each clock is now created by using its physical
address as a prefix (as it was done for the platform device
names). Thanks to this we have an automatic way to compute a unique name.

Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/e66cdd54d36c6bef78460a51e577f171b6ccb031.1496239589.git-series.gregory.clement@free-electrons.com

7 years agoclk: mvebu: ap806: cosmetic improvement
Gregory CLEMENT [Wed, 31 May 2017 14:07:22 +0000 (16:07 +0200)]
clk: mvebu: ap806: cosmetic improvement

Instead of using &pdev->dev all over the place, introduce a pointer
variable for it.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/5a55e081d96fc6d2a28331b59df90f56d32a9f24.1496239589.git-series.gregory.clement@free-electrons.com

7 years agodt-bindings: ap806: introduce a new binding
Gregory CLEMENT [Wed, 31 May 2017 14:07:25 +0000 (16:07 +0200)]
dt-bindings: ap806: introduce a new binding

This patch updates the documentation according to the changes made in the
patch "clk: mvebu: ap806: introduce a new binding"

Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/32e35c1d5919bdf9dc7d58678f0c0b462886d03e.1496239589.git-series.gregory.clement@free-electrons.com

7 years agodt-bindings: ap806: do not depend anymore of the *-clock-output-names
Gregory CLEMENT [Wed, 31 May 2017 14:07:23 +0000 (16:07 +0200)]
dt-bindings: ap806: do not depend anymore of the *-clock-output-names

This patch updates the documentation according to the change made in the
patch "clk: mvebu: ap806: do not depend anymore of the
*-clock-output-names": the clock names are no more part of the binding.

Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/d502b5abc68cbb5739ce72ba8be27528f9042a28.1496239589.git-series.gregory.clement@free-electrons.com

7 years agoclk: sunxi-ng: a64: Export PLL_PERIPH0 clock for the PRCM
Chen-Yu Tsai [Wed, 31 May 2017 07:58:23 +0000 (15:58 +0800)]
clk: sunxi-ng: a64: Export PLL_PERIPH0 clock for the PRCM

The PRCM takes PLL_PERIPH0 as one of its parents for the AR100 clock.
As such we need to be able to describe this relationship in the device
tree.

Export the PLL_PERIPH0 clock so we can reference it in the PRCM node.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
7 years agoclk: sunxi-ng: h3: Export PLL_PERIPH0 clock for the PRCM
Chen-Yu Tsai [Wed, 31 May 2017 07:58:21 +0000 (15:58 +0800)]
clk: sunxi-ng: h3: Export PLL_PERIPH0 clock for the PRCM

The PRCM takes PLL_PERIPH0 as one of its parents for the AR100 clock.
As such we need to be able to describe this relationship in the device
tree.

Export the PLL_PERIPH0 clock so we can reference it in the PRCM node.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
7 years agodt-bindings: clock: sunxi-ccu: Add pll-periph to PRCM's needed clocks
Chen-Yu Tsai [Wed, 31 May 2017 07:58:19 +0000 (15:58 +0800)]
dt-bindings: clock: sunxi-ccu: Add pll-periph to PRCM's needed clocks

The AR100 clock in the PRCM has parents, one of which is pll-periph from
the main CCU.

Add it to the list of required clocks for the PRCM CCU.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
7 years agoclk: meson-gxbb: Add EE 32K Clock for CEC
Neil Armstrong [Wed, 24 May 2017 09:43:45 +0000 (11:43 +0200)]
clk: meson-gxbb: Add EE 32K Clock for CEC

On Amlogic GX SoCs, there is two CEC controllers :
- An Amlogic CEC custom in the AO domain
- The Synopsys HDMI-TX Controller in the EE domain

Each of these controllers needs a 32.768KHz clock, but there is two paths :
- In the EE domain, the "32k_clk" this patchs is adding
- In the AO domain, with a more complex dual divider more precise setup

The AO 32K clock support will be pushed later in the corresponding
gxbb-aoclk driver when the AE CEC driver is ready.

The EE 32k_clk must be pushed earlier since mainline support for CEC in the
Synopsys HDMI-TX controller is nearby.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
[Rebased patch on top of last changes]
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
7 years agoclk: gxbb: remove CLK_IGNORE_UNUSED from clk81
Jerome Brunet [Wed, 24 May 2017 09:39:32 +0000 (11:39 +0200)]
clk: gxbb: remove CLK_IGNORE_UNUSED from clk81

clk81 already has CLK_IS_CRITICAL so CLK_IGNORE_UNUSED is not
necessary

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
7 years agoclk: meson: meson8b: mark clk81 as critical
Martin Blumenstingl [Wed, 24 May 2017 09:39:31 +0000 (11:39 +0200)]
clk: meson: meson8b: mark clk81 as critical

Disabling clk81 results in an immediate freeze of the whole system. This
can happen "accidentally" when the last child-clock of clk81 is disabled
(in this case the common clock framework also disables clk81, even if it
was only enabled indirectly before).

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
7 years agoclk: meson: gxbb: remove the "cpu_clk" from the GXBB and GXL driver
Martin Blumenstingl [Thu, 4 May 2017 18:19:20 +0000 (20:19 +0200)]
clk: meson: gxbb: remove the "cpu_clk" from the GXBB and GXL driver

It seems that the "cpu_clk" was carried over from the meson8b clock
controller driver. On Meson GX (GXBB/GXL/GXM) the registers which are
used by the cpu_clk have a different purpose (in other words: they don't
control the CPU clock anymore). HHI_SYS_CPU_CLK_CNTL1 bits 31:24 are
reserved according to the public S905 datasheet, while bit 23 is the
"A53_trace_clk_DIS" gate (which according to the datasheet should only
be used in case a silicon bug is discovered) and bits 22:20 are a
divider (A53_trace_clk). The meson clk-cpu code however expects that
bits 28:20 are reserved for a divider (according to the public S805
datasheet this "SCALE_DIV: This value represents an N+1 divider of the
input clock.").

The CPU clock on Meson GX SoCs is provided by the SCPI DVFS clock
driver instead. Two examples from a Meson GXL S905X SoC:
- vcpu (SCPI DVFS clock 0) rate: 1000000000 / cpu_clk rate: 708000000
- vcpu (SCPI DVFS clock 0) rate: 1512000000 / cpu_clk rate: 708000000

Unfortunately the CLKID_CPUCLK was already exported (but is currently
not used) to DT. Due to the removal of this clock definition there is
now a hole in the clk_hw_onecell_data (which is not a problem because
this case is already handled in gxbb_clkc_probe).

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
7 years agoclk: meson-gxbb: un-export the CPU clock
Martin Blumenstingl [Thu, 4 May 2017 18:19:19 +0000 (20:19 +0200)]
clk: meson-gxbb: un-export the CPU clock

The CPU clock defined in the Meson GX clock driver is actually a
left-over from the Meson8b clock controller. Un-export the clock so we
can remove it from the driver.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
7 years agoclk: meson-gxbb: expose UART clocks
Helmut Klein [Fri, 31 Mar 2017 16:54:34 +0000 (18:54 +0200)]
clk: meson-gxbb: expose UART clocks

Expose the clock ids of the three none AO uarts to the dt-bindings

Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Helmut Klein <hgkr.klein@gmail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
[tidy the commit message to match similar change]
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
7 years agoclk: meson-gxbb: expose SPICC gate
Neil Armstrong [Thu, 20 Apr 2017 11:59:10 +0000 (13:59 +0200)]
clk: meson-gxbb: expose SPICC gate

Expose the SPICC gate clock to enable the SPICC controller.

Acked-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
[tidy commit message to match similar changes]
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>