Deepak Sharma [Tue, 22 May 2018 22:31:23 +0000 (15:31 -0700)]
drm/amdgpu: Use GTT for dumb buffer if sg display enabled (v2)
When vram size <= THRESHOLD(256M) lets use GTT for dumb buffer
allocation. As SG will be enabled with vram size <= 256M
scan out will not be an issue.
v2: Use amdgpu_display_supported_domains to get supported domain.
Signed-off-by: Deepak Sharma <Deepak.Sharma@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nayan Deshmukh [Fri, 25 May 2018 04:45:46 +0000 (10:15 +0530)]
drm/scheduler: fix a corner case in dependency optimization
When checking for a dependency fence for belonging to the same entity
compare it with scheduled as well finished fence. Earlier we were only
comparing it with the scheduled fence.
Signed-off-by: Nayan Deshmukh <nayan26deshmukh@gmail.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Fixes: 9b4c412a654c ("drm/amdgpu: Add static CG control for VCN on RV") Signed-off-by: kbuild test robot <fengguang.wu@intel.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This is required so we use the correct minimum clocks for Vega. Without
this pplib will never be able to enter the lowest clock states.
Signed-off-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
David Francis [Thu, 24 May 2018 14:40:12 +0000 (10:40 -0400)]
drm/amd/display: Remove use of division operator for long longs
In fixed31_32.h, in dc_fixpt_shl,'/' was used for division of one long
long int by another long long int. As there is no inbuilt long long
int division function in c, gcc inserted its own. However, gcc does not
link the library that contains this function. To avoid this, use
bitwise operators instead of /
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: David Francis <David.Francis@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Shaoyun Liu [Tue, 22 May 2018 15:45:41 +0000 (11:45 -0400)]
drm/amdgpu: Update GFX info structure to match what vega20 used
Update to the latest version from the vbios team.
Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Emily Deng [Wed, 23 May 2018 07:53:03 +0000 (15:53 +0800)]
drm/sched: add rcu_barrier after entity fini
To free the fence from the amdgpu_fence_slab, need twice call_rcu, to avoid
the amdgpu_fence_slab_fini call kmem_cache_destroy(amdgpu_fence_slab) before
kmem_cache_free(amdgpu_fence_slab, fence), add rcu_barrier after drm_sched_entity_fini.
The kmem_cache_free(amdgpu_fence_slab, fence)'s call trace as below:
1.drm_sched_entity_fini ->
drm_sched_entity_cleanup ->
dma_fence_put(entity->last_scheduled) ->
drm_sched_fence_release_finished ->
drm_sched_fence_release_scheduled ->
call_rcu(&fence->finished.rcu, drm_sched_fence_free)
v2:put the barrier before the kmem_cache_destroy
v3:put the dma_fence_put(fence->parent) before call_rcu in
drm_sched_fence_release_scheduled
Signed-off-by: Emily Deng <Emily.Deng@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Thu, 19 Apr 2018 13:01:12 +0000 (15:01 +0200)]
drm/amdgpu: move VM BOs on LRU again
Move all BOs belonging to a VM on the LRU with every submission.
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Thu, 19 Apr 2018 08:56:02 +0000 (10:56 +0200)]
drm/amdgpu: rework VM state machine lock handling v2
Only the moved state needs a separate spin lock protection. All other
states are protected by reserving the VM anyway.
v2: fix some more incorrect cases
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 10 May 2018 20:15:12 +0000 (15:15 -0500)]
drm/amdgpu/gmc9: disable partial wr rmw if ECC is not enabled
The vbios mistakenly sets this bit on some boards without ECC.
This can lead to reduced performance in some workloads. Disable
the bit if the board does not have ECC.
Remove calls to suspend/resume atomic helpers from amdgpu_device_gpu_recover. (v2)
First of all it's already being called from the display code from amd_ip_funcs.suspend/resume hooks.
Second of all, the place in amdgpu_device_gpu_recover it's being called is wrong for GPU stalls since
it is called BEFORE we cancel and force completion of all in flight jobs which were not yet processed.
So, as Bas pointed in the ticket we will try to wait for fence in amdgpu_pm_compute_clocks but the pipe
is hanged so we end up in deadlock.
v2: remove unused variable
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106500 Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dave Airlie [Tue, 22 May 2018 00:45:42 +0000 (10:45 +1000)]
Merge tag 'drm/tegra/for-4.18-rc1' of git://anongit.freedesktop.org/tegra/linux into drm-next
drm/tegra: Changes for v4.18-rc1
This set enables IOMMU support in the gr2d and gr3d drivers and adds
support for the zpos property on older Tegra generations. It also
enables scaling filters and incorporates some rework to eliminate a
private wrapper around struct drm_framebuffer.
The remainder is mostly a random assortment of fixes and cleanups, as
well as some preparatory work for destaging the userspace ABI, which
is almost ready and is targetted for v4.19-rc1.
Dave Airlie [Tue, 22 May 2018 00:37:07 +0000 (10:37 +1000)]
Merge branch 'etnaviv/next' of https://git.pengutronix.de/git/lst/linux into drm-next
So what we have for this cycle is a bit of spring cleaning with removal
of unused register logging code and getting rid of the license text in
favor of SPDX, a few smaller MMU handling improvements and a timeout
calculation change, fixing premature fence wait timeouts after 50 days
of uptime.
Thierry Reding [Wed, 16 May 2018 14:43:11 +0000 (16:43 +0200)]
drm/tegra: Add kerneldoc for UAPI
Document the userspace ABI with kerneldoc to provide some information on
how to use it.
v3:
- reword description of arrays and array lengths
v2:
- keep GEM object creation flags for ABI compatibility
- fix typo in struct drm_tegra_syncpt_incr kerneldoc
- fix typos in struct drm_tegra_submit kerneldoc
- reworded some descriptions as suggested
Leo Liu [Thu, 17 May 2018 17:54:21 +0000 (13:54 -0400)]
drm/amdgpu: fix insert nop for UVD4.2 ring
NO_OP register should be writen to 0
Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Liu [Thu, 17 May 2018 17:52:00 +0000 (13:52 -0400)]
drm/amdgpu: fix insert nop for UVD5 ring
NO_OP register should be writen to 0
Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Liu [Thu, 17 May 2018 17:44:28 +0000 (13:44 -0400)]
drm/amdgpu: fix insert nop for UVD6 ring
NO_OP register should be writen to 0
Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Liu [Thu, 17 May 2018 17:37:50 +0000 (13:37 -0400)]
drm/amdgpu: fix insert nop for UVD7 ring
NO_OP register should be writen to 0
Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Liu [Thu, 17 May 2018 17:31:49 +0000 (13:31 -0400)]
drm/amdgpu: fix insert nop for VCN decode ring
NO_OP register should be writen to 0
Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Anthony Koo [Sat, 28 Apr 2018 00:50:07 +0000 (20:50 -0400)]
drm/amd/display: fix memory leaks
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Eric Bernstein [Thu, 26 Apr 2018 18:06:00 +0000 (14:06 -0400)]
drm/amd/display: DCN1 link encoder
Create DCN1 link encoder files and update AUX and HPD register access.
Signed-off-by: Eric Bernstein <eric.bernstein@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nikola Cornij [Fri, 27 Apr 2018 21:26:25 +0000 (17:26 -0400)]
drm/amd/display: Clear underflow status for debug purposes
We want to keep underflow sticky bit on for the longevity tests outside
of test environment. For debug purposes it is, however, useful to clear
underflow status after the test that caused it so that the following
tests are not affected. This change fullfils both requirements by clearing
the underflow only from within Windows or Diags test environment.
Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Anthony Koo [Fri, 27 Apr 2018 19:23:23 +0000 (15:23 -0400)]
drm/amd/display: fix bug with index check
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Anthony Koo [Thu, 26 Apr 2018 14:03:44 +0000 (10:03 -0400)]
drm/amd/display: Add fullscreen transitions to log
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jun Lei [Thu, 26 Apr 2018 14:24:25 +0000 (10:24 -0400)]
drm/amd/display: constify a few dc_surface_update fields
Signed-off-by: Jun Lei <Jun.Lei@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xingyue Tao [Thu, 19 Apr 2018 20:23:12 +0000 (16:23 -0400)]
drm/amd/display: Only limit VSR downscaling when actually downscaling
Signed-off-by: Xingyue Tao <xingyue.tao@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Anthony Koo [Tue, 24 Apr 2018 19:36:27 +0000 (15:36 -0400)]
drm/amd/display: use macro for logs
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nikola Cornij [Mon, 23 Apr 2018 19:55:36 +0000 (15:55 -0400)]
drm/amd/display: Log DTN only after the atomic commit in Diag
Also print HUBP info only if pipe enabled. This fixes having different
DTN logs for different test sequences.
Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yue Hin Lau [Wed, 18 Apr 2018 20:07:04 +0000 (16:07 -0400)]
drm/amd/display: disable mpo if brightness adjusted
Signed-off-by: Yue Hin Lau <Yuehin.Lau@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xingyue Tao [Thu, 19 Apr 2018 20:23:12 +0000 (16:23 -0400)]
drm/amd/display: Add dc cap to restrict VSR downscaling src size
- Adds int max_downscale_src_width in dc struct
- Checks and does not support if downscale size is more than 4k (width > 3840)
Signed-off-by: Xingyue Tao <xingyue.tao@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Eric Yang <eric.yang2@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Eric Bernstein <eric.bernstein@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Charlene Liu [Wed, 18 Apr 2018 18:31:41 +0000 (14:31 -0400)]
drm/amd/display: underflow/blankscreen recovery
[Description]
for any reason, if driver detects HUBP underflow,
if a debug option enabled to enable recovery.
it will kick in a sequence of recovery.
Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 17 May 2018 17:45:52 +0000 (12:45 -0500)]
drm/amdgpu: Take uvd encode rings into account in idle work (v2)
Take the encode rings into account in the idle work handler.
v2: fix typo: s/num_uvd_inst/num_enc_rings/
Reviewed-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 17 May 2018 17:33:34 +0000 (12:33 -0500)]
drm/amdgpu: count fences from all uvd instances in idle handler
Current multi-UVD hardware uses a single clock and power source
so handle all instances in the idle handler.
Reviewed-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nayan Deshmukh [Wed, 16 May 2018 13:24:18 +0000 (18:54 +0530)]
drm/scheduler: fix function name prefix in comments
That got missed while moving the files outside of amdgpu.
Signed-off-by: Nayan Deshmukh <nayan26deshmukh@gmail.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tom St Denis [Wed, 9 May 2018 18:22:29 +0000 (14:22 -0400)]
drm/amd/amdgpu: Code comments for the amdgpu_ttm.c driver. (v2)
NFC just comments.
(v2): Updated based on feedback from Alex Deucher.
Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dan Carpenter [Thu, 17 May 2018 12:56:05 +0000 (15:56 +0300)]
drm/amd/pp: missing curly braces in smu7_enable_sclk_mclk_dpm()
We added some more lines of code to this if statement but forgot to add
curly braces.
Fixes: 0c24e7ef233b ("drm/amd/powerplay: add specific changes for VEGAM in smu7_hwmgr.c") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Wed, 16 May 2018 13:39:58 +0000 (08:39 -0500)]
drm/amdgpu/display: remove VEGAM config option
Leftover from bringup. No need to keep it around for
upstream.
Reviewed-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This spinlock is superfluous, any call to drm_sched_entity_push_job
should already be under a lock together with matching drm_sched_job_init
to match the order of insertion into queue with job's fence seqence
number.
Christian König [Thu, 19 Apr 2018 07:57:21 +0000 (09:57 +0200)]
drm/amdgpu: remove unused member
This lock isn't used any more.
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Skip drm_sched_entity related ops for KIQ ring.
Following change 75fbed2 we never initialize or use the GPU
scheduler for KIQ and hence we need to skip KIQ ring when iterating
amdgpu_ctx's scheduler entites.
Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Feifei Xu [Mon, 22 Jan 2018 11:08:33 +0000 (19:08 +0800)]
drm/amdgpu: Add vega20 pci ids
Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
James Zhu [Mon, 30 Apr 2018 12:43:12 +0000 (08:43 -0400)]
drm/amdgpu/vg20:Enable UVD/VCE for Vega20
Vega20 ucode load type is set to AMDGPU_FW_LOAD_DIRECT for default.
So UVD/VCE needn't PSP IP block up. UVD/VCE for Vega20 can be enabled
at this moment.
Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
James Zhu [Tue, 24 Apr 2018 01:00:58 +0000 (21:00 -0400)]
drm/amdgpu/vg20:Enable 2nd instance queue maping for uvd 7.2
Enable 2nd instance uvd queue maping for uvd 7.2. For user, only one UVD
instance presents. there is two rings for uvd decode, and
4 rings for uvd encode.
Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
James Zhu [Tue, 24 Apr 2018 00:56:01 +0000 (20:56 -0400)]
drm/amdgpu/vg20:Enable the 2nd instance IRQ for uvd 7.2
For Vega20, the 2nd instance uvd IRQ using different client id.
Enable the 2nd instance IRQ for uvd 7.2
Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
James Zhu [Tue, 24 Apr 2018 00:49:28 +0000 (20:49 -0400)]
drm/amdgpu/vg20:Add IH client ID for the 2nd UVD
For Vega20, there are two UVD hardware. Need add
the 2nd IH client ID for the 2nd UVD Hardware.
Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
James Zhu [Fri, 11 May 2018 18:56:44 +0000 (13:56 -0500)]
drm/amdgpu/vg20:Enable the 2nd instance for uvd
For Vega20, set num of uvd instance to 2, to enble 2nd instance.
The IB test build-in registers need update for vega20 2nd instance.
Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
James Zhu [Mon, 23 Apr 2018 23:11:46 +0000 (19:11 -0400)]
drm/amdgpu/vg20:increase 3 rings for AMDGPU_MAX_RINGS
For Vega20, there are two UVD Hardware. One more UVD hardware
adds one decode ring and two encode rings. So AMDGPU_MAX_RINGS
need increase by 3.
Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
James Zhu [Tue, 15 May 2018 19:31:24 +0000 (14:31 -0500)]
drm/amdgpu/vg20:Restruct uvd.inst to support multiple instances
Vega20 has dual-UVD. Need add multiple instances support for uvd.
Restruct uvd.inst, using uvd.inst[0] to replace uvd.inst->.
Repurpose amdgpu_ring::me for instance index, and initialize to 0.
There are no any logical changes here.
Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
James Zhu [Tue, 15 May 2018 19:25:46 +0000 (14:25 -0500)]
drm/amdgpu/vg20:Restruct uvd to support multiple uvds
Vega20 has dual-UVD. Need Restruct amdgpu_device::uvd to support
multiple uvds. There are no any logical changes here.
Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Mon, 26 Mar 2018 03:43:04 +0000 (11:43 +0800)]
drm/amd/powerplay: update vega20 cg flags (v2)
v2: remove duplicate flag.
Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>