Imre Deak [Fri, 12 May 2023 19:55:13 +0000 (22:55 +0300)]
drm/i915/tc: Reset TypeC PHYs left enabled in DP-alt mode after the sink disconnects
If the output on a DP-alt link with its sink disconnected is kept
enabled for too long (about 20 sec), then some IOM/TCSS firmware timeout
will cause havoc on the PCI bus, at least for other GFX devices on it
which will stop powering up. Since user space is not guaranteed to do a
disabling modeset in time, switch such disconnected but active links to
TBT mode - which is without such shortcomings - with a 2 second delay.
If the above condition is detected already during the driver load/system
resume sanitization step disable the output instead, as at that point no
user space or kernel client depends on a consistent output state yet and
because subsequent atomic modeset on such connectors - without the
actual sink capabilities available - can fail.
An active/disconnected port as above will also block the HPD status of
other active/disconnected ports to get updated (stuck in the connected
state), until the former port is disabled, its PHY is disconnected and
a ~10 ms delay has elapsed. This means the link state for all TypeC
ports/CRTCs must be rechecked after a CRTC is disabled due to the above
reason. For this disconnect the PHY synchronously after the CRTC/port is
disabled and recheck all CRTCs for the above condition whenever such a
port is disabled.
To account for a race condition during driver loading where the sink is
disconnected after the above sanitization step and before the HPD
interrupts get enabled, do an explicit check/link reset if needed from
the encoder's late_register hook, which is called after the HPD
interrupts are enabled already.
v2:
- Handle an active/disconnected port blocking the HPD state update of
another active/disconnected port.
- Cancel the delayed work resetting the link also from the encoder
enable/suspend/shutdown hooks.
- Rebase on the earlier intel_modeset_lock_ctx_retry() addition,
fixing here the missed atomic state reset in case of a retry.
- Fix handling of an error return from intel_atomic_get_crtc_state().
- Recheck if the port needs to be reset after all the atomic state
is locked and async commits are waited on.
v3:
- Add intel_crtc_needs_link_reset(), instead of open-coding it,
keep intel_crtc_has_encoders(). (Ville)
- Fix state dumping and use a bitmask to track disabled CRTCs in
intel_sanitize_all_crtcs(). (Ville)
- Set internal in intel_atomic_state right after allocating it.
(Ville)
- Recheck all CRTCs (not yet force-disabled) after a CRTC is
force-disabled for any reason (not only due to a link state)
in intel_sanitize_all_crtcs().
- Reduce delay after CRTC disabling to 20ms, and use the simpler
msleep().
- Clarify code comment about HPD behaviour in
intel_sanitize_all_crtcs().
- Move all the TC link reset logic to intel_tc.c .
- Cancel the link reset work synchronously during system suspend,
driver unload and shutdown.
v4:
- Rebased on previous patch, which allows calling the TC port
suspend/cleanup handlers without modeset locks held; remove the
display driver suspended assert from the link reset work
accordingly.
v5: (Ville)
- Remove reset work canceling from intel_ddi_pre_pll_enable().
- Track a crtc vs. pipe mask in intel_sanitize_all_crtcs().
- Add reset_link_commit() to clarify the
intel_modeset_lock_ctx_retry loop.
Cc: Kai-Heng Feng <kai.heng.feng@canonical.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Tested-by: Kai-Heng Feng <kai.heng.feng@canonical.com> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5860 Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230512195513.2699-2-imre.deak@intel.com
Imre Deak [Fri, 12 May 2023 19:55:12 +0000 (22:55 +0300)]
drm/i915/tc: Call TypeC port flush_work/cleanup without modeset locks held
Call the TypeC port flush_work and cleanup handlers without the modeset
locks held. These don't require the locks, as the work takes - as it
should be able to at any point in time - any locks it needs and by the
time cleanup is called and after cleanup returns the encoder is not in
use.
This is required by the next patch canceling a TypeC port work
synchronously during encoder suspend and shutdown, where the work can
take modeset locks as well, hence the canceling must be done without
holding the locks.
I also considered moving the modeset locking down to each encoder
suspend()/shutdown() hook instead, however locking the full modeset
state for each encoder separately would be odd, and the bigger change -
affecting all encoders - is beyond the scope of this patchset.
v2:
- Add a TODO: comment to remove modeset locks if no encoder depends
on this. (Ville)
adding the helper to i915. I find this approach preferrable than
open-coding the corresponding steps (fixed for me an atomic
state reset during a DEADLK retry, which I missed in the open-coded
version) and also better than the existing
DRM_MODESET_LOCK_ALL_BEGIN/END macros for the reasons described in the
above original patchset.
This change takes the helper into use only for atomic commits during DDI
hotplug handling, as a preparation for a follow-up patch adding a
similar commit started from the same spot. Other places doing a
driver-internal atomic commit is to be converted by a follow-up
patchset.
Imre Deak [Wed, 10 May 2023 10:31:27 +0000 (13:31 +0300)]
drm/i915/dp: Prevent link training fallback on disconnected port
Prevent downgrading the link training maximum lane count/rate if the
sink is disconnected - and so the link training failure is expected. In
such cases modeset failures due to the reduced max link params would be
just confusing for user space (instead of which the correct thing it
should act on is the sink disconnect signaled by a hotplug event,
requiring a disabling modeset).
v2:
- Check the actual HPD state to handle the forced connector state case.
(Vinod)
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Vinod Govindapillai <vinod.govindapillai@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> (v1) Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230510103131.1618266-11-imre.deak@intel.com
Imre Deak [Wed, 10 May 2023 10:31:26 +0000 (13:31 +0300)]
drm/i915/dp: Convert link training error to debug message on disconnected sink
If a sink is disconnected it's expected that link training actions will
fail on it, so downgrade the error messages about such actions to be a
debug message. Such - expected - link training failures are more
frequent after a follow up patch, after which an active TypeC link is
reset after the sink is disconnected which also involves a link
training.
v2:
- Check the actual HPD state to handle the forced connector state case.
(Vinod)
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Vinod Govindapillai <vinod.govindapillai@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> (v1) Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230510103131.1618266-10-imre.deak@intel.com
Imre Deak [Wed, 10 May 2023 10:31:25 +0000 (13:31 +0300)]
drm/i915/dp: Add link training debug and error printing helpers
Add functions for printing link training debug and error messages, both
to prepare for the next patch, which downgrades an error to a debug
message if the sink is disconnected and to remove some code duplication.
v2: (Ville)
- Always print the connector prefix.
- Preserve the drm_dbg_kms() debug category.
v3:
- Keep printing the name of functions calling the helpers. (Jani)
Imre Deak [Wed, 10 May 2023 10:31:24 +0000 (13:31 +0300)]
drm/i915: Add support for disabling any CRTCs during HW readout/sanitization
During HW readout/sanitization CRTCs can be disabled only if they don't
have an attached encoder (and so the encoder disable hooks don't need to
be called). An upcoming patch will need to disable CRTCs also with an
attached encoder, so add support for this.
For bigjoiner configs the encoder disabling hooks require the slave CRTC
states, so add these too to the atomic state. Since the connector atomic
state is already up-to-date when the CRTC is disabled the connector
state needs to be updated (reset) after the CRTC is disabled, make this
so. Follow the proper order of disabling first all bigjoiner slaves,
then any port synced CRTC slaves followed by the CRTC originally
requested to be disabled.
v2:
- Fix calculating the bigjoiner_masters mask in a port sync config,
(Ville)
- Keep _noatomic suffix in intel_crtc_disable_noatomic(). (Ville)
- Rebase on full CRTC state reset in this patchset, not requiring
resetting the bigjoiner state separately and (instead) resetting
the full atomic CRTC and related global state after all linked
pipes got disabled.
- Disable portsync slaves before a portsync master.
- Disable a portsync master if a linked portsync slave is disabled.
v3: (Ville)
- Use s/u32/u8 for transcoder and pipe masks.
- Use is_power_of_2() instead of hweight()==1.
Imre Deak [Wed, 10 May 2023 10:31:22 +0000 (13:31 +0300)]
drm/i915: Separate intel_crtc_disable_noatomic_begin/complete()
Split calling the CRTC/encoder disabling hooks and updating the CRTC and
DPLL object states from updating the CRTC and atomic state and other
global state (BW, CDCLK, DBUF) into separate functions. When disabling a
bigjoiner configuration the latter step can be done only after all the
linked pipes are disabled, so this change prepares for that.
Imre Deak [Wed, 10 May 2023 10:31:21 +0000 (13:31 +0300)]
drm/i915: Update connector atomic state before crtc sanitize-disabling
During HW state readout/sanitization an up-to-date connector atomic
state will be required by a follow-up patch, which can disable CRTCs
with an encoder (and calling the correct encoder hooks happens via the
connector atomic state encoder pointer). So update the connector state
already before the CRTC sanitize/disable step. For now this doesn't make
a difference, since intel_modeset_update_connector_atomic_state() will
update/enable the atomic state only for connectors that have an enabled
encoder/CRTC. Such CRTCs/encoders will not be affected by
intel_sanitize_crtc().
v2: Add comment about why the connector state needs to be up-to-date.
Imre Deak [Wed, 10 May 2023 10:31:20 +0000 (13:31 +0300)]
drm/i915: Make the CRTC state consistent during sanitize-disabling
Make sure that the CRTC state is reset correctly, as expected after
disabling the CRTC.
In particular this change will:
- Zero all the CSC blob pointers after intel_crtc_free_hw_state()
has freed them.
- Zero the shared DPLL and port PLL pointers and clear the
corresponding CRTC reference flag in the PLL state.
- Reset all the transcoder and pipe fields.
v2:
- Reset fully the CRTC state. (Ville)
- Clear pipe active flags in the DPLL state.
v3:
- Clear only the CRTC reference flag and add a helper for this.
(Ville)
v4:
- Rebased on previous patch, adding
intel_unreference_shared_dpll_crtc() separately. (Ville)
Imre Deak [Wed, 10 May 2023 10:31:18 +0000 (13:31 +0300)]
drm/i915: Fix PIPEDMC disabling for a bigjoiner configuration
For a bigjoiner configuration display->crtc_disable() will be called
first for the slave CRTCs and then for the master CRTC. However slave
CRTCs will be actually disabled only after the master CRTC is disabled
(from the encoder disable hooks called with the master CRTC state).
Hence the slave PIPEDMCs can be disabled only after the master CRTC is
disabled, make this so.
intel_encoders_post_pll_disable() must be called only for the master
CRTC, as for the other two encoder disable hooks. While at it fix this
up as well. This didn't cause a problem, since
intel_encoders_post_pll_disable() will call the corresponding hook only
for an encoder/connector connected to the given CRTC, however slave
CRTCs will have no associated encoder/connector.
Fixes: 3af2ff0840be ("drm/i915: Enable a PIPEDMC whenever its corresponding pipe is enabled") Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230510103131.1618266-2-imre.deak@intel.com
Suraj Kandpal [Mon, 15 May 2023 10:32:24 +0000 (16:02 +0530)]
drm/i915/hdcp: Fix modeset locking issue in hdcp mst
Since topology state is being added to drm_atomic_state now all
drm_modeset_lock required are being taken from core. This raises
an issue when we try to loop over connector and assign vcpi id to
our streams as we did not have atomic state to derive acquire_ctx
from. We fill in stream info if dpmst encoder is found before
enabling hdcp. intel_hdcp_required_stream will be broken which
will only set the content type.
--v2
-move prepare streams to beginning of intel_hdcp_enable to avoid
checking of mst encoder twice [Ankit]
--v3
-break intel_required_content_stream to two part and set the stream_id
at the beginning [Ankit]
--v4
-change return types for intel_hdcp_prepare_stream and
intel_hdcp_required content_stream [Ankit]
-rename intel_hdcp_set_content_stream to
intel_hdcp_set_stream [Ankit]
-place intel_hdcp_set_streams above caller [Ankit]
Remove enforce_type0 check outside the loop since it
does not make sense to keep it there as we use the same
digport and continue checking it again and again
Jani Nikula [Mon, 15 May 2023 10:17:37 +0000 (13:17 +0300)]
drm/i915/irq: split out hotplug irq handling
Split hotplug irq handling out of i915_irq.[ch] into
display/intel_hotplug_irq.[ch].
The line between the new intel_hotplug_irq.[ch] and the existing
intel_hotplug.[ch] needs further clarification, but the first step is to
move the stuff out of i915_irq.[ch].
Jani Nikula [Thu, 11 May 2023 15:21:53 +0000 (18:21 +0300)]
drm/i915/gt: drop dependency on VLV_DISPLAY_BASE
CHV_FUSE_GT (0x182168) is purely about GT fuses, therefore belongs in
intel_gt_regs.h, is in the gcfgmmio unit, but is technically in the VLV
display base area.
Add VLV_GUNIT_BASE to drop dependency on VLV_DISPLAY_BASE and thus
display/intel_display_reg_defs.h in intel_gt_regs.h.
Ville Syrjälä [Tue, 9 May 2023 16:02:05 +0000 (19:02 +0300)]
drm/i915: Flip VBT DDC pin maps around
Swap the roles of the index vs. value for the VBT DDC pin
mapping tables. This is not strictly necessary for DDC pins
but it will make this work exactly like the AUX CH mapping
tables where the role reversal is necessary (or at least makes
things easier). Consistency is good.
Ville Syrjälä [Tue, 9 May 2023 16:02:04 +0000 (19:02 +0300)]
drm/i915: Split map_aux_ch() into per-platform arrays
The big switch+if statement mess in map_aux_ch() is
illegible. Split up into cleaner per-platform arrays
like we already have for the gmbus pins.
We use enum aux_ch as the index and the VBT thing as
the value. Slightly non-intuitive perhaps but if we
did it the other way around we'd have problems with
AUX_CH_A being zero, and thus any non-populated
element would look like AUX_CH_A.
v2: flip the index vs. value around
TODO: Didn't bother with the platform variants beyond the
ones that really need remapping, which means if the
VBT is bogus we end up with a nonexistent aux ch.
Might be nice to check this a bit better.
Yet another bitmask in device info?
Jani Nikula [Thu, 4 May 2023 10:35:08 +0000 (13:35 +0300)]
drm/i915: taint kernel when force probing unsupported devices
For development and testing purposes, the i915.force_probe module
parameter and DRM_I915_FORCE_PROBE kconfig option allow probing of
devices that aren't supported by the driver.
The i915.force_probe module parameter is "unsafe" and setting it taints
the kernel. However, using the kconfig option does not.
Always taint the kernel when force probing a device that is not
supported.
v2: Drop "depends on EXPERT" to avoid build breakage (kernel test robot)
Fixes: 7ef5ef5cdead ("drm/i915: add force_probe module parameter to replace alpha_support") Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Dave Airlie <airlied@gmail.com> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230504103508.1818540-1-jani.nikula@intel.com
drm/i915: Fix wrong condition in bxt_set_cdclk for DG2
By my own mistake, after adding !IS_DG2 into wrong branch,
bxt_set_cdclk started to execute code intended for platforms
gen < 11, which is wrong.
Move IS_DG2 check to better place.
Ville Syrjälä [Mon, 7 Nov 2022 19:46:04 +0000 (21:46 +0200)]
drm/i915: Pick one HDMI port for infoframe/audio transmission on g4x
On g4x the hardware has only one audio/video DIP block. Thus
only one HDMI port can transmit audio/infoframes at a time.
Currently we pretend that multiple ports can do it at the same
time, but that doesn't actually work for two reasons:
- the state of the single hw block will get clobbered by
the multiple ports, leading to state checker failures
- the hardware will automagically disable audio/infoframe
transmission when enabled on multiple ports
To fix this let's allow only one of the ports to transmit
audio/infoframes at a time. We'll just go over all the HDMI
ports and pick the first one that is otherwise capable of
audio/infoframes. Further HDMI ports will be treated as if
they had a DVI sink connected.
In order to compute this consistently we'll also need to
always add all HDMI ports to the atomic state.
Ville Syrjälä [Mon, 7 Nov 2022 19:46:03 +0000 (21:46 +0200)]
drm/i915: Move has_hdmi_sink out from intel_hdmi_compute_config()
We'll be wanting to compute has_hdmi_sink a bit differently
for some platforms. To that end compute it in the encoder
.compute_config_hook() before we call intel_hdmi_compute_config().
intel_hdmi_compute_has_hdmi_sink() will do the basic lifting
beyond any platform specific stuff.
drm/i915/display: Use sink_format instead of ycbcr420_output flag
Start passing the sink_format, to all functions that take a bool
ycbcr420_output as parameter. This will make the functions generic,
and will serve as a slight step towards 4:2:2 support later.
v2: Rebased.
v3: Correct the checks in places concerned with pipe output. (Ville)
Other minor styling and refactoring fixes, as suggested by Ville.
drm/i915/dp: Configure PCON for conversion of output_format to YCbCr444
Handle the case with DP to HDMI PCON, where sink_format is set to YCbCr444.
In that case PCON is required to be configured to convert from given
output_format to YCbCR444.
v2: Drop drm_WARN for invalid case, let MISSING_CASE catch it. (Ville)
drm/i915/dp: Replace intel_dp.dfp members with the new crtc_state sink_format
The decision to use DFP output format conversion capabilities should be
during compute_config phase.
This patch uses the members of intel_dp->dfp to only store the
format conversion capabilities of the DP device and uses the crtc_state
sink_format member, to program the protocol-converter for
colorspace/format conversion.
v2: Use sink_format to determine the color conversion config for the
pcon (Ville).
v3: Fix typo: missing 'break' in switch case (lkp kernel test robot).
v4: Add helper to check if DP supports YCBCR420.
v5: Simplify logic for computing output_format, based on the given
sink_format. (Ville).
Added scaler constraint for YCbCr420 output.
v6: Split the patch for Scaler constraint for Ycbcr420.
v7: Simplify the policy for selecting output_format:
Always try for RGB first, followed by YCBCR444, and finally by YCBCR420.
v8: Removed redundant comments, minor refactoring. (Ville)
v9: Added member for ycbcr420 passthrough cap, fixed minor issues. (Ville)
drm/i915/display: Add new member to configure PCON color conversion
The decision to use DFP output format conversion capabilities should be
during compute_config phase.
This patch adds new member to crtc_state to represent the final
output_format to the sink. In case of a DFP this can be different than
the output_format, as per the format conversion done via the PCON.
This will help to store only the format conversion capabilities of the
DP device in intel_dp->dfp, and use crtc_state to compute and store the
configuration for color/format conversion for a given mode.
v2: modified the new member to crtc_state to represent the final
output_format that eaches the sink, after possible conversion by
PCON kind of devices. (Ville)
v3: Addressed comments from Ville:
-Added comments to clarify difference between sink_format and
output_format.
-Corrected the order of setting sink_format and output_format.
-Added readout for sink_format in get_pipe_config hooks.
v4: Set sink_format for intel_sdvo too. (Ville)
v5: Rebased.
v6: Fixed condition to go for YCbCr420 format for dp and hdmi. (Ville)
v7: Fix the condition to set sink_format for HDMI.
Set hdmi output_format simply as sink_format. (Ville)
drm_dp_dsc_sink_max_slice_count() may return 0 if something goes
wrong on the part of the DSC sink and its DPCD register. This null
value may be later used as a divisor in intel_dsc_compute_params(),
which will lead to an error.
In the unlikely event that this issue occurs, fix it by testing the
return value of drm_dp_dsc_sink_max_slice_count() against zero.
Found by Linux Verification Center (linuxtesting.org) with static
analysis tool SVACE.
drm/i915: Fix NULL ptr deref by checking new_crtc_state
intel_atomic_get_new_crtc_state can return NULL, unless crtc state wasn't
obtained previously with intel_atomic_get_crtc_state, so we must check it
for NULLness here, just as in many other places, where we can't guarantee
that intel_atomic_get_crtc_state was called.
We are currently getting NULL ptr deref because of that, so this fix was
confirmed to help.
drm/i915: Communicate display power demands to pcode
Display to communicate display pipe count/CDCLK/voltage configuration
to Pcode for more accurate power accounting for DG2.
Existing sequence is only sending the voltage value to the Pcode.
Adding new sequence with current cdclk associate with voltage value masking.
Adding pcode request when any pipe power well will disable or enable.
v2: - Make intel_cdclk_need_serialize static to make CI compiler happy.
v3: - Removed redundant return(Jani Nikula)
- Changed intel_cdclk_power_usage_to_pcode_(pre|post)_notification to be
static and also naming to intel_cdclk_pcode_(pre|post)_notify(Jani Nikula)
- Changed u8 to be u16 for cdclk parameter in intel_pcode_notify function,
as according to BSpec it requires 10 bits(Jani Nikula)
- Replaced dev_priv's with i915's(Jani Nikula)
- Simplified expression in intel_cdclk_need_serialize(Jani Nikula)
- Removed redundant kernel-doc and indentation(Jani Nikula)
v4: - Fixed some checkpatch warnings
v5: - According to HW team comments that change should affect only DG2,
fix correspodent platform check to account this.
v6: - Added one more missing IS_DG2 check(Vinod Govindapillai)
Ville Syrjälä [Wed, 26 Apr 2023 13:50:17 +0000 (16:50 +0300)]
drm/i915: Define bitmasks for skl+ scaler window pos/size
Define and use the bitmasks for the x/y components
of the skl+ scaler window pos/size registers.
We stick to the full 16 bits mask here even though the
hardware limits are actually lower. The current (ADL)
hardware maximums are in fact: 14 bits for X size, 13 bits
for X pos, 13 bits for Y size/pos. Yes, that is correct,
X pos has less bits than the X size for some reason. But
that doesn't actually matter for now as we don't currently
even support such wide displays without the use of bigjoiner
(due to max plane width limit).
v2: Switch back to full 16bit masks since that's what
we use transcoder timign regs and PIPESRC as well
Ville Syrjälä [Wed, 26 Apr 2023 13:50:13 +0000 (16:50 +0300)]
drm/i915: Define bitmasks for ilk pfit window pos/size
Define and use the bitmasks for the x/y components
of the ilk+ panel filter window pos/size registers.
Note that we stick to the full 16 bit mask even though
the actual hardware limits are lower (and somewhat
platform dependent). BDW is actually limited to
13 bits horizontal and 12 bits vertical, with the high
bits being hardwired to zero. HSW should have the same
limits as BDW. And pre-HSW should be limited to 12bits
in both directions as that's already the limit of the
transcoder timing registers. Curiously on HSW and earlier
platforms all 16 bits can actually be set, but presumably
the hardware ignores the high bits.
v2: Switch back to full 16bit masks since that's what
we use transcoder timign regs and PIPESRC as well
Unlike previous platforms that used PORT_TX_DFLEXDPSP
for max_lane calculation, MTL uses only PORT_TX_DFLEXPA1
from which the max_lanes has to be calculated.
Bspec: 50235, 65380
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: Jose Roberto de Souza <jose.souza@intel.com> Signed-off-by: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230428095433.4109054-13-mika.kahola@intel.com
Imre Deak [Fri, 28 Apr 2023 09:54:31 +0000 (12:54 +0300)]
drm/i915/mtl: TypeC HPD live status query
The HPD live status for MTL has to be read from different set of
registers. MTL deserves a new function for this purpose
and cannot reuse the existing HPD live status detection
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230428095433.4109054-12-mika.kahola@intel.com
Mika Kahola [Fri, 28 Apr 2023 09:54:30 +0000 (12:54 +0300)]
drm/i915/mtl: Power up TCSS
Add register writes to enable powering up Type-C subsystem i.e. TCSS.
For MeteorLake we need to request TCSS to power up and check the TCSS
power state after 500 us.
In addition, for PICA we need to set/clear the Type-C PHY ownnership
bit when Type-C device is connected/disconnected.
Xe_LPD+ defines interrupt bits for only DDI ports in the DE Port
Interrupt registers. The bits for Type-C ports are defined in the PICA
interrupt registers.
Mika Kahola [Fri, 28 Apr 2023 09:54:22 +0000 (12:54 +0300)]
drm/i915/mtl: C20 HW readout
Create a table for C20 DP1.4, DP2.0 and HDMI2.1 rates.
The PLL settings are based on table, not for algorithmic alternative.
For DP 1.4 only MPLLB is in use.
Once register settings are done, we read back C20 HW state.
Mika Kahola [Fri, 28 Apr 2023 09:54:21 +0000 (12:54 +0300)]
drm/i915/mtl: C20 PLL programming
C20 phy PLL programming sequence for DP, DP2.0, HDMI2.x non-FRL and
HDMI2.x FRL. This enables C20 MPLLA and MPLLB programming sequence. add
4 lane support for c20.
v2: Add 6.48Gbps and 6.75Gbps modes for eDP (RK)
Fix lane check (RK)
Fix multiline commenting (Arun)
use usleep_range() instead of msleep() (Andi)
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Bhanuprakash Modem <bhanuprakash.modem@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com> Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230428095433.4109054-2-mika.kahola@intel.com
Hans de Goede [Tue, 25 Apr 2023 19:44:41 +0000 (21:44 +0200)]
drm/i915/dsi: Use unconditional msleep() instead of intel_dsi_msleep()
The intel_dsi_msleep() helper skips sleeping if the MIPI-sequences have
a version of 3 or newer and the panel is in vid-mode.
This is based on the big comment around line 730 which starts with
"Panel enable/disable sequences from the VBT spec.", where
the "v3 video mode seq" column does not have any wait t# entries.
Checking the Windows driver shows that it does always honor
the VBT delays independent of the version of the VBT sequences.
Commit 6fdb335f1c9c ("drm/i915/dsi: Use unconditional msleep for
the panel_on_delay when there is no reset-deassert MIPI-sequence")
switched to a direct msleep() instead of intel_dsi_msleep()
when there is no MIPI_SEQ_DEASSERT_RESET sequence, to fix
the panel on an Acer Aspire Switch 10 E SW3-016 not turning on.
And now testing on a Nextbook Ares 8A shows that panel_on_delay
must always be honored otherwise the panel will not turn on.
Instead of only always using regular msleep() for panel_on_delay
do as Windows does and always use regular msleep() everywhere
were intel_dsi_msleep() is used and drop the intel_dsi_msleep()
helper.
Changes in v2:
- Replace all intel_dsi_msleep() calls instead of just
the intel_dsi_msleep(panel_on_delay) call
Cc: stable@vger.kernel.org Fixes: 6fdb335f1c9c ("drm/i915/dsi: Use unconditional msleep for the panel_on_delay when there is no reset-deassert MIPI-sequence") Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230425194441.68086-1-hdegoede@redhat.com
Type-C PHYs are taking longer than expected for Aux IO Power Enabling.
Workaround: Increase the timeout.
---v2
-change style on how we mention WA [Ankit]
-fix bat error by creating new func that is only called for aux power
well scenarios so we can avoid null pointer error as it is called
everywhere.
--v3
-Add non-default enable_timeout to power well descriptor which avoids
adding more platform checks [Imre]
--v4
-Remove Bspec link from top to bottom remove WA link from commit put it
on comment [Jani]
-enable_timeout in ms and add .fixed_enable_delay too [Imre]
--v5
-move power_wells instead of duplicating them [Imre]
Imre Deak [Mon, 24 Apr 2023 20:02:05 +0000 (23:02 +0300)]
drm/i915/adlp+: Disable DC5/6 states for TC port DDI/AUX and for combo port AUX
On ADLP+ Bspec allows DC5/6 to be enabled while power well 2 is enabled.
Since the AUX and DDI power wells (except for port A/B) are also backed
by power well 2, this would suggest that DC5/6 can be enabled while any
of these AUX or DDI port functionalities are used. As opposed to this
AUX transfers will time out on ADLP TypeC ports while DC6 is enabled.
Until the restriction for DC5/6 is clarified in Bspec let's assume that
the intention is to allow for using these power states while pipe A/B is
enabled, but only for combo ports which can be used with eDP outputs.
Similarly assume that AUX transaction initiated by the driver on any port
requires DC states to be disabled.
Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Fixes: 88c487938414 ("drm/i915: Use separate "DC off" power well for ADL-P and DG2") Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230424200205.1732941-1-imre.deak@intel.com
Communicating QGV points restriction to PUnit happens via PM Demand
instead of the Pcode mailbox in the previous platforms. GV point
restriction is handled by the PM demand code.
Ville Syrjälä [Tue, 11 Apr 2023 19:14:29 +0000 (22:14 +0300)]
drm/i915/psr: Sprinkle cpu_transcoder variables around
Reduce the 'intel_dp' stuff a bit by introducing local
cpu_transcoder variables.
Ideally I'd like the whole PSR code to stop using intel_dp
except during a full modeset, but dunno yet if that's
possible. But the less 'intel_dp' we have sprad around
the easier that should be to figure out eventually.
Ville Syrjälä [Tue, 11 Apr 2023 19:14:28 +0000 (22:14 +0300)]
drm/i915/psr: Include PSR_PERF_CNT in debugfs output on all platforms
The fact that DC states reset the PSR perofrmance counter
is no reason not to include it in the debug output.
But let's keep the comment there to remind people about
that caveat.
Ville Syrjälä [Tue, 11 Apr 2023 19:14:27 +0000 (22:14 +0300)]
drm/i915/psr: Add a FIXME for the PSR vs. AUX usage conflict
We need to disable PSR when we are doing AUX by hand, otherwise
it's possible that the PSR hardware could be using the AUX CH
while we try to do our manual stuff. Add a FIXME for now.
Ville Syrjälä [Tue, 11 Apr 2023 19:14:26 +0000 (22:14 +0300)]
drm/i915/psr: Define more PSR mask bits
Define more of the PSR mask bits, and describe in detail
what some of them do. Even if we don't set them all from
the driver they can be very useful during PSR debugging.
Having to trawl through bspec every time to find them is
not fun, and re-reverse engineering the behaviour every
time is time consuming (even if a bit more fun than spec
trawling).
v2: Moar bits
Put the description into a comment to be easily available
v2: Fix the BDW_UNMASK_VBL_TO_REGS_IN_SRD/HSW_UNMASK_VBL_TO_REGS_IN_SRD
description
Rebase due to intel_psr_regs.h
Ville Syrjälä [Tue, 11 Apr 2023 19:14:22 +0000 (22:14 +0300)]
drm/i915: Fix up whitespace in some display chicken registers
Fix a bunch of whitespace issues in some display register
definitons. Only touching the bits alerayd using REG_BIT() &
co. here. The rest will come later.
Ville Syrjälä [Tue, 18 Apr 2023 17:55:20 +0000 (20:55 +0300)]
drm/i915: Use REG_BIT() & co. for ilk+ pfit registers
Polish the ilk+ pfit registers with REG_BIT() & co., and
also take the opportunity to unify the ivb/hsw vs. not checks
in ilk_pfit_enable() and ilk_get_pfit_config().
Ville Syrjälä [Tue, 18 Apr 2023 17:55:14 +0000 (20:55 +0300)]
drm/i915: Check pipe source size when using skl+ scalers
The skl+ scalers only sample 12 bits of PIPESRC so we can't
do any plane scaling at all when the pipe source size is >4k.
Make sure the pipe source size is also below the scaler's src
size limits. Might not be 100% accurate, but should at least be
safe. We can refine the limits later if we discover that recent
hw is less restricted.
Matt Roper [Tue, 18 Apr 2023 22:04:44 +0000 (15:04 -0700)]
drm/i915/mtl: Re-use ADL-P's "DC off" power well
As with ADL-P, MTL's "DC off" power well should be a dependency of the
PGC and PGD power wells, not the entire PG2 well. In fact, the DC5/DC6
requirements between the two platforms are the same, so the Xe_LPD "DC
off" well definition can just be re-used for Xe_LPD+.
Matt Roper [Tue, 18 Apr 2023 22:04:43 +0000 (15:04 -0700)]
drm/i915: Use separate "DC off" power well for ADL-P and DG2
Although ADL-P and DG2 both use the same general power well setup, the
DC5/DC6 requirements are slightly different which means each platform
should have its own "DC off" power well.
DG2 (i.e., Xe_HPD IP) requires that DC5 be disabled whenever PG2 is
active. However ADL-P (i.e., Xe_LPD IP) only requires DC5/DC6 to be
disabled when the PGC or PGD subwells are active; we should be able to
remain in these DC states when PGB and general PG2 functionality is in
use.
v2: Use dc_of as power well name.
Move xehpd power domain definitions near power well definition.(Imre)
Jani Nikula [Wed, 19 Apr 2023 09:42:43 +0000 (12:42 +0300)]
drm/i915: use explicit includes for i915_reg.h and i915_irq.h
A lot of places include i915_reg.h implicitly via i915_irq.h, which gets
included implicitly via intel_display_trace.h. Remove the includes from
the headers, and include i915_reg.h and i915_irq.h explicitly where
needed.
Imre Deak [Fri, 14 Apr 2023 17:38:00 +0000 (20:38 +0300)]
drm/i915/dp_mst: Fix active port PLL selection for secondary MST streams
The port PLL selection needs to be up-to-date in the CRTC state of both
the primary and all secondary MST streams. The commit removing the
encoder update_prepare/complete hooks (see Fixes: below), stopped doing
this for secondary streams, fix this up.
Fixes: 0f752b2178c9 ("drm/i915: Remove the encoder update_prepare()/complete() hooks") Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/8336 Cc: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230414173800.590790-1-imre.deak@intel.com
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