Terje Bergstrom [Fri, 22 Mar 2013 14:34:01 +0000 (16:34 +0200)]
gpu: host1x: Add host1x driver
Add host1x, the driver for host1x and its client unit 2D. The Tegra
host1x module is the DMA engine for register access to Tegra's
graphics- and multimedia-related modules. The modules served by
host1x are referred to as clients. host1x includes some other
functionality, such as synchronization.
Dave Airlie [Wed, 17 Apr 2013 05:18:32 +0000 (15:18 +1000)]
Merge branch 'gma500-next' of git://github.com/patjak/drm-gma500 into drm-next
Patrik writes:
I haven't had much review or testing on other platforms than Poulsbo but
at least the following Cedarview bug has been squashed and no
regressions reported: https://bugs.freedesktop.org/show_bug.cgi?id=58527
* 'gma500-next' of git://github.com/patjak/drm-gma500:
drm/gma500: Add debugging info to psb_gtt_restore()
drm/gma500: Check connector status before restoring sdvo
gma500:fix build failure for 3.9-rc5
drm/gma500: Fix hibernation problems on sdvo encoders
drm/gma500: Add hooks for hibernation
drm/gma500: Activate the gtt rebuild on suspend/resume
drm/gma500: Add support for rebuilding the gtt
drm/gma500: Change fb name so pm-utils doesn't apply quirks
gma500: Make VGA and HDMI connector hotpluggable
drm/gma500: Clean up various defines
drm/gma500: Remove unnecessary function exposure
drm/gma500: Type clock limits directly into array and remove defines
drm/gma500: Calculate clock in one function instead of three identical
drm/gma500: Remove unused i8xx clock limits
gma500: medfield: Fix possible NULL pointer dereference
drivers: gpu: drm: gma500: Replaced calls kzalloc & memcpy with kmemdup
gma500: remove unused drm_psb_no_fb
Dave Airlie [Tue, 16 Apr 2013 22:48:23 +0000 (08:48 +1000)]
Merge branch 'drm-next-3.10' of git://people.freedesktop.org/~agd5f/linux into drm-next
Alex writes:
This is the initial 3.10 pull request for radeon. The big changes here
are UVD support and proper tiling support for SI. The rest is
bug fixes. I hope to have another pull request later in the week with
some new things we've been working on internally.
* 'drm-next-3.10' of git://people.freedesktop.org/~agd5f/linux: (28 commits)
drm/radeon: Always flush the VM
drm/radeon: re-enable PTE/PDE packet for set_page on cayman/TN
drm/radeon: cleanup properly if mmio mapping fails
drm/radeon/evergreen+: don't enable HPD interrupts on eDP/LVDS
drm/radeon: add si tile mode array query v3
drm/radeon: add ring working query
drm/radeon: handle broken disabled rb mask gracefully
drm/radeon: add pcie set/get lanes callbacks for newer asics
drm/radeon: update r600 set/get pcie lane config
drm/radeon/kms: replace *REG32_PCIE_P with *REG32_PCIE_PORT
drm/radeon: remove unused blit remnants from si.c
drm/radeon: add UVD tiling addr config v2
drm/radeon: init UVD clocks to sane defaults
drm/radeon: add set_uvd_clocks callback for r7xx v3
drm/radeon: add set_uvd_clocks callback for SI
drm/radeon: add set_uvd_clocks callback for evergreen
drm/radeon: add set_uvd_clocks callback for ON/LN/TN (v4)
drm/radeon: add radeon_atom_get_clock_dividers helper
drm/radeon: add pm callback for setting uvd clocks
drm/radeon: UVD bringup v8
...
This is slightly cleaned up version of Jerome's patch.
There seems to be an issue tracking the last flush of
the VM which results in hangs in certain cases when
VM is used. For now just flush the VM for every IB.
Signed-off-by: Jerome Glisse <jglisse@redhat.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
Alex Deucher [Tue, 16 Apr 2013 14:42:15 +0000 (10:42 -0400)]
drm/radeon: re-enable PTE/PDE packet for set_page on cayman/TN
PTE/PDE doesn't support a single update (count = 1). We had
previously disabled it since it we were hitting that case which
let to hangs. The PTE/PDE packet is much more efficient for VM
updates where it can be used.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dave Airlie [Tue, 16 Apr 2013 03:24:25 +0000 (13:24 +1000)]
drm/qxl: make lots of things static.
/usr/lib/gcc/x86_64-linux-gnu/4.7/include/stddef.h:414:9: sparse: preprocessor token offsetof redefined
include/linux/stddef.h:17:9: this was the original definition
>> drivers/gpu/drm/qxl/qxl_drv.c:49:5: sparse: symbol 'qxl_modeset' was not declared. Should it be static?
Reported-by: kbuild test robot. Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Tue, 16 Apr 2013 03:20:03 +0000 (13:20 +1000)]
Merge tag 'omapdss-for-3.10' of git://gitorious.org/linux-omap-dss2/linux into drm-next
Omapdss patches for 3.10 merge window
The biggest changes are:
* DSI video mode: automatic clock and timing calculation
* Lots of platform data related panel driver cleanups, to prepare for DT
* tag 'omapdss-for-3.10' of git://gitorious.org/linux-omap-dss2/linux: (69 commits)
drm/omap: add statics to a few structs
drm/omap: Fix and improve crtc and overlay manager correlation
drm/omap: Take a fb reference in omap_plane_update()
drm/omap: Make fixed resolution panels work
drm/omap: fix modeset_init if a panel doesn't satisfy omapdrm requirements
OMAPDSS: DPI: widen the pck search when using dss fck
OMAPDSS: fix dss_fck clock rate rounding
omapdss: use devm_clk_get()
OMAPDSS: nec-nl8048 panel: Use dev_pm_ops
OMAPDSS: DISPC: Revert to older DISPC Smart Standby mechanism for OMAP5
OMAPDSS: DISPC: Configure doublestride for NV12 when using 2D Tiler buffers
omapdss: Features: Fix some parameter ranges
omapdss: DISPC: add max pixel clock limits for LCD and TV managers
OMAPDSS: DSI: Use devm_clk_get()
drivers: video: omap2: dss: Use PTR_RET function
OMAPDSS: VENC: remove platform_enable/disable calls
OMAPDSS: n8x0 panel: remove use of platform_enable/disable
OMAPDSS: n8x0 panel: handle gpio data in panel driver
OMAPDSS: picodlp panel: remove platform_enable/disable callbacks
OMAPDSS: picodlp panel: handle gpio data in panel driver
...
Chris Wilson [Fri, 12 Apr 2013 09:39:59 +0000 (10:39 +0100)]
drm: Perform ioctl command validation on the stored kernel values
Userspace is free to pass in any command bits it feels like through the
ioctl cmd, and for example trinity likes to fuzz those bits to create
conflicting commands. So instead of relying upon userspace to pass along
the correct IN/OUT flags for the ioctl, use the flags as expected by the
kernel.
This does have a side-effect that NULL pointers can not be substituted
by userspace in place of a struct. This feature was not being used by
any driver, but instead exposed all of the command handlers to a user
triggerable OOPS.
Paul Sokolovsky [Fri, 12 Apr 2013 23:28:26 +0000 (18:28 -0500)]
drm.h: Fix DRM compilation with bare-metal toolchain.
An ifdef in drm.h expects to be compiled with full-fledged Linux
toolchain, but it's common to compile kernel with just bare-metal
toolchain which doesn't define __linux__. So, also add __KERNEL__
check.
[nm@ti.com: port forward to 3.9-rc6 and post to dri devel for feedback as RFC] Signed-off-by: Paul Sokolovsky <paul.sokolovsky@linaro.org> Signed-off-by: Dave Airlie <airlied@redhat.com>
drm: Destroy property blobs at mode config cleanup time
Property blob objects need to be destroyed when cleaning up to avoid
memory leaks. Go through the list of all blobs in the
drm_mode_config_cleanup() function and destroy them.
The drm_mode_config_cleanup() function needs to be moved after the
drm_property_destroy_blob() declaration. Move drm_mode_config_init() as
well to keep the functions together.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Tue, 16 Apr 2013 03:03:47 +0000 (13:03 +1000)]
Merge tag 'drm-intel-next-2013-04-06' of git://people.freedesktop.org/~danvet/drm-intel into drm-next
Daniel writes:
Since I expect Linus to open the merge window in about a week I guess this
is the last i915 feature pull for 3.10. Highlights:
Updated testing tree for -next. Highlights:
- Corner case fixes discovered with static analyzers (Damien).
- More fixes to combat unclaimed register errors on Haswell (Paulo).
- Some small fixes to the gpu turbo code (Rodrigo+Ben), Ben has more
fixes for overclocking support pending.
- More prep work for fastboot from Chris.
- VT-switchless suspend/resume from Jesse.
- The prep work of Egbert Eich's hpd irq storm handling. Hopefully we can
squeeze in the actual storm handling code for 3.10 ...
- More convenience helpers for Imre's sg iterator. Core parts acked by
Andrew Morton.
- A bit of backlight code cleanup from Jani.
- Fixed ilk gpu reset (Jesse).
- Reduced color range handling fixes for VLV (Ville).
The big item here is though the introduction of pipe_config to properly
pre-compute the desired modeset state before touching the hw. Together
with some very basic support to read out the current config from the hw
and compare the state with the sw tracking. This is all prep work for more
reliable fastboot, atomic modesets and other cool features. Stuff
converted to the new world includes:
- Most simple pipe attributes (reduce color range, pixel multiplier).
- Pipe bpp/dither handling.
- Some convenience flags like ->has_pch_encoder to simplify the code flow.
- (Almost) DP clock handling, had to be reverted since part of a prep
patch was lost in rebasing ...
Expect a lot of patches for this throughout 3.11, there's tons of work
till we have all state properly tracked for fastbooting to woExpect a lot
of patches for this throughout 3.11, there's tons of work till we have all
state properly tracked for fastbooting to work.
For 3.10 I have a bunch of fixes queued up and I plan to send them all out
at the end of this week. I need to shuffle patches in my -next queue a bit
so that we don't but feature-y stuff in there, too. The main thing I'd
like to sneak in is Egbert's hpd irq storm handling, which should be
pretty low-risk since all the infrastructure work has landed already. I
also have the oops fix pending, but that only mustered review before the
w/e and giving how hairy that part of our modeset code is, I want to give
it some more testing before forwarding.
Note: annarchy.fd.o seems to run out of disk space, so couldn't push the
usual for-airlied branch. Tag should work though.
Note 2: I've had to do a backmerge since conflicts grew too ugly, but the
upstream -rc I've backmerged is already in your drm-next.
* tag 'drm-intel-next-2013-04-06' of git://people.freedesktop.org/~danvet/drm-intel: (75 commits)
drm/i915: info level for simulated gpu hang dmesg notice
drm/i915: revert eDP bpp clamping code changes
Revert "drm/i915: fix DP get_hw_state return value"
drm/i915: Don't use the HDMI port color range bit on Valleyview
drm/i915: Set PIPECONF color range bit on Valleyview
drm/i915: extract i9xx_set_pipeconf
drm/i915: Add no-lvds quirk for Fujitsu Esprimo Q900
drm/i915: create pipe_config->dpll for clock state
drm/i915: hw readout support for ->has_pch_encoders
drm/i915: add hw state readout/checking for pipe_config
drm/i915: rip out superflous is_dp&is_cpu_edp tracking
drm/i915: remove leaky eDP functions
drm/i915: track dp target_clock in pipe_config
drm/i915: move dp_m_n computation to dp_encoder->compute_config
drm/i915: clear up the fdi/dp set_m_n confusion
drm/i915: Fix sdvo connector get_hw_state function
drm/i915: drop DPFLIPSTAT enables on VLV v3
drm/i915: add Punit read/write routines for VLV v2
drm/i915: panel power sequencing for VLV eDP v2
drm/i915/dp: fix up VLV DP handling v2
...
drm/gma500: Check connector status before restoring sdvo
This patch fixes a bug introduced by:
commit 749387dc8d8270b279f27a0a794cdf4f4a4aa774
Author: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
Date: Sun Apr 7 16:35:50 2013 +0200
drm/gma500: Fix hibernation problems on sdvo encoders
The bug is triggered when we do a mode set on a sdvo encoder with all
connectors in the disconnected state. A crtc is considered enabled by
drm even though all of its connectors are disconnected. Work around
this by adding a check in our sdvo restore function.
Also remove the unneeded dpms on. Prepare and Commit will take care of
that.
drm: cleanup: use drm_framebuffer_reference instead of a kref_get
drm_framebuffer_lookup() does a kref_get() for the framebuffer if it finds one
corresponding to the fb id passed to it. Use drm_framebuffer_reference() instead
for clarity since it's the function used in other places to take a reference.
Signed-off-by: Archit Taneja <archit@ti.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Dave Airlie <airlied@redhat.com>
drm: Add 1600x1200 (UXGA) screen resolution to the built-in EDIDs
The 1600x1200 (UXGA) screen resolution was lacking in the set of
built-in selectable EDID screen resolutions that can be used to
repair misbehaving monitor firmware.
This patch adds the related data set and expands the documentation.
Signed-off-by: Carsten Emde <C.Emde@osadl.org> Acked-by: Paul Menzel <paulepanter@users.sourceforge.net> Signed-off-by: Dave Airlie <airlied@redhat.com>
In order to make it easier to port the code to other operating systems
(like the BSDs), relicense the HDMI helpers under the more permissive
MIT license.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 25 Feb 2013 04:47:55 +0000 (14:47 +1000)]
drm: add new QXL driver. (v1.4)
QXL is a paravirtual graphics device used by the Spice virtual desktop
interface.
The drivers uses GEM and TTM to manage memory, the qxl hw fencing however
is quite different than normal TTM expects, we have to keep track of a number
of non-linear fence ids per bo that we need to have released by the hardware.
The releases are freed from a workqueue that wakes up and processes the
release ring.
releases are suballocated from a BO, there are 3 release categories, drawables,
surfaces and cursor cmds. The hw also has 3 rings for commands, cursor and release handling.
The hardware also have a surface id tracking mechnaism and the driver encapsulates it completely inside the kernel, userspace never sees the actual hw surface
ids.
This requires a newer version of the QXL userspace driver, so shouldn't be
enabled until that has been placed into your distro of choice.
Authors: Dave Airlie, Alon Levy
v1.1: fixup some issues in the ioctl interface with padding
v1.2: add module device table
v1.3: fix nomodeset, fbcon leak, dumb bo create, release ring irq,
don't try flush release ring (broken hw), fix -modesetting.
v1.4: fbcon cpu usage reduction + suitable accel flags.
Signed-off-by: Alon Levy <alevy@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Christian König [Tue, 9 Apr 2013 14:35:42 +0000 (10:35 -0400)]
drm/radeon: add ring working query
Add new ioctl option and bumb minor version number.
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
If the disabled rb mask register is not properly initialized
program a sane default based on the number of RBs for the
asic. This avoids a potential divide by 0 when calculating
the backend mask.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Archit Taneja [Tue, 26 Mar 2013 13:45:19 +0000 (19:15 +0530)]
drm/omap: Fix and improve crtc and overlay manager correlation
The omapdrm driver currently takes a config/module arg to figure out the number
of crtcs it needs to create. We could create as many crtcs as there are overlay
managers in the DSS hardware, but we don't do that because each crtc eats up
one DSS overlay, and that reduces the number of planes we can attach to a single
crtc.
Since the number of crtcs may be lesser than the number of hardware overlay
managers, we need to figure out which overlay managers to use for our crtcs. The
current approach is to use pipe2chan(), which returns a higher numbered manager
for the crtc.
The problem with this approach is that it assumes that the overlay managers we
choose will connect to the encoders the platform's panels are going to use,
this isn't true, an overlay manager connects only to a few outputs/encoders, and
choosing any overlay manager for our crtc might lead to a situation where the
encoder cannot connect to any of the crtcs we have chosen. For example, an
omap5-panda board has just one hdmi output. If num_crtc is set to 1, with the
current approach, pipe2chan will pick up the LCD2 overlay manager, which cannot
connect to the hdmi encoder at all. The only manager that could have connected
to hdmi was the TV overlay manager.
Therefore, there is a need to choose our overlay managers keeping in mind the
panels we have on that platform. The new approach iterates through all the
available panels, creates encoders and connectors for them, and then tries to
get a suitable overlay manager to create a crtc which can connect to the
encoders.
We use the dispc_channel field in omap_dss_output to retrieve the desired
overlay manager's channel number, we then check whether the manager had already
been assigned to a crtc or not. If it was already assigned to a crtc, we assume
that out of all the encoders which intend use this crtc, only one will run at a
time. If the overlay manager wan't assigned to a crtc till then, we create a
new crtc and link it with the overlay manager.
This approach just looks for the best dispc_channel for each encoder. On DSS HW,
some encoders can connect to multiple overlay managers. Since we don't try
looking for alternate overlay managers, there is a greater possibility that 2
or more encoders end up asking for the same crtc, causing only one encoder to
run at a time.
Also, this approach isn't the most optimal one, it can do either good or bad
depending on the sequence in which the panels/outputs are parsed. The optimal
way would be some sort of back tracking approach, where we improve the set of
managers we use as we iterate through the list of panels/encoders. That's
something left for later.
Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
drm/omap: Take a fb reference in omap_plane_update()
When userspace calls SET_PLANE ioctl, drm core takes a reference of the fb and
passes control to the update_plane op defined by the drm driver.
In omapdrm, we have a worker thread which queues framebuffers objects received
from update_plane and displays them at the appropriate time.
It is possible that the framebuffer is destoryed by userspace between the time
of calling the ioctl and apply-worker being scheduled. If this happens, the
apply-worker holds a pointer to a framebuffer which is already destroyed.
Take an extra refernece/unreference of the fb in omap_plane_update() to prevent
this from happening. A reference is taken of the fb passed to update_plane(),
the previous framebuffer (held by plane->fb) is unreferenced. This will prevent
drm from destroying the framebuffer till the time it's unreferenced by the
apply-worker.
This is in addition to the exisitng reference/unreference in update_pin(),
which is taken for the scanout of the plane's current framebuffer, and an
unreference the previous framebuffer.
Signed-off-by: Archit Taneja <archit@ti.com> Reviewed-by: Rob Clark <robdclark@gmail.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Archit Taneja [Tue, 26 Mar 2013 13:45:20 +0000 (19:15 +0530)]
drm/omap: Make fixed resolution panels work
The omapdrm driver requires omapdss panel drivers to expose ops like detect,
set_timings and check_timings. These can be NULL for fixed panel DPI, DBI, DSI
and SDI drivers. At some places, there are no checks to see if the panel driver
has these ops or not, and that leads to a crash.
The following things are done to make fixed panels work:
- The omap_connector's detect function is modified such that it considers panel
types which are generally fixed panels as always connected(provided the panel
driver doesn't have a detect op). Hence, the connector corresponding to these
panels is always in a 'connected' state.
- If a panel driver doesn't have a check_timings op, assume that it supports the
mode passed to omap_connector_mode_valid(the 'mode_valid' drm helper function)
- The function omap_encoder_update shouldn't really do anything for fixed
resolution panels, make sure that it calls set_timings only if the panel
driver has one.
Signed-off-by: Archit Taneja <archit@ti.com> Reviewed-by: Rob Clark <robdclark@gmail.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Archit Taneja [Tue, 26 Mar 2013 13:45:18 +0000 (19:15 +0530)]
drm/omap: fix modeset_init if a panel doesn't satisfy omapdrm requirements
modeset_init iterates through all the registered omapdss devices and has some
initial checks to see if the panel has a driver and the required driver ops for
it to be usable by omapdrm.
The function bails out from modeset_init if a panel doesn't meet the
requirements, and stops the registration of the future panels and encoders which
come after it, that isn't the correct thing to do, we should go through the rest
of the panels. Replace the 'return's with 'continue's.
Signed-off-by: Archit Taneja <archit@ti.com> Reviewed-by: Rob Clark <robdclark@gmail.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Tomi Valkeinen [Wed, 10 Apr 2013 11:54:54 +0000 (14:54 +0300)]
OMAPDSS: DPI: widen the pck search when using dss fck
When not using DSI PLL to generate the pixel clock, but DSS FCK, the
possible pixel clock rates are rather limited. DSS FCK is currently used
on OMAP2 and OMAP3.
When using Beagleboard with a monitor that supports high resolutions,
the clock rates do not match (at least for me) for the monitor's pixel
clocks within the current threshold in the code, which is +/- 1MHz.
This patch widens the search up to +/- 15MHz. The search is done in
steps, i.e. it first tries to find a rather exact clock, than a bit less
exact, etc. so this should not change the cases where a clock was
already found.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Tomi Valkeinen [Wed, 10 Apr 2013 11:47:38 +0000 (14:47 +0300)]
OMAPDSS: fix dss_fck clock rate rounding
DSS func clock is calculated with prate / div * m. However, the current
omapdss code calculates it with prate * m / div, which yields a slightly
different result when there's a remainder. For example, 432000000 / 14 *
2 = 61714284, but 432000000 * 2 / 14 = 61714285.
In addition to that, the clock framework wants the clock rate given with
clk_set_rate to be higher than the actual (truncated) end result. So, if
prate is 432000000, and div is 14, the real result is 30857142.8571...
We need to call clk_set_rate with 30857143, which gives us a clock of 30857142. That's why we need to use DIV_ROUND_UP() when calling
clk_set_rate.
This patch fixes the clock calculation.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Last version of this patch is not clear enough and X86 duplicated.
This patch fixes build failure of v3.9-rc5 and rc6.
When config ACPI_VIDEO as m, DRM_GMA500 as y, here comes the failure.
GMA5/600 needs acpi_video just like nouveau.
And some tab type fix by the way.
Failure message:
drivers/built-in.o: In function `psb_driver_load':
kernel-3.9-rc5/drivers/gpu/drm/gma500/psb_drv.c:340: \
undefined reference to `acpi_video_register'
make: *** [vmlinux] Error 1
Archit Taneja [Tue, 26 Mar 2013 13:45:25 +0000 (19:15 +0530)]
OMAPDSS: DISPC: Revert to older DISPC Smart Standby mechanism for OMAP5
DISPC on OMAP5 has a more optimised mechanism of asserting Mstandby to achieve
more power savings when DISPC is configured in Smart Standby mode. This
mechanism leads to underflows when multiple DISPC pipes are enabled.
There is a register field which can let us revert to the older mechanism of
asserting Mstandby. Configure this field to prevent underflows.
Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Archit Taneja [Tue, 26 Mar 2013 13:45:24 +0000 (19:15 +0530)]
OMAPDSS: DISPC: Configure doublestride for NV12 when using 2D Tiler buffers
When using a DISPC video pipeline to a fetch a NV12 buffer in a 2D container, we
need to set set a doublestride bit in the video pipe's ATTRIBUTES register. This
is needed because the stride for the UV plane(using a 16 bit Tiler container) is
double the stride for the Y plane(using a 8 bit Tiler container) for the 0 or
180 degree views. The ROW_INC register is meant for the Y plane, and the HW will
calculate the row increment needed for the UV plane by using double the stride
value based on whether this bit is set or not.
Set the bit when we are using a 2D Tiler buffer and when rotation is 0 or 180
degrees. The stride value is the same for 90 and 270 degree Tiler views, hence
the bit shouldn't be set.
Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Archit Taneja [Tue, 26 Mar 2013 13:45:23 +0000 (19:15 +0530)]
omapdss: Features: Fix some parameter ranges
Increase the DSS_FCLK and DSI_FCLK max supported frequencies, these come because
some frequencies were increased from OMAP5 ES1 to OMAP5 ES2. We support only
OMAP5 ES2 in the kernel, so replace the ES1 values with ES2 values. Increase the
DSI PLL Fint range, this was previously just copied from the OMAP4 param range
struct.
Fix the maximum DSS_FCLK on OMAP2, it's 133 Mhz according to the TRM.
Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Archit Taneja [Tue, 26 Mar 2013 13:45:22 +0000 (19:15 +0530)]
omapdss: DISPC: add max pixel clock limits for LCD and TV managers
Each version of OMAP has a limitation on the maximum pixel clock frequency
supported by an overlay manager. This limit isn't checked by omapdss. Add
dispc feats for lcd and tv managers and check whether the target timings can
be supported or not.
The pixel clock limitations are actually more complex. They depend on which OPP
OMAP is in, and they also depend on which encoder is the manager connected to.
The OPP dependence is ignored as DSS forces the PM framework to be on OPP100
when DSS is enabled, and the encoder dependencies are ignored by DISPC for now.
These limits should come from the encoder driver.
The OMAP2 TRM doesn't mention the maximum pixel clock limit. This value is left
as half of DSS_FCLK, as OMAP2 requires the PCD to be atleast 2.
Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Christian König [Mon, 8 Apr 2013 10:41:37 +0000 (12:41 +0200)]
drm/radeon: add UVD tiling addr config v2
v2: set UVD tiling config for rv730
Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jerome Glisse <jglisse@redhat.com>
Christian König [Mon, 8 Apr 2013 10:41:36 +0000 (12:41 +0200)]
drm/radeon: init UVD clocks to sane defaults
Just until we get proper DPM for that.
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jerome Glisse <jglisse@redhat.com>
Christian König [Mon, 8 Apr 2013 10:41:34 +0000 (12:41 +0200)]
drm/radeon: add set_uvd_clocks callback for SI
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Mon, 8 Apr 2013 10:41:33 +0000 (12:41 +0200)]
drm/radeon: add set_uvd_clocks callback for evergreen
v2: remove unneeded register definitions
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Mon, 8 Apr 2013 10:41:32 +0000 (12:41 +0200)]
drm/radeon: add set_uvd_clocks callback for ON/LN/TN (v4)
v2: write clk registers only once!
v3: update cg scratch register properly
v4: add TN support
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Mon, 8 Apr 2013 10:41:30 +0000 (12:41 +0200)]
drm/radeon: add pm callback for setting uvd clocks
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Mon, 8 Apr 2013 10:41:29 +0000 (12:41 +0200)]
drm/radeon: UVD bringup v8
Just everything needed to decode videos using UVD.
v6: just all the bugfixes and support for R7xx-SI merged in one patch
v7: UVD_CGC_GATE is a write only register, lockup detection fix
v8: split out VRAM fallback changes, remove support for RV770,
add support for HEMLOCK, add buffer sizes checks
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Mon, 8 Apr 2013 10:41:28 +0000 (12:41 +0200)]
drm/radeon: rework fallback handling v2
Let the CS module decide if we can fall back to VRAM or not.
v2: remove unintended change
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Mon, 8 Apr 2013 10:41:27 +0000 (12:41 +0200)]
drm/radeon: UVD doesn't needs VM on SI v2
v2: update error message and comment
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Samuel Li [Mon, 8 Apr 2013 21:25:47 +0000 (17:25 -0400)]
drm/radeon: Use direct mapping for fast fb access on RS690
This patch allows the CPU to map the stolen vram segment
directly rather than going through the PCI BAR. This
significantly improves performance for certain workloads with
a properly patched ddx.
Use radeon.fastfb=1 to enable it (disabled by default).
Currently only supported on RS690, but support for RS780/880
and newer APUs may be added eventually.
Signed-off-by: Samuel Li <samuel.li@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Mon, 8 Apr 2013 15:13:01 +0000 (11:13 -0400)]
drm/radeon: clean up vram/gtt location handling
Add a per-asic MC (memory controller) mask which holds the
mak address mask the asic is capable of. Use this when
calculating the vram and gtt locations rather using asic
specific functions or limiting everything to 32 bits.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/gma500: Fix hibernation problems on sdvo encoders
The state of the SDVO chip is more difficult to save than the LVDS so we do a
full mode set on the crtc to get SDVO operational again. The SDVOB/C register is
also stored just in case we have special bits set in the future.
drm/gma500: Activate the gtt rebuild on suspend/resume
This patch activates the rebuilding of the gtt. Currently we reinitialize the
gtt by inserting the stolen pages again and map the rest to our scratch page.
Then we go about restoring the needed ranges. This is a bit overkill but right
now we don't have that much to restore so better safe than sorry.
drm/i915: convert DP autodither code to new infrastructure
The old behaviour was that we used the plane's bpp (usually 24bpp) for
computing the dp link bw, but set up the pipe with the bpp value from
vbt if available. This takes the vbt bpp override into account even
for the dp link bw configuration.
On Paulo's hsw machine this resulted in a slower link clock and a
black screen - but the mode actually /should/ fit even with the lower
clock. Until we've cleared up simply stay bug-for-bug compatible with
the old code.
While at it, also restore a debug message lost in:
drm/i915: precompute pipe bpp before touching the hw
Cc: Paulo Zanoni <przanoni@gmail.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Tested-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ville Syrjälä [Tue, 2 Apr 2013 13:10:10 +0000 (16:10 +0300)]
drm/i915: Don't use the HDMI port color range bit on Valleyview
VLV docs still list the the color range selection bit for the HDMI
ports, but for DP ports it has been repurposed.
I have no idea whether the HDMI color range selection bit still works
on VLV, but since we now have to use the PIPECONF color range bit for
DP, we might as well do the same for HDMI.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ville Syrjälä [Tue, 2 Apr 2013 13:10:09 +0000 (16:10 +0300)]
drm/i915: Set PIPECONF color range bit on Valleyview
VLV has the color range selection bit in the PIPECONF register.
Configure it appropriately.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
[danvet: fixup rebase issues due to slightly different baseline.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drm/i915: Add no-lvds quirk for Fujitsu Esprimo Q900
The "Mobile Sandy Bridge CPUs" in the Fujitsu Esprimo Q900
mini desktop PCs are probably misleading the LVDS detection
code in intel_lvds_supported. Nothing is connected to the
LVDS ports in these systems.
Signed-off-by: Christian Lamparter <chunkeey@googlemail.com> Cc: stable@vger.kernel.org Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Dave Airlie [Fri, 5 Apr 2013 00:18:13 +0000 (10:18 +1000)]
Merge tag 'drm-intel-next-2013-03-23' of git://people.freedesktop.org/~danvet/drm-intel into drm-next
Daniel writes:
Highlights:
- Imre's for_each_sg_pages rework (now also with the stolen mem backed
case fixed with a hack) plus the drm prime sg list coalescing patch from
Rahul Sharma. I have some follow-up cleanups pending, already acked by
Andrew Morton.
- Some prep-work for the crazy no-pch/display-less platform by Ben.
- Some vlv patches, by far not all (Jesse et al).
- Clean up the HDMI/SDVO #define confusion (Paulo)
- gen2-4 vblank fixes from Ville.
- Unclaimed register warning fixes for hsw (Paulo). More still to come ...
- Complete pageflips which have been stuck in a gpu hang, should prevent
stuck gl compositors (Ville).
- pm patches for vt-switchless resume (Jesse). Note that the i915 enabling
is not (yet) included, that took a bit longer to settle. PM patches are
acked by Rafael Wysocki.
- Minor fixlets all over from various people.
* tag 'drm-intel-next-2013-03-23' of git://people.freedesktop.org/~danvet/drm-intel: (79 commits)
drm/i915: Implement WaSwitchSolVfFArbitrationPriority
drm/i915: Set the VIC in AVI infoframe for SDVO
drm/i915: Kill a strange comment about DPMS functions
drm/i915: Correct sandybrige overclocking
drm/i915: Introduce GEN7_FEATURES for device info
drm/i915: Move num_pipes to intel info
drm/i915: fixup pd vs pt confusion in gen6 ppgtt code
style nit: Align function parameter continuation properly.
drm/i915: VLV doesn't have HDMI on port C
drm/i915: DSPFW and BLC regs are in the display offset range
drm/i915: set conservative clock gating values on VLV v2
drm/i915: fix WaDisablePSDDualDispatchEnable on VLV v2
drm/i915: add more VLV IDs
drm/i915: use VLV DIP routines on VLV v2
drm/i915: add media well to VLV force wake routines v2
drm/i915: don't use plane pipe select on VLV
drm: modify pages_to_sg prime helper to create optimized SG table
drm/i915: use for_each_sg_page for setting up the gtt ptes
drm/i915: create compact dma scatter lists for gem objects
drm/i915: handle walking compact dma scatter lists
...
Jan Stancek [Thu, 4 Apr 2013 18:35:10 +0000 (11:35 -0700)]
mm: prevent mmap_cache race in find_vma()
find_vma() can be called by multiple threads with read lock
held on mm->mmap_sem and any of them can update mm->mmap_cache.
Prevent compiler from re-fetching mm->mmap_cache, because other
readers could update it in the meantime:
thread 1 thread 2
|
find_vma() | find_vma()
struct vm_area_struct *vma = NULL; |
vma = mm->mmap_cache; |
if (!(vma && vma->vm_end > addr |
&& vma->vm_start <= addr)) { |
| mm->mmap_cache = vma;
return vma; |
^^ compiler may optimize this |
local variable out and re-read |
mm->mmap_cache |
This issue can be reproduced with gcc-4.8.0-1 on s390x by running
mallocstress testcase from LTP, which triggers:
Merge tag 'upstream-3.9-rc6' of git://git.infradead.org/linux-ubifs
Pull UBIFS fix from Artem Bityutskiy:
"Make the space fixup feature work in the case when the file-system is
first mounted R/O and then remounted R/W."
* tag 'upstream-3.9-rc6' of git://git.infradead.org/linux-ubifs:
UBIFS: make space fixup work in the remount case
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/hid
Pull HID fixes from Jiri Kosina:
- Workaround for device ID conflict between Masterkit MA901 usb radio
device and Atmel V-USB devices, to avoid regressions from older
kernels, by Alexey Klimov
- fix for possible race during input device registration in magicmouse
driver, by Benjamin Tissoires
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/hid:
HID: magicmouse: fix race between input_register() and probe()
media: radio-ma901: return ENODEV in probe if usb_device doesn't match
HID: fix Masterkit MA901 hid quirks
Merge tag 'gpio-fixes-v3.9' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio
Pull GPIO fixes from Linus Walleij:
"Two GPIO fixes for the v3.9 series:
- Fix erroneous return value in the ICH driver
- Make the STMPE driver proper properly on device tree boots"
* tag 'gpio-fixes-v3.9' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio:
gpio: stmpe: pass DT node to irqdomain
gpio-ich: Fix value returned by ichx_gpio_request
HID: magicmouse: fix race between input_register() and probe()
Since kernel 3.7, it appears that the input registration occured before
the end of magicmouse_setup_input(). This is shown by receiving a lot of
"EV_SYN SYN_REPORT 1" instead of normal "EV_SYN SYN_REPORT 0".
This value means that the output buffer is full, and the user space
is loosing events.
Using .input_configured guarantees that the race is not occuring, and that
the call of "input_set_events_per_packet(input, 60)" is taken into account
by input_register().
Merge branch 'fixes' of git://git.linaro.org/people/rmk/linux-arm
Pull ARM fixes from Russell King:
"Another round of ARM fixes, which include:
- Fixing a problem with LPAE mapping sections
- Reporting of some hwcaps on Krait CPUs
- Avoiding repetitive warnings in the breakpoint code
- Fixing a build error noticed on Dove platforms with PJ4 CPUs
- Fix masking of level 2 cache revision.
- Fixing timer-based udelay()
- A larger fix for an erratum causing people major grief with Cortex
A15 CPUs"
* 'fixes' of git://git.linaro.org/people/rmk/linux-arm:
ARM: 7690/1: mm: fix CONFIG_LPAE typos
ARM: 7689/1: add unwind annotations to ftrace asm
ARM: 7685/1: delay: use private ticks_per_jiffy field for timer-based delay ops
ARM: 7684/1: errata: Workaround for Cortex-A15 erratum 798181 (TLBI/DSB operations)
ARM: 7682/1: cache-l2x0: fix masking of RTL revision numbering and set_debug init
ARM: iWMMXt: always enable iWMMXt support with PJ4 CPUs
ARM: 7681/1: hw_breakpoint: use warn_once to avoid spam from reset_ctrl_regs()
ARM: 7678/1: Work around faulty ISAR0 register in some Krait CPUs
ARM: 7680/1: Detect support for SDIV/UDIV from ISAR0 register
ARM: 7679/1: Clear IDIVT hwcap if CONFIG_ARM_THUMB=n
ARM: 7677/1: LPAE: Fix mapping in alloc_init_section for unaligned addresses
ARM: KVM: vgic: take distributor lock on sync_hwstate path
ARM: KVM: vgic: force EOIed LRs to the empty state
Merge tag 'ext4_for_linus_stable' of git://git.kernel.org/pub/scm/linux/kernel/git/tytso/ext4
Pull ext4 fixes from Ted Ts'o:
"Unfortunately, we introduced some big-endian bugs during the last
merge window. Fortunately, Cai and Christian noticed before 3.9
shipped."
* tag 'ext4_for_linus_stable' of git://git.kernel.org/pub/scm/linux/kernel/git/tytso/ext4:
ext4: fix big-endian bugs which could cause fs corruptions
Zheng Liu [Wed, 3 Apr 2013 16:27:18 +0000 (12:27 -0400)]
ext4: fix big-endian bugs which could cause fs corruptions
When an extent was zeroed out, we forgot to do convert from cpu to le16.
It could make us hit a BUG_ON when we try to write dirty pages out. So
fix it.
[ Also fix a bug found by Dmitry Monakhov where we were missing
le32_to_cpu() calls in the new indirect punch hole code.
There are a number of other big endian warnings found by static code
analyzers, but we'll wait for the next merge window to fix them all
up. These fixes are designed to be Obviously Correct by code
inspection, and easy to demonstrate that it won't make any
difference (and hence, won't introduce any bugs) on little endian
architectures such as x86. --tytso ]
Signed-off-by: Zheng Liu <wenqing.lz@taobao.com> Signed-off-by: "Theodore Ts'o" <tytso@mit.edu> Reported-by: CAI Qian <caiqian@redhat.com> Reported-by: Christian Kujau <lists@nerdbynature.de> Cc: Dmitry Monakhov <dmonakhov@openvz.org>
Paul Bolle [Wed, 3 Apr 2013 11:24:45 +0000 (12:24 +0100)]
ARM: 7690/1: mm: fix CONFIG_LPAE typos
CONFIG_LPAE doesn't exist: the correct option is CONFIG_ARM_LPAE, so fix
up the two typos under arch/arm/.
The fix to head.S is slightly scary, but this is just for setting up
an early io-mapping for the serial port when running on a big-endian,
LPAE system. Since these systems don't exist in the wild (at least, I
have no access to one outside of kvmtool, which doesn't provide a serial
port suitable for earlyprintk), then we can revisit the code later if it
causes any problems.
Signed-off-by: Paul Bolle <pebolle@tiscali.nl> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Rabin Vincent [Tue, 2 Apr 2013 21:11:46 +0000 (22:11 +0100)]
ARM: 7689/1: add unwind annotations to ftrace asm
Add unwind annotations to the ftrace assembly code so that the function
tracer's stacktracing options (func_stack_trace, etc.) work when
CONFIG_ARM_UNWIND is enabled.
Signed-off-by: Rabin Vincent <rabin@rab.in> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Will Deacon [Thu, 28 Mar 2013 10:17:55 +0000 (11:17 +0100)]
ARM: 7685/1: delay: use private ticks_per_jiffy field for timer-based delay ops
Commit 70264367a243 ("ARM: 7653/2: do not scale loops_per_jiffy when
using a constant delay clock") fixed a problem with our timer-based
delay loop, where loops_per_jiffy is scaled by cpufreq yet used directly
by the timer delay ops.
This patch fixes the problem in a more elegant way by keeping a private
ticks_per_jiffy field in the delay ops, independent of loops_per_jiffy
and therefore not subject to scaling. The loop-based delay continues to
use loops_per_jiffy directly, as it should.
Acked-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Catalin Marinas [Tue, 26 Mar 2013 22:35:04 +0000 (23:35 +0100)]
ARM: 7684/1: errata: Workaround for Cortex-A15 erratum 798181 (TLBI/DSB operations)
On Cortex-A15 (r0p0..r3p2) the TLBI/DSB are not adequately shooting down
all use of the old entries. This patch implements the erratum workaround
which consists of:
1. Dummy TLBIMVAIS and DSB on the CPU doing the TLBI operation.
2. Send IPI to the CPUs that are running the same mm (and ASID) as the
one being invalidated (or all the online CPUs for global pages).
3. CPU receiving the IPI executes a DMB and CLREX (part of the exception
return code already).
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Rob Herring [Mon, 25 Mar 2013 16:02:48 +0000 (17:02 +0100)]
ARM: 7682/1: cache-l2x0: fix masking of RTL revision numbering and set_debug init
Commit b8db6b8 (ARM: 7547/4: cache-l2x0: add support for Aurora L2 cache
ctrl) moved the masking of the part ID which caused the RTL version to be
lost. Commit 6248d06 (ARM: 7545/1: cache-l2x0: make outer_cache_fns a
field of l2x0_of_data) changed how .set_debug is initialized. Both commits
break commit 74ddcdb (ARM: 7608/1: l2x0: Only set .set_debug
on PL310 r3p0 and earlier) which uses the RTL version to conditionally set
.set_debug function pointer. Commit b8db6b8 also caused the printed cache
ID to be missing the version information.
Fix this by reverting how the part number is masked so the RTL version
info is maintained. The cache-id-part DT property does not set the RTL
bits so masking them should have no effect. Also, re-arrange the order
of the function pointer init so the .set_debug function can be overridden.
Reported-by: Paolo Pisati <paolo.pisati@canonical.com> Signed-off-by: Rob Herring <rob.herring@calxeda.com> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> Cc: Yehuda Yitschak <yehuday@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Russell King [Wed, 3 Apr 2013 15:33:26 +0000 (16:33 +0100)]
ARM: iWMMXt: always enable iWMMXt support with PJ4 CPUs
Jason Cooper reports these build errors:
arch/arm/kernel/built-in.o: In function `iwmmxt_do':
/.../arch/arm/kernel/pj4-cp0.c:36: undefined reference to `iwmmxt_task_release'
/.../arch/arm/kernel/pj4-cp0.c:40: undefined reference to `iwmmxt_task_switch'
make: *** [vmlinux] Error 1
This is caused because the PJ4 code explicitly references the iWMMXt
code, but doesn't require it to be built. Fix this by ensuring that
iWMMXt is always enabled with PJ4.
Reported-by: Jason Cooper <jason@lakedaemon.net> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The platform_enable/disable callbacks in board files for VENC omap_dss_device
instances don't do anything. Hence, we can remove these callbacks from the VENC
driver.
projects / mirror_ubuntu-disco-kernel.git / log