Imre Deak [Fri, 6 Oct 2023 13:37:13 +0000 (16:37 +0300)]
drm/i915/dp: Use connector DSC DPCD in i915_dsc_fec_support_show()
Use the connector's DSC DPCD capabilities in i915_dsc_fec_support_show()
instead of the version stored in the encoder. Atm the two are identical,
but a follow-up patch will store the (MST) connector specific version
in the connector.
Imre Deak [Tue, 10 Oct 2023 11:25:03 +0000 (14:25 +0300)]
drm/i915/dp_mst: Set connector DSC capabilities and decompression AUX
Similarly to eDP and SST-DP connectors read out the DSC capabilities for
MST connectors as well. Atm these will match the root port's DSC caps
and only used after a follow-up change enables the decompression for
each stream separately (vs. the current way of enabling it only globally
in the first branch device downstream of the root port).
Imre Deak [Wed, 11 Oct 2023 17:16:05 +0000 (20:16 +0300)]
drm/i915/dp: Store DSC DPCD capabilities in the connector
In an MST topology the DSC capabilities are specific to each connector,
retrieved either from the sink if it decompresses the stream, or from a
branch device between the source and the sink in case this branch device
does the decompression. Accordingly each connector needs to cache its
own DSC DPCD and FEC capabilities, along with the AUX device through
which the decompression can be enabled. This patch prepares for that by
storing the capabilities and the DSC AUX device in the connector, for
now these just matching the version stored in intel_dp. The follow-up
patches will convert all users to look up these in the connector instead
of intel_dp, after which the intel_dp copies are removed.
v2:
- Rebased on intel_edp_get_dsc_sink_cap() addition in previous patch.
v3:
- Rebased on read-out fix for eDP in previous patch.
Imre Deak [Wed, 11 Oct 2023 17:16:04 +0000 (20:16 +0300)]
drm/i915/dp: Sanitize DPCD revision check in intel_dp_get_dsc_sink_cap()
Check only the eDP or the DP specific DPCD revision depending on the
sink type. Pass the corresponding revision to the function, which allows
getting the DSC caps of a branch device (in an MST topology, which has
its own DPCD and so DPCD revision).
While at it use DP_DPCD_REV_14 instead of open coding it and for clarity
add a separate function to read out the DSC capability on eDP.
v2:
- Use DP_DPCD_REV_14 instead of open coding it. (Stan)
- Check EDP_DCPD_REV/DPCD_REV in a clearer way. (Ville)
v3:
- Fix the read-out for eDP in intel_dp_detect().
The display engine does not snoop the caches so we should mark
the DSB command buffer as I915_CACHE_NONE.
i915_gem_object_create_internal() always gives us I915_CACHE_LLC
on LLC platforms. And to make things 100% correct we should also
clflush at the end, if necessary.
Note that currently this is a non-issue as we always write the
command buffer through a WC mapping, so a cache flush is not actually
needed. But we might actually want to consider a WB mapping since
we also end up reading from the command buffer (in the indexed
reg write handling). Either that or we should do something else
to avoid those reads (might actually be even more sensible on DGFX
since we end up reading over PCIe). But we should measure the overhead
first...
Anyways, no real harm in adding the belts and suspenders here so
that the code will work correctly regardless of how we map the
buffer. If we do get a WC mapping (as we request)
i915_gem_object_flush_map() will be a nop. Well, apart form
a wmb() which may just flush the WC buffer a bit earlier
than would otherwise happen (at the latest the mmio accesses
would trigger the WC flush).
Ville Syrjälä [Mon, 9 Oct 2023 13:22:01 +0000 (16:22 +0300)]
drm/i915/dsb: Allocate command buffer from local memory
Using system memory for the DSB command buffer doesn't appear to work.
On DG2 it seems like the hardware internally replaces the actual memory
reads with zeroes, and so we end up executing a bunch of NOOPs instead
of whatever commands we put in the buffer. To determine that I measured
the time it takes to execute the instructions, and the results are
always more or less consistent with executing a buffer full of NOOPs
from local memory.
Another theory I considered was some kind of cache coherency issue.
Looks like i915_gem_object_pin_map_unlocked() will in fact give you a
WB mapping for system memory on DGFX regardless of what mapping mode
was requested (WC in case of the DSB code). But clflush did not
change the behaviour at all, so that theory seems moot.
On DG1 it looks like the hardware might actually be fetching data from
system memory as the logs indicate that we just get underruns. But that
is equally bad, so doesn't look like we can really use system memory on
DG1 either.
Thus always allocate the DSB command buffer from local memory on
discrete GPUs.
Hans de Goede [Wed, 20 Sep 2023 19:56:12 +0000 (21:56 +0200)]
drm/i915/vlv_dsi: Add DMI quirk for backlight control issues on Lenovo Yoga Tab 3 (v2)
On the Lenovo Yoga Tab 3 Pro YT3-X90F there are 2 issues with the backlight
on/off MIPI sequences:
1. The backlight on sequence has an I2C MIPI sequence element which uses
bus 0, but there is a bogus I2cSerialBus resource under the GPU in
the DSDT which causes i2c_acpi_find_adapter() to pick the wrong bus.
2. There is no backlight off sequence, causing the backlight to stay on.
Add a DMI quirk fixing both issues.
v2:
- Add Closes tag to gitlab issue with drm.debug=0xe, VBT info
Hans de Goede [Wed, 20 Sep 2023 19:56:11 +0000 (21:56 +0200)]
drm/i915/vlv_dsi: Add DMI quirk for wrong I2C bus and panel size on Lenovo Yoga Tablet 2 series (v3)
On the Lenovo Yoga Tablet 2 830 / 1050 there are 2 problems:
1. The I2C MIPI sequence elements reference bus 3. ACPI has I2C1 - I2C7
which under Linux become bus 0 - 6. And the MIPI sequence reference
to bus 3 is indented for I2C3 which is bus 2 under Linux.
This leads to errors like these:
[ 178.244049] i2c_designware 80860F41:03: controller timed out
[ 178.245703] i915 0000:00:02.0: [drm] *ERROR* Failed to xfer payload of size (1) to reg (169)
There are 3 timeouts when the panel is on, delaying
waking up the screen on a key press by 3 seconds.
Note mipi_exec_i2c() cannot just subtract 1 from the bus
given in the I2C MIPI sequence element. Since on other
devices the I2C bus-numbers used in the MIPI sequences do
actually start at 0.
2. width_/height_mm contain a bogus 192mm x 120mm size. This is
especially a problem on the 8" 830 version which uses a 10:16
portrait screen where as the bogus size is 16:10.
Add a DMI quirk to override the I2C bus and the panel size with
the correct values.
Note both the 10" 1050 models as well as the 8" 830 models use the same
mainboard and thus the same DMI strings. The 10" 1050 uses a 1920x1200
landscape screen, where as the 8" 830 uses a 1200x1920 portrait screen,
so the quirk handling uses the display resolution to detect the model.
v2:
- Also override i2c_bus_num to fix mipi_exec_i2c() timeouts
v3:
- Add Closes tag to gitlab issue with drm.debug=0xe, VBT info
Hans de Goede [Wed, 20 Sep 2023 19:56:10 +0000 (21:56 +0200)]
drm/i915/vlv_dsi: Add DMI quirk for wrong panel modeline in BIOS on Asus TF103C (v3)
Vtotal is wrong in the BIOS supplied modeline for the DSI panel on
the Asus TF103C leading to the last line of the display being shown
as the first line.
The factory installed Android has a hardcoded modeline in its kernel,
causing it to not suffer from this BIOS bug;
and the Android boot-splash which uses the EFI FB which does have this bug
has the last line all black causing the bug to not be visible.
This commit introduces a generic DMI based quirk mechanism to vlv_dsi for
doing various fixups, and uses this to correct the modeline.
v2:
- s/mode_fixup/dmi_quirk/ to make the new DMI quirk mechanism more generic
- Add a comment with the old and new modelines to the patch and commit msg
v3:
- Add Closes tag to gitlab issue with drm.debug=0xe, VBT info
Suraj Kandpal [Mon, 9 Oct 2023 09:55:37 +0000 (15:25 +0530)]
drm/i915/hdcp: Move common message filling function to its own file
Create a new file intel_hdcp_gsc_message that contain functions
which fill the hdcp messages we send to gsc cs this refactor will
help us reuse code for Xe later on
--v2
-add the missed file for proper build
--v3
-use forward declarations instead of #includes [Jani]
--v4
-move linux/err.h to intel_hdcp_gsc_message.c from
intel_hdcp_gsc_message.h [Jani]
--v5
-move linux include on top of drm includes [Uma]
Jani Nikula [Wed, 11 Oct 2023 07:29:04 +0000 (10:29 +0300)]
drm/i915: enable W=1 warnings by default
We enable a bunch more compiler warnings than the kernel
defaults. However, they've drifted to become a unique set of warnings,
and have increasingly fallen behind from the W=1 set.
Align with the W=1 warnings from scripts/Makefile.extrawarn for clarity,
by copy-pasting them with s/KBUILD_CFLAGS/subdir-ccflags-y/ to make it
easier to compare in the future.
Some of the -Wextra warnings do need to be disabled, just like in
Makefile.extrawarn, but take care to not disable them for W=2 or W=3
builds, depending on the warning.
v2: Add back some -Wextra warning disables (Nathan)
Jani Nikula [Wed, 11 Oct 2023 07:29:03 +0000 (10:29 +0300)]
drm/i915: drop -Wall and related disables from cflags as redundant
The kernel top level Makefile, and recently scripts/Makefile.extrawarn,
have included -Wall, and the disables -Wno-format-security and
$(call cc-disable-warning,frame-address,) for a very long time. They're
redundant in our local subdir-ccflags-y and can be dropped.
drm/i915/cx0: Only clear/set the Pipe Reset bit of the PHY Lanes Owned
Currently, with MFD/pin assignment D, the driver clears the pipe reset bit
of lane 1 which is not owned by display. This causes the display
to block S0iX.
By not clearing this bit for lane 1 and keeping whatever default, S0ix
started to work. This is already what the driver does at the end
of the phy lane reset sequence (Step#8)
Bspec: 65451 Fixes: 619a06dba6fa ("drm/i915/mtl: Reset only one lane in case of MFD") Cc: Mika Kahola <mika.kahola@intel.com> Cc: Gustavo Sousa <gustavo.sousa@intel.com> Signed-off-by: Khaled Almahallawy <khaled.almahallawy@intel.com> Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231005001310.154396-1-khaled.almahallawy@intel.com
Add a wrapper around intel_step_name that takes in driver data as an
argument. This wrapper will help maintain compatibility with the
proposed xe driver.
Ville Syrjälä [Mon, 9 Oct 2023 14:58:28 +0000 (17:58 +0300)]
drm/i915: Fix VLV color state readout
VLV was missed when the color.get_config() hook was added.
Remedy that.
Not really sure what the final plan here was since a bunch of
color related readout was left in intel_display.c anyway,
but that's for anothr day to figure out...
Remove redundant intel_connector NULL check. Having it here just
creates further confusion and also the variable already gets
dereferenced before the aforementioned NULL check
Ville Syrjälä [Wed, 4 Oct 2023 15:56:03 +0000 (18:56 +0300)]
drm/i915: Simplify snps/c10x DPLL state checker calling convetion
Passing in the atomic state + crtc state is a bit weird. The latter
can be just the crtc (which is the normal calling convention used
in a lot of other places).
Ville Syrjälä [Thu, 5 Oct 2023 12:27:13 +0000 (15:27 +0300)]
drm/i915: Simplify watermark state checker calling convention
There is never any reason to pass in both the crtc and its state
as one can always dig out the crtc from its state. But for more
consistency across the whole state checker let's just pass the
overall atomic state+crtc here as well.
Ville Syrjälä [Wed, 4 Oct 2023 15:55:57 +0000 (18:55 +0300)]
drm/i915: Stop clobbering old crtc state during state check
The state checker overwrites the old crtc state with the
current hardware state. While that does save a kmalloc() it seems
rather dubious as there might still be something that we need
in the old crtc state.
Stop doing that and just allocate a temporary state for the state
checker. Should the extra malloc during the commit phase turn out
too annoying we could of course preallocate one for each crtc, but
let's proceed with the straightforward approch for now.
And while at it let's mark the new crtc state as const to make
sure the state checker doesn't mess it up.
Ville Syrjälä [Wed, 4 Oct 2023 15:55:56 +0000 (18:55 +0300)]
drm/i915/psr: Unify PSR pre/post plane update hooks
intel_psr_pre_plane_update() operates on a per-crtc level, whereas
intel_psr_post_plane_update() operates on the whole atomic commit,
for no real reason that I can see. Adjust intel_psr_post_plane_update()
to match the intel_psr_pre_plane_update() approach.
Ville Syrjälä [Tue, 3 Oct 2023 19:42:51 +0000 (22:42 +0300)]
drm/i915/fbc: Remove ancient 16k plane stride limit
The 16k max plane stride limit seems to be originally from
i965gm, and no explicit limit has been specified since (g4x+).
So let's assume the max plane stride itself is a suitable limit
also for the more recent FBC hardware.
In fact even for i965gm the max X-tiled stride is also 16k so
technically we don't need the check there either, but let's
keep it there anyway since it's explicitly mentioned in the
spec. Gen2/3 have more strict limits checked separately.
drm/i915/pmu: Use local64_try_cmpxchg in i915_pmu_event_read
Use local64_try_cmpxchg instead of local64_cmpxchg (*ptr, old, new) == old
in i915_pmu_event_read. x86 CMPXCHG instruction returns success in ZF flag,
so this change saves a compare after cmpxchg (and related move instruction
in front of cmpxchg).
Also, try_cmpxchg implicitly assigns old *ptr value to "old" when cmpxchg
fails. There is no need to re-read the value in the loop.
No functional change intended.
Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Cc: David Airlie <airlied@gmail.com> Cc: Daniel Vetter <daniel@ffwll.ch> Signed-off-by: Uros Bizjak <ubizjak@gmail.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230703150859.6176-1-ubizjak@gmail.com
Uma Shankar [Fri, 29 Sep 2023 07:43:06 +0000 (13:13 +0530)]
drm/i915/display: Created exclusive version of vga decode setup
Current vga arbiter implementation in i915 needs a re-design.
The current approach would cause real problems if anyone actually
needs to talk another GPU using legacy VGA resources.
The main issue is that X becomes a slideshow if it thinks there
are multiple GPUs that have VGA decoding enabled as it insists
on adjusting the VGA routing pretty much for every little operation
involving any of the GPUs.
The cleanup will be planned for i915. Meanwhile to focus on Xe
upstreaming and have a cleaner separation, the said functionality
is being moved to a different file exclusive for i915. Xe driver
will re-use rest of the display code from i915.
v2: Addressed Jani Nikula's review comments.
v3: Dropped a duplicate function (Jani)
v4: Updated commit message with reasoning as sugested by Ville.
Imre Deak [Fri, 29 Sep 2023 15:49:29 +0000 (18:49 +0300)]
drm/i915/dp_mst: Make sure pbn_div is up-to-date after sink reconnect
Atm the MST encoder config computation may use an out-of-date pbn_div
value, if the sink is unplugged and a sink is replugged with different
link rate/lane count capabilities. The current way of reinitializing
pbn_div depends on pbn_div getting cleared via intel_atomic_check() ->
drm_dp_mst_atomic_check() ->
drm_dp_mst_atomic_check_payload_alloc_limits(), however the clearing
won't happen if the sink got unplugged (and hence
drm_dp_mst_topology_mgr::mst_state being false).
To fix the above, simply update pbn_div unconditionally during config
computation, making pbn_div always match the link rate and lane count.
This is to eliminate all cases of "*ERROR* LSPCON mode hasn't settled",
followed by link training errors. Intel engineers recommended increasing
this timeout and that does resolve the issue.
On some CometLake-based device designs the Parade PS175 takes more than
400ms to settle in PCON mode. 100 reboot trials on one device resulted
in a median settle time of 440ms and a maximum of 444ms. Even after
increasing the timeout to 500ms, 2% of devices still had this error. So
this increases the timeout to 800ms.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/9443 Signed-off-by: Pablo Ceballos <pceballos@google.com> Signed-off-by: Niko Tsirakis <ntsirakis@google.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231002204709.761089-1-ntsirakis@google.com
Ville Syrjälä [Tue, 3 Oct 2023 20:06:19 +0000 (23:06 +0300)]
drm/i915: Introduce for_each_shared_dpll()
No one really cares how we store the shared_dplls. Currently
it happens to be an array, but we could change that to a more
flexible scheme at some point. Hide the implementation details
behind an iterator macro.
The slight downside is the pll variable moving out of the
loop scope, but maybe someday soon we'll start to convert
everything over to having declarations within for-statements...
Ville Syrjälä [Tue, 3 Oct 2023 20:06:18 +0000 (23:06 +0300)]
drm/i915: Decouple I915_NUM_PLLS from PLL IDs
Stop assuming the size of PLL ID based bitmask is restricted
to I915_NUM_PLLS bits. This is the last thing coupling the
two things together and thus artificially limiting PLL IDs.
We could just pass any arbitrary (large enough) size to
for_each_set_bit() and be done with it, but the WARN
requiring the caller to not pass in a bogus bitmask seems
potentially useful to keep around. So let's just calculate
the full bitmask on the spot.
And while at it let's assert that the PLL IDs will fit
into the bitmask we use for them.
TODO: could also get rid of I915_NUM_PLLS entirely and just
dynamically allocate i915->shared_dplls[] and state->shared_dpll[].
But that would involve error handling in the modeset init path. Uff.
Ville Syrjälä [Tue, 3 Oct 2023 20:06:17 +0000 (23:06 +0300)]
drm/i915: Stop requiring PLL index == PLL ID
There's no good reason to keep around this PLL index == PLL ID
footgun. Get rid of it.
Both i915->shared_dplls[] and state->shared_dpll[] are indexed
by the same thing now, which is just the index we get at
initialization from dpll_mgr->dpll_info[]. The rest is all about
PLL IDs now.
v2: Add pll->index to mimic drm_crtc & co.
Remove the comment saying ID should match the index
v3: s/i/pll->index/ in debugfs loop (Jani)
Jani Nikula [Tue, 3 Oct 2023 12:42:09 +0000 (15:42 +0300)]
drm/i915: separate display runtime info init
Move display related functionality from intel_device_info_runtime_init()
to intel_display_device_info_runtime_init() and call the latter from the
top level.
drm/i915/lnl: possibility to enable FBC on first three planes
In LNL onwards, FBC can be associated to the first three planes.
FBC will be enabled on planes first come first served basis
until the userspace can select one of these FBC capable planes
explicitly.
v2:
- avoid fbc->state.plane check in intel_fbc_check_plane (Ville)
- simplify plane binding register writes (Matt)
- Update the subject to reflect that fbc can be enabled only in
the first three planes (Matt)
v3:
- use icl_is_hdr_plane(), use wrapper macro for plane binding
register access, comments update and patch split (Ville)
v4:
- update to the plane binding register access macro
Dave Airlie [Mon, 2 Oct 2023 20:02:29 +0000 (06:02 +1000)]
Merge tag 'drm-intel-gt-next-2023-09-28' of git://anongit.freedesktop.org/drm/drm-intel into drm-next
Driver Changes:
Fixes/improvements/new stuff:
- Fix TLB-Invalidation seqno store [mtl] (Alan Previn)
- Force a reset on internal GuC error [guc] (John Harrison)
- Define GSC fw [gsc] (Daniele Ceraolo Spurio)
- Update workaround 14016712196 [dg2/mtl] (Tejas Upadhyay)
- Mark requests for GuC virtual engines to avoid use-after-free (Andrzej Hajda)
- Add Wa_14015150844 [dg2/mtl] (Shekhar Chauhan)
- Prevent error pointer dereference (Dan Carpenter)
- Add Wa_18022495364 [tgl,adl,rpl] (Dnyaneshwar Bhadane)
- Fix GuC PMU by moving execlist stats initialization to execlist specific setup (Umesh Nerlige Ramappa)
- Fix PXP firmware load [pxp/mtl] (Alan Previn)
- Fix execution/context state of PXP contexts (Alan Previn)
- Limit the length of an sg list to the requested length (Matthew Wilcox)
- Fix reservation address in ggtt_reserve_guc_top [guc] (Javier Pello)
- Add Wa_18028616096 [dg2] (Shekhar Chauhan)
- Get runtime pm in busyness worker only if already active [guc/pmu] (Umesh Nerlige Ramappa)
- Don't set PIPE_CONTROL_FLUSH_L3 for aux inval (Nirmoy Das)
Future platform enablement:
- Fix and consolidate some workaround checks, make others IP version based [mtl] (Matt Roper)
- Replace Meteorlake subplatforms with IP version checks (Matt Roper)
- Adding DeviceID for Arrowlake-S under MTL [mtl] (Nemesa Garg)
- Run relevant bits of debugfs drop_caches per GT (Tvrtko Ursulin)
Miscellaneous:
- Remove Wa_15010599737 [dg2] (Shekhar Chauhan)
- Align igt_spinner_create_request with hangcheck [selftests] (Jonathan Cavitt)
- Remove pre-production workarounds [dg2] (Matt Roper)
- Tidy some workaround definitions (Matt Roper)
- Wait longer for tasks in migrate selftest [gt] (Jonathan Cavitt)
- Skip WA verification for GEN7_MISCCPCTL on DG2 [gt] (Andrzej Hajda)
- Silence injected failure in the load via GSC path [huc] (Daniele Ceraolo Spurio)
- Refactor deprecated strncpy (Justin Stitt)
- Update RC6 mask for mtl_drpc [debugfs/mtl] (Badal Nilawar)
- Remove a static inline that requires including i915_drv.h [gt] (Jani Nikula)
- Remove inlines from i915_gem_execbuffer.c [gem] (Jani Nikula)
- Remove gtt_offset from stream->oa_buffer.head/.tail [perf] (Ashutosh Dixit)
- Do not disable preemption for resets (Tvrtko Ursulin)
Let's introduce the basic documentation about CCS.
While doing that, also removed the legacy execution flag name. That flag
simply doesn't exist for CCS and it is not needed on current context
submission. Those flag names are only needed on legacy context,
while on new ones we only need to pass the engine ID.
It is worth mention that this documentation should probably live with
the engine definitions rather than in the i915.rst file directly and
that more updates are likely need in this section. But this should
come later.
v2: Overall improvements from Matt and Tvrtko.
Fixes: 944823c94639 ("drm/i915/xehp: Define compute class and engine") Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Sushma Venkatesh Reddy <sushma.venkatesh.reddy@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230926165107.23440-1-rodrigo.vivi@intel.com
Jani Nikula [Tue, 12 Sep 2023 11:06:28 +0000 (14:06 +0300)]
drm/i915: define I915 during i915 driver build
The xe driver will reuse i915 display code by compiling it separately as
part of xe. We'll want to be able to distinguish between building the
i915 display code for i915 and xe. Define I915 when building i915.
Cc: David Airlie <airlied@gmail.com> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Dave Airlie <airlied@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/97558201836115b91cbe32840239df855d0c2e4c.1694514689.git.jani.nikula@intel.com
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