Ville Syrjälä [Wed, 25 Jan 2023 18:52:31 +0000 (20:52 +0200)]
drm/i915: Undo rmw damage to gen3 error interrupt handler
The gen2/gen3 irq code is supposed to be identical apart
from the 32bit vs. 16bit access width. The recent change
to intel_de_rmw() ruined that symmetry. Restore it to avoid
needless mental gymnastics when comparing the two codepaths.
And while at it remove the extra eir!=0 check that somehow
ended up in the gen2 codepath only.
Ville Syrjälä [Wed, 25 Jan 2023 18:52:30 +0000 (20:52 +0200)]
drm/i915: Mark FIFO underrun disabled earlier
At least on some platforms (tested on ctg) the way
vgacon does screen blanking seems to flag constant
FIFO underruns, which means we have to be prepared
for them while the driver is loading. Currently
there is a time window between drm_crtc_init() and
intel_sanitize_fifo_underrun_reporting() during
which FIFO underrun reporting is in fact marked as
enabled. Thus we may end up mistakenly detecting
these bogus underruns during driver init.
Close the race by marking FIFO underrun reporting
as disabled prior to even registering the crtc.
intel_sanitize_fifo_underrun_reporting()/etc. will
re-enable it later if needed.
Ville Syrjälä [Wed, 22 Feb 2023 15:14:54 +0000 (17:14 +0200)]
drm/i915/audio: Track audio state per-transcoder
The audio logic lives in the transcoder rather than the pipe,
so start tracking it like that.
This is only really important for bigjoiner cases where tracking
by pipe doesn't work at all since intel_audio_codec_{enable,disable}()
won't even be called for the slave pipe. This means the state
checker won't find the ELD for the slave pipe and gets upset.
The PD->has_audio readout does currently work since that gets
read out from the same transcoder for both pipes.
For other cases this doesn't actually matter since it's only
the normal pipe transcoders that are audio capable, whereas
the more special transcoders (EDP/DSI) are not.
Ville Syrjälä [Mon, 13 Feb 2023 22:52:58 +0000 (00:52 +0200)]
drm/i915: Remove pointless register read
We just wrote the EDP transcoder's VTOTAL register a few lines
earlier, so instead of reading it back out again let's just
generate the same value for the transocder B/C register.
Ville Syrjälä [Mon, 13 Feb 2023 22:52:57 +0000 (00:52 +0200)]
drm/i915: Sprinkle some FIXMEs about TGL+ DSI transcoder timing mess
The DSI code has some local hacks to program TRANS_VBLANK on
TGL+ (ICL DSI transcoders didn't have this register). That
will not work when we need to start using the delayed vblank
(for DSB purposes). Too lazy to figure out what the is going
on there, so just sprinkle FIXMEs in the hopes someone else
will spot them eventually.
v2: Only TRANS_{HBLANK,SET_CONTEXT_LATENCY} still no not
exist for DSI transcoders, only TRANS_VBLANK
Ville Syrjälä [Mon, 13 Feb 2023 22:52:56 +0000 (00:52 +0200)]
drm/i915: Configure TRANS_SET_CONTEXT_LATENCY correctly on ADL+
On TGL VBLANK.VBLANK_START was the mechanism by which we can
delay the pipe's internal vblank in relation to the transcoder's
vblank. On ADL+ that no longer does anything. Instead we must
now use the new TRANS_SET_CONTEXT_LATENCY register. Program it
accordingly.
And since VBLANK.VBLANK_START is no longer used by the hardware
on ADL+ let's just zero it out to make it stand out in register
dumps. Seeing the zeroed value should hopefully remind people
to check the other register instead.
The PSR code has no business mucking around with the
vblank delay. Currently nothing that depends on knowing
the exact vblank start scanline (eg. vblank evasion)
is aware of this and so will not work correctly.
The w/a seems to be for pre-production hw only, so let's
just nuke it.
Define the contents of the transcoder timing registers using
REG_GENMASK() & co. For ease of maintenance let's just define
the bitmasks with the full 16bit width (also used by the
current hand rolled stuff) even though not all bits are actually
used. None of the unsued bits have ever contained anything.
Jani spotted that the CRT load detection code did use narrower
bitmasks, so that is now going to change. But that is fine
since any garbage in the high bits would have been caught by
the state checker that always used the full 16bit masks.
Ville Syrjälä [Mon, 13 Feb 2023 22:52:52 +0000 (00:52 +0200)]
drm/i915: Define the "unmodified vblank" interrupt bit
On TGL+ the normal "start of vblank" interrupt is the pipe's
(potentially delayed) version. Add the new bit for the
transcoder's "unmodified" vblank so I don't have to dig it
out from bspec every time.
Ville Syrjälä [Mon, 13 Feb 2023 22:52:51 +0000 (00:52 +0200)]
drm/i915: Dump blanking start/end
With the delayed vblank we need to start knowing where
the blanking periods start. So let's start dumping
out also the blanking start/end timings.
And while at it let's try to make that huge list of
numbers somewhat legible by indicating what each value
means. Also drop the 'type' since that doesn't really
mean anything for the crtc_ timings.
Ville Syrjälä [Mon, 13 Feb 2023 22:52:50 +0000 (00:52 +0200)]
drm/i915: s/PIPECONF/TRANSCONF/
Rename PIPECONF to TRANSCONF to make it clear what it actually
applies to.
While the usual convention is to pick the earliers name I think
in this case it's more clear to use the later name. Especially
as even the register offset is in the wrong range (0x70000 vs.
0x60000) and thus makes it look like this is per-pipe.
There is one place in gvt that's doing something with TRANSCONF
while iterating with for_each_pipe(). So that might not be doing
the right thing for TRANSCODER_EDP, dunno. Not knowing what it
does I left it as is to avoid breakage.
Ville Syrjälä [Mon, 13 Feb 2023 22:52:49 +0000 (00:52 +0200)]
drm/i915: Give CPU transcoder timing registers TRANS_ prefix
Name the CPU transcoder timing registers TRANS_FOO rather than
just FOO. This is the modern name, after the pipe/transcoder split
happened. Makes it a bit more obvious whether you pass in a pipe or
a transcoder.
PIPESRC is a bit special as it's a pipe register, even though it
lives in the transcoder registers range (0x60000 instead of 0x70000).
And BCLRPAT I suppose is a transcoder register (since it has something
to do with the timing generator), but it doesn't even exist after gen4
so I left it to use the only name it ever had in bspec.
And while at it let's pass in the correct enum in few more
places why don't we. Although in all those places the distinction
doesn't matter.
Ville Syrjälä [Thu, 16 Feb 2023 23:13:11 +0000 (01:13 +0200)]
drm/i915: Fix platform default aux ch for skl
SKL/derivatives have DDI E but no AUX E, so we need to pick
another aux ch as the platform default. DDI E is more or less
the other half of DDI A, so we pick AUX A.
In all other cases we should have a corresponding aux ch for
each DDI.
Ville Syrjälä [Thu, 16 Feb 2023 23:13:09 +0000 (01:13 +0200)]
drm/i915: Restructure intel_bios_port_aux_ch()
Restructure intel_bios_port_aux_ch() to resemble the ddc_pin
counterpart, where the intel_bios.c stuff only deals with the
child device definition, and the platform default will come from
elsewhere.
This requires the introduction of AUX_CH_NONE as the value 0
is already taken to mean AUX_CH_A.
v2: Sort includes alphabetically (Ankit)
vCould we ask them to do a BIOS fix for all of them so that
we wouldn't keep getting these bug reports for each model
separately?
Ashutosh Dixit [Thu, 16 Feb 2023 16:49:44 +0000 (08:49 -0800)]
drm/i915/hwmon: Enable PL1 limit when writing limit value to HW
Previous documentation suggested that the PL1 power limit is always enabled
in HW. However we now find this not to be the case on some platforms (such
as ATSM). Therefore enable the PL1 power limit (by setting the enable bit)
when writing the PL1 limit value to HW.
Ashutosh Dixit [Thu, 16 Feb 2023 16:49:43 +0000 (08:49 -0800)]
drm/i915/hwmon: Replace hwm_field_scale_and_write with hwm_power_max_write
hwm_field_scale_and_write has a single caller hwm_power_write and is
specific to hwm_power_write but makes it appear that it is a general
function which can have multiple callers. Replace the function with
hwm_power_max_write which is specific to hwm_power_write and use that in
future patches where the function needs to be extended.
Ville Syrjälä [Wed, 15 Feb 2023 22:24:26 +0000 (00:24 +0200)]
drm/i915: Add a few more debugs for failed framebuffer creation
Most of the .fb_create() failure paths are annotated but there
are a few that seem capable of failing silently (well, higher
level code should print something, just not anything actually
useful). Drop a few more hints into the log to aid in debugging.
Ville Syrjälä [Wed, 15 Feb 2023 22:24:25 +0000 (00:24 +0200)]
drm/i915: Don't leak the DPT if drm_framebuffer_init() fails
We are failing to free the already allocated DPT if the final
drm_framebuffer_init() fails. That would require idr_alloc() to
fail, so not very likely, but let's add the cleanup code anyway.
Ville Syrjälä [Wed, 15 Feb 2023 14:00:21 +0000 (16:00 +0200)]
drm/i915: Include connector id+name in all backlight debugs/errors
With multi panel machines becoming more prominent it's also
important to know which connector's backlight we're talking
about. Include that information in all the backlight debug/error
messages.
Jani Nikula [Wed, 15 Feb 2023 14:19:10 +0000 (16:19 +0200)]
drm/i915/wm: remove ILK+ nop funcs fallback
Disabling ILK+ watermarks on failure to read the watermark levels dates
back to 2010 and commit 7f8a85698f5c ("drm/i915: Add the support of
memory self-refresh on Ironlake"), with no explanations, and it's been
copied and modified from that ever since. Finally drop it.
If the value are actually zero, the ilk_compute_*_wm() functions should
handle it gracefully.
Jani Nikula [Wed, 15 Feb 2023 14:19:06 +0000 (16:19 +0200)]
drm/i915/wm: move ILK watermark sanitization to i9xx_wm.[ch]
Move sanitize_watermarks() to i9xx_wm.[ch] and rename as
ilk_wm_sanitize(). The slightly unfortunate downside is having to expose
intel_atomic_check() from intel_display.c, but this declutters
intel_display.c nicely.
v2:
- Move to i9xx_wm.[ch] instead of intel_wm.[ch] (Ville)
drm/i915: Copy highest enabled wm level to disabled wm levels for gen >= 9
There was a specific SW workaround requested, which should prevent
some watermark issues happening, which requires copying highest
enabled wm level to those disabled wm levels(bit 31 is of course
still needs to be cleared).
This is related to different subsystems like PSR and others, which
may still consult a low power wm values ocassionally, despite those
are disabled. For that reason we need to keep sane values in
correspondent registers, even when those are disabled.
v2: Remove redundant WA for ICL and extend this WA for all platforms
starting from SKL, as it seems that we needed this anyway on
all of those(Ville Syrjälä)
drm/i915/display: Add 480 MHz CDCLK steps for RPL-U
A new step of 480MHz has been added on SKUs that have a RPL-U
device id to support 120Hz displays more efficiently. Use a
new quirk to identify the machine for which this change needs
to be applied.
Ville Syrjälä [Wed, 15 Feb 2023 13:56:16 +0000 (15:56 +0200)]
drm/i915: Make backlight setup debugs consistent
It's confusing to debug backlight issues when one can't
easily even tell what kind of backlight control was
selected. Sprinkle uniform debug messages to all the
backlight setup functions.
Also the one that was already there (ext_pwm) was
using drm_info() for some reason. I don't think that's
warranted so switch it to drm_dbg_kms() as well.
v2: Deal with AUX backlights too (Jani)
Move the VLV/CHV initial pipe debug there too (Jani)
Jani Nikula [Mon, 13 Feb 2023 19:59:59 +0000 (21:59 +0200)]
drm/i915/wm: add .get_hw_state to watermark funcs
Get rid of the if ladder in intel_modeset_setup_hw_state() and hide a
number of functions by adding a .get_hw_state() hook to watermark
functions. At least for now, combine the platform specific sanitization
to the hw state readouts on the relevant platforms instead of adding a
separate hook for that.
There's a functional change on PCH split platforms: If i9xx_wm_init()
fails to read plane latency and chooses the nop functions,
ilk_wm_get_hw_state() won't get called for readout. Add the
ilk_init_lp_watermarks() call on that path which now won't be called in
.get_hw_state(), as it looks like the only thing that could make a
difference.
Jani Nikula [Mon, 13 Feb 2023 19:59:57 +0000 (21:59 +0200)]
drm/i915/wm: move remaining watermark code out of intel_pm.c
Add new files intel_wm.[ch] and i9xx_wm.[ch] under display/ to hold
generic and pre-SKL watermark code, respectively. SKL+ watermark code
has already been split out to skl_watermark.[ch].
Use the _wm.[ch] naming for brevity; we may want to rename
skl_watermark.[ch] later accordingly.
Add new intel_wm_init() to call either skl_wm_init() or
i9xx_wm_init(i915) depending on the platform, the latter comprising of
the remains of intel_init_pm().
Sprinkle in some minor checkpatch fixes while moving the code.
Imre Deak [Wed, 8 Feb 2023 11:43:00 +0000 (13:43 +0200)]
drm/i915: Sanitize the display fused-off check on GEN7/8
Detecting in intel_device_info_runtime_init() that the display is fused
off or not present should only zero intel_runtime_info::pipe_mask, while
the other related masks will be accordingly zeroed later in the
function. Remove the redundant zeroing of the related fields on GEN7/8.
Imre Deak [Wed, 8 Feb 2023 11:42:59 +0000 (13:42 +0200)]
drm/i915/dgfx, mtl+: Disable display functionality if the display is not present
DG1/DG2 and MTL+ has added a new display-present HW flag. Check this
flag and if cleared, disable the driver's display functionality.
So far the missing check resulted in running the display initialization
sequence, and the WARNs below, due to the display register accesses
timing out:
v2: (Jani)
- Change "Display fused off" dmesg info to "Display not present".
- Zero only runtime->pipe_mask, other fields being zeroed based on this
later.
- Detect display presence already before the fused-off checks and only for
HAS_DISPLAY().
v3: Fix "preset" vs "present" typo.
Reported-and-tested-by: iczero <iczero@hellomouse.net> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/8015 Cc: iczero <iczero@hellomouse.net> Cc: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230208114300.3123934-4-imre.deak@intel.com
Imre Deak [Wed, 8 Feb 2023 11:42:58 +0000 (13:42 +0200)]
drm/i915: Move display power initialization during driver probing later
Determining whether the display engine is present on a platform happens
only in intel_device_info_runtime_init(). Initializing the display power
functionality depends on this condition, so move
intel_power_domains_init() later after the runtime init function has
been called.
The next patch fixing platforms without display, depends on this patch.
Imre Deak [Wed, 8 Feb 2023 11:42:57 +0000 (13:42 +0200)]
drm/i915: Fix system suspend without fbdev being initialized
If fbdev is not initialized for some reason - in practice on platforms
without display - suspending fbdev should be skipped during system
suspend, fix this up. While at it add an assert that suspending fbdev
only happens with the display present.
Ville Syrjälä [Wed, 8 Feb 2023 01:55:08 +0000 (03:55 +0200)]
drm/i915: Use encoder->devdata in eDP init
Since we now populate encoder->devdata for all DP capable
platforms we can consult it directly during the eDP
connector init instead of taking a detour via some global
list/array.
Unfortunately we can't quite get rid of
intel_dp_is_port_edp() since it's still used by the higher
level ilk/vlv/chv output setup code.
Ville Syrjälä [Tue, 14 Feb 2023 07:38:18 +0000 (09:38 +0200)]
drm/i915: Iterate all child devs in intel_bios_is_port_present()
Instead of consulting vbt.ports[] lets just go through the
whole child device list to check whether a specific port
was declared by the VBT or not.
Note that this doesn't change anything wrt. detecting duplicate
child devices with the same port as vbt.ports[] would also always
contain exactly one of the duplicates.
v2: Include a is_port_valid() check to deal with some broken VBTs
Mention something about duplicate port detection (Jani)
Ville Syrjälä [Wed, 8 Feb 2023 01:55:06 +0000 (03:55 +0200)]
drm/i915: Pass devdata to intel_bios_port_aux_ch()
Currently intel_bios_port_aux_ch() digs out the devdata
(VBT child device info) from the vbt.ports[] array. We
need to get rid of that, so just pass in the correct
encoder->devdata (now that we have it also for g4x+ ports)
directly.
Ville Syrjälä [Wed, 8 Feb 2023 01:55:05 +0000 (03:55 +0200)]
drm/i915: Populate encoder->devdata for g4x+ DP/HDMI ports
Let's make encoder->devdata (the VBT information for the port)
available on g4x+ platforms as well. Much easier when you can
just grab it there instead of trying to find it from some global
list array based on the port.
Note that (unlike DDI platforms) we don't currently require
that each DP/HDMI port is actually declared in VBT. Perhaps
in the future we may want to rethink that, but for now just
stick in a debug+FIXME as a reminder.
Ville Syrjälä [Wed, 8 Feb 2023 01:55:04 +0000 (03:55 +0200)]
drm/i915: Consult the registered encoders for the ICL combo PHY w/a
Display WA #1178 calls us to tweak some magic bits when doing AUX
to an external combo PHY port. Instead of looking to see if the VBT
has declared such a port (which could in theory even alias with a
declared eDP port on the same PHY) just check the real situation
based on the registered encoders.
The only slight chicken vs. egg situation here is during output
probing. But typically we'd register the eDP ports first and so
once we get to probe anything external on the combo PHY we have
already determined if it's eDP or not.
Ville Syrjälä [Wed, 8 Feb 2023 01:55:03 +0000 (03:55 +0200)]
drm/i915: Replace intel_bios_is_port_hpd_inverted() with intel_bios_encoder_hpd_invert()
intel_bios_is_port_hpd_inverted() is only used on bxt/glk on
which we always have encoder->devdata available. So consult
that instead of digging around in vbt.ports[].
And rename the function to match the common pattern.
Ville Syrjälä [Wed, 8 Feb 2023 01:55:02 +0000 (03:55 +0200)]
drm/i915: Replace intel_bios_is_lane_reversal_needed() with intel_bios_encoder_lane_reversal()
The sole user of intel_bios_is_lane_reversal_needed() has
the devdata already located, so pass it in directly instead
of digging it again from vbt.ports[].
And rename the function to follow the common pattern for
these things.
Ville Syrjälä [Wed, 8 Feb 2023 01:55:01 +0000 (03:55 +0200)]
drm/i915: Replace intel_bios_is_lspcon_present() with intel_bios_encoder_is_lspcon()
We always have encoder->devdata available on the platforms
that can have LSPCON. So let's start looking there instead
of digging it out from vbt.ports[].
And let's rename the function to fit the common pattern
for these things.
Ville Syrjälä [Wed, 8 Feb 2023 01:54:59 +0000 (03:54 +0200)]
drm/i915: Pass the whole encoder to hotplug_enables()
bxt_hotplug_enables() needs to dig out not only the
hpd_pin but also the VBT child device info, so let's just
pass in the whole encoder to avoid having to look things
up multiple times.
Suraj Kandpal [Tue, 14 Feb 2023 05:20:17 +0000 (10:50 +0530)]
drm/i915/dp: Increase slice_height for DP
According VDSC spec 1.2a Section 3.8 Options for Slice
implies that 108 lines is an optimal slice height, but any
size can be used as long as vertical active
integer multiple and maximum vertical slice count requirements are met.
Bspec: 49259
--v3
-remove previous fallback code and return slice_height as 2 [Jani]
Ville Syrjälä [Thu, 9 Feb 2023 22:25:04 +0000 (00:25 +0200)]
drm/i915: Replace wm.max_levels with wm.num_levels and use it everywhere
Replaces wm.max_level with wm.num_levels, since that generally
results in nicer looking code (for-loops can be in standard
form etc.).
Also get rid of the two different wrappers we have for this
(ilk_wm_max_level() and intel_wm_num_levels()). They don't
really do anything for us other than potentially slow things
down if the compiler actually emits the function calls every
time (num_planes*num_wm_levels*higher_level_wm_function_calls
could be a big number). The watermark code already shows up
far too prominently in cpu profiles. Though I must admit that
I didn't look at the generated code this time.
Ville Syrjälä [Thu, 9 Feb 2023 00:32:50 +0000 (02:32 +0200)]
drm/i915: Populate wm.max_level for everyone
Switch ilk+ and skl+ platforms to also setting up
wm.max_level and remove a bunch of if ladders as a result.
There will be a tiny change in the debugfs on CHV machines
that have DVFS disabled in the BIOS. Presviously debugfs
would show the latency for the DVFS level as well, but
that will no longer be the case. Which is arguably better
as that number is absolutely meaningless when DVFS can't
be enabled anyway.
0349c41b0596 ("drm/i915/hwmon: Enable PL1 power limit") is incorrect and
caused a major regression on ATSM. The change enabled the PL1 power limit
but FW sets the default value of the PL1 limit to 0 which implies HW now
works at minimum power and therefore the lowest effective frequency. This
means all workloads now run slower resulting in even GuC FW load operations
timing out, rendering ATSM unusable.
A different solution to the original issue of the PL1 limit being disabled
on ATSM is needed but till that is developed, revert 0349c41b0596.
Jani Nikula [Tue, 7 Feb 2023 11:16:26 +0000 (13:16 +0200)]
drm/i915/bios: set default backlight controller index
With backlight controller set to -1 in intel_panel_init_alloc() to
distinguish uninitialized values, and controller later being set only if
it's present in VBT, we can end up with -1 for the controller:
[drm:intel_bios_init_panel [i915]] VBT backlight PWM modulation
frequency 200 Hz, active high, min brightness 0, level 255,
controller 4294967295
There's no harm if it happens on platforms that ignore controller due to
only one backlight controller being present, like on VLV above, but play
it safe.
Jani Nikula [Tue, 7 Feb 2023 12:40:24 +0000 (14:40 +0200)]
drm/i915/uncore: cast iomem to avoid sparse warning
drmm_add_action_or_reset() is unaware of __iomem and the pointer needs
to be a plain void *. Cast __iomem away and back while the pointer goes
through drmm.
Ville Syrjälä [Tue, 7 Feb 2023 06:43:36 +0000 (08:43 +0200)]
drm/i915: Populate encoder->devdata for DSI on icl+
We now have some eDP+DSI dual panel systems floating around
where the DSI panel is the secondary LFP and thus needs to
consult "panel type 2" in VBT in order to locate all the
other panel type dependant stuff correctly.
To that end we need to pass in the devdata to
intel_bios_init_panel_late(), otherwise it'll just assume
we want the primary panel type. So let's try to just populate
the vbt.ports[] stuff and encoder->devdata for icl+ DSI
panels as well.
We can't do this on older platforms as there we risk a DSI
port aliasing with a HDMI/DP port, which is a totally legal
thing as the DSI ports live in their own little parallel
universe.
Ville Syrjälä [Tue, 7 Feb 2023 06:43:35 +0000 (08:43 +0200)]
drm/i915: Fix VBT DSI DVO port handling
Turns out modern (icl+) VBTs still declare their DSI ports
as MIPI-A and MIPI-C despite the PHYs now being A and B.
Remap appropriately to allow the panels declared as MIPI-C
to work.
Matt Atwood [Wed, 1 Feb 2023 23:28:01 +0000 (15:28 -0800)]
drm/i915: Fix memory leaks in scatterlist
This patch fixes memory leaks on error escapes in i915_scatterlist.c
Fixes: c3bfba9a2225 ("drm/i915: Check for integer truncation on scatterlist creation") Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com> Reviewed-by: Harish Chegondi <harish.chegondi@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230201232801.123684-1-matthew.s.atwood@intel.com
Jonathan Gray [Mon, 6 Feb 2023 04:37:27 +0000 (15:37 +1100)]
drm/i915: Add another EHL pci id
described as "32 Execution Unit (EU) Super SKU" in:
Intel Atom x6000E Series, and Intel Pentium and Celeron N and
J Series Processors for IoT Applications
Datasheet, Volume 1
Document Number: 636112-1.6
Ashutosh Dixit [Fri, 3 Feb 2023 15:53:09 +0000 (07:53 -0800)]
drm/i915/hwmon: Enable PL1 power limit
Previous documentation suggested that PL1 power limit is always
enabled. However we now find this not to be the case on some
platforms (such as ATSM). Therefore enable PL1 power limit during hwmon
initialization.
Bspec: 51864
v2: Add Bspec reference (Gwan-gyeong)
v3: Add Fixes tag
Ville Syrjälä [Wed, 18 Jan 2023 16:30:31 +0000 (18:30 +0200)]
drm/i915/dsb: Introduce intel_dsb_finish()
Introduce a function to emits whatever commands we need
at the end of the DSB command buffer. For the moment we
only do the tail cacheline alignment there, but eventually
we might want to eg. emit an interrupt.
Ville Syrjälä [Wed, 18 Jan 2023 16:30:30 +0000 (18:30 +0200)]
drm/i915/dsb: Split intel_dsb_wait() from intel_dsb_commit()
Starting the DSB execution vs. waiting for it stop are two
totally different things. Split intel_dsb_wait() from
intel_dsb_commit() so that we can eventually allow the DSB
to execute asynchronously.
Jouni Högander [Mon, 23 Jan 2023 07:44:37 +0000 (09:44 +0200)]
drm/i915/fbdev: Implement fb_dirty for intel custom fb helper
After disconnecting damage worker from update logic it's left to fbdev
emulation implementation to have fb_dirty function. Currently intel
fbdev doesn't have it. This is causing problems to features (PSR, FBC,
DRRS) relying on dirty callback.
Implement simple fb_dirty callback to deliver notifications about updates
in fb console.
v4: Add proper Fixes tag and modify commit message
v3: Check damage clip
v2: Improved commit message and added Fixes tag
Fixes: f231af498c29 ("drm/fb-helper: Disconnect damage worker from update logic") Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Thomas Zimmermann <tzimmermann@suse.de> Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230123074437.475103-1-jouni.hogander@intel.com
Jani Nikula [Thu, 2 Feb 2023 12:04:52 +0000 (14:04 +0200)]
drm/i915/dmc: check incoming dmc id validity
Add validity checks for the dmc ids computed from pipe parameters in
intel_dmc_enable_pipe() and intel_dmc_disable_pipe(). It's slightly
difficult for humans and static analyzers alike to ensure the resulting
dmc ids are within bounds. Just check them and reject invalid ones.
Ville Syrjälä [Tue, 31 Jan 2023 00:21:27 +0000 (02:21 +0200)]
drm/i915: Expose SAGV state via debugfs
Since SAGV is controlled via unidirectional pcode commands
we have no way to query the current state. So instead let's
expose the last programmed state via debugfs. This way we
can at least know whether SAGV should be enabled or not
(which can be important to know when dealing with underruns/etc.).
Ville Syrjälä [Tue, 31 Jan 2023 00:21:26 +0000 (02:21 +0200)]
drm/i915: Keep sagv status updated on icl+
On icl+ SAGV is controlled by masking of the QGV points.
Reduce the QGV point mask to the same kind of enabled vs.
disable information that we had on previous platforms.
Will be useful in answering the question whether SAGV is
actually enabled or not.
Ville Syrjälä [Tue, 31 Jan 2023 00:21:25 +0000 (02:21 +0200)]
drm/i915: Introduce HAS_SAGV()
Introuce a HAS_SAGV() macro to answer the question whether
the platform in general supports SAGV. intel_has_sagv() will
keep on giving us the more specific answer whether the current
device supports SAGV or not.
Ville Syrjälä [Tue, 31 Jan 2023 00:21:24 +0000 (02:21 +0200)]
drm/i915: Don't do the WM0->WM1 copy w/a if WM1 is already enabled
Due to a workaround we have to make sure the WM1 watermarks block/lines
values are sensible even when WM1 is disabled. To that end we copy those
values from WM0.
However since we now keep each wm level enabled on a per-plane basis
it doesn't seem necessary to do that copy when we already have an
enabled WM1 on the current plane. That is, we might be in a situation
where another plane can only do WM0 (and thus needs the copy) but
the current plane's WM1 is still perfectly valid (ie. fits into the
current DDB allocation).
Skipping the copy could avoid reprogramming the plane's registers
needlessly in some cases.
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