Aleksey Makarov [Thu, 15 Jan 2015 13:11:09 +0000 (16:11 +0300)]
MIPS: OCTEON: Delete unused COP2 saving code
Commit 2c952e06e4f5 ("MIPS: Move cop2 save/restore to switch_to()")
removes assembler code to store COP2 registers. Commit a36d8225bceb ("MIPS: OCTEON: Enable use of FPU") mistakenly
restores it
Fixes: a36d8225bceb ("MIPS: OCTEON: Enable use of FPU") Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: David Daney <david.daney@cavium.com>
Patchwork: https://patchwork.linux-mips.org/patch/8937/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
David Daney [Thu, 15 Jan 2015 13:11:05 +0000 (16:11 +0300)]
MIPS: OCTEON: Save/Restore wider multiply registers in OCTEON III CPUs
The wide multiplier is twice as wide, so we need to save twice as much
state. Detect the multiplier type (CPU type) at start up and install
model specific handlers.
[aleksey.makarov@auriga.com:
conflict resolution,
support for old compilers]
Markos Chandras [Mon, 16 Feb 2015 15:13:11 +0000 (15:13 +0000)]
MIPS: boot: Provide more uImage options
Allow more compression algorithms as well as uncompressed uImage.bin
to be generated. An uncompressed image might be useful to rule out
problems in the decompression code in the bootloader or even speed
up the boot process at the expense of a bigger uImage file.
MIPS: ip22-gio: Remove legacy suspend/resume support
There are currently no gio device drivers that implement suspend/resume
and this patch removes the bus specific legacy suspend and resume callbacks.
This will allow us to eventually remove struct bus_type legacy suspend and
resume support altogether.
gio device drivers wanting to implement suspend and resume can use dev PM
ops which will work out of the box without further modifications necessary.
Manuel Lauss [Wed, 18 Feb 2015 10:01:56 +0000 (11:01 +0100)]
MIPS: Alchemy: Fix cpu clock calculation
The current code uses bits 0-6 of the sys_cpupll register to calculate
core clock speed. However this is only valid on Au1300, on all earlier
models the hardware only uses bits 0-5 to generate core clock.
This fixes clock calculation on the MTX1 (Au1500), where bit 6 of cpupll
is set as well, which ultimately lead the code to calculate a bogus cpu
core clock and also uart base clock down the line.
Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Reported-by: John Crispin <blogic@openwrt.org> Tested-by: Bruno Randolf <br1@einfach.org> Cc: stable@vger.kernel.org [v3.17+] Cc: Linux-MIPS <linux-mips@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/9279/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Steven J. Hill [Thu, 19 Feb 2015 16:18:52 +0000 (10:18 -0600)]
MIPS: Add set/clear CP0 macros for PageGrain register
Build set and clear macros for the PageGrain register.
Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9289/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Steven J. Hill [Thu, 19 Feb 2015 16:18:50 +0000 (10:18 -0600)]
MIPS: Usage and cosmetic cleanups of page table bits.
* Clean up white spaces and tabs.
* Get rid of remaining hardcoded values for calculating
shifts and masks.
* Get rid of redundant macro values.
* Do not use page table bits directly in #ifdef's.
Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9287/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Petr Malat [Fri, 12 Dec 2014 14:28:01 +0000 (15:28 +0100)]
MIPS: Provide correct siginfo_t.si_stime
Provide correct siginfo_t.si_stime on MIPS64
Bug description:
MIPS version of copy_siginfo() is not aware of alignment on platforms with
64-bit long integers, which leads to an incorrect si_stime passed to signal
handlers, because the last element (si_stime) of _sifields._sigchld is not
copied. If _MIPS_SZLONG is 64, then the _sifields starts at the offset of
4 * sizeof(int).
Patch description:
Use the generic copy_siginfo, which doesn't have this problem.
Ralf Baechle [Thu, 19 Feb 2015 12:47:20 +0000 (13:47 +0100)]
MIPS: Makefile: Pass -march option on Loongson3A cores
The loongson 3A cores do not select a suitable -march option so the build
system uses the default one from the toolchain. This may or may not be
suitable for a loongson 3A build. In order to avoid that, we explicitly set
a suitable -march option for that core. Furthermore, some very old
compilers don't support -march= at all and there is the possibility of
toolchain combinations such as GCC 4.9 and binutils 2.24 for which
-march=loongson3a will result in MIPS64 R2 code being generated but then
rejected by GAS. So treat the Longsoon 3A as an R2 CPU.
Markos Chandras [Thu, 8 Jan 2015 09:32:25 +0000 (09:32 +0000)]
MIPS: kernel: elf: Improve the overall ABI and FPU mode checks
The previous implementation did not cover all possible FPU combinations
and it silently allowed ABI incompatible objects to be loaded with the
wrong ABI. For example, the previous logic would set the FP_64 ABI as
the matching ABI for an FP_XX object combined with an FP_64A object.
This was wrong, and the matching ABI should have been FP_64A.
The previous logic is now replaced with a new one which determines
the appropriate FPU mode to be used rather than the FP ABI. This has
the advantage that the entire logic is much simpler since it is the FPU
mode we are interested in rather than the FP ABI resulting to code
simplifications. This also removes the now obsolete FP32XX_HYBRID_FPRS
option.
Cc: Matthew Fortune <Matthew.Fortune@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Markos Chandras [Wed, 3 Dec 2014 12:37:32 +0000 (12:37 +0000)]
MIPS: Make use of the ERETNC instruction on MIPS R6
The ERETNC instruction, introduced in MIPS R5, is similar to the ERET
one, except it does not clear the LLB bit in the LLADDR register.
This feature is necessary to safely emulate R2 LL/SC instructions.
However, on context switches, we need to clear the LLAddr/LLB bit
in order to make sure that an SC instruction from the new thread
will never succeed if it happens to interrupt an LL operation on the
same address from the previous thread.
Leonid Yegoshin [Wed, 3 Dec 2014 15:47:03 +0000 (15:47 +0000)]
MIPS: kernel: mips-r2-to-r6-emul: Add R2 emulator for MIPS R6
MIPS R6 removed quite a few R2 instructions. However, there
is plenty of <R6 userland code so we add an in-kernel emulator
so we can still be able to execute all R2 userland out there.
The emulator comes with a handy debugfs under /mips/ directory
(r2-emul-stats) to provide some basic statistics of the
instructions that are being emulated.
Below are some statistics from booting a minimal buildroot image:
Markos Chandras [Tue, 2 Dec 2014 09:46:19 +0000 (09:46 +0000)]
MIPS: Add LLB bit and related feature for the Config 5 CP0 register
The LLBIT (bit 4) in the Config5 CP0 register indicates the software
availability of the Load-Linked bit. This bit is only set by hardware
and it has the following meaning:
0: LLB functionality is not supported
1: LLB functionality is supported. The following feature are also
supported:
- ERETNC instruction. Similar to ERET but it does not clear the LLB
bit in the LLAddr register.
- CP0 LLAddr/LLB bit must be set
- LLbit is software accessible through the LLAddr[0]
This will be used later on to emulate R2 LL/SC instructions.
Markos Chandras [Wed, 26 Nov 2014 13:05:09 +0000 (13:05 +0000)]
MIPS: Emulate the new MIPS R6 B{L,G}T{Z,}{AL,}C instructions
MIPS R6 added the following four instructions which share the
BGTZ and BGTZL opcode:
BLTZALC: Compact branch-and-link if GPR rt is < to zero
BGTZALC: Compact branch-and-link if GPR rt is > to zero
BLTZL : Compact branch if GPR rt is < to zero
BGTZL : Compact branch if GPR rt is > to zero
BLTC : Compact branch if GPR rs is less than GPR rt
BLTUC : Similar to BLTC but unsigned
Markos Chandras [Wed, 26 Nov 2014 12:57:54 +0000 (12:57 +0000)]
MIPS: Emulate the new MIPS R6 B{L,G}Ε{Z,}{AL,}C instructions
MIPS R6 added the following four instructions which share the
BLEZ and BLEZL opcodes:
BLEZALC: Compact branch-and-link if GPR rt is <= to zero
BGEZALC: Compact branch-and-link if GPR rt is >= to zero
BLEZC : Compact branch if GPR rt is <= to zero
BGEZC : Compact branch if GPR rt is >= to zero
BGEC : Compact branch if GPR rs is less than or equal to GPR rt
BGEUC : Similar to BGEC but unsigned.
Markos Chandras [Tue, 25 Nov 2014 16:02:23 +0000 (16:02 +0000)]
MIPS: kernel: branch: Do not emulate the branch likelies on MIPS R6
MIPS R6 removed the BLTZL, BGEZL, BLTZAL, BGEZAL, BEQL, BNEL, BLEZL,
BGTZL branch likely instructions so we must not try to emulate them on
MIPS R6 if the R2-to-R6 emulator is not present.
Markos Chandras [Tue, 2 Dec 2014 15:30:19 +0000 (15:30 +0000)]
MIPS: mm: c-r4k: Set the correct ISA level
The local_r4k_flush_cache_sigtramp function uses the 'cache'
instruction inside an asm block. However, MIPS R6 changed the
opcode for the cache instruction and as a result of which we
need to set the correct ISA level.
Leonid Yegoshin [Mon, 24 Nov 2014 15:42:46 +0000 (15:42 +0000)]
MIPS: mm: tlbex: Use cpu_has_mips_r2_exec_hazard for the EHB instruction
MIPS uses the cpu_has_mips_r2_exec_hazard macro to determine whether the
EHB instruction is available or not. This is necessary for MIPS R6
which also supports the EHB instruction.
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Markos Chandras [Wed, 19 Nov 2014 09:39:56 +0000 (09:39 +0000)]
MIPS: mm: page: Add MIPS R6 support
The MIPS R6 pref instruction only has 9 bits for the immediate
field so skip the micro-assembler PREF instruction if the offset
does not fit in 9 bits. Moreover, bit 30 (Pref_PrepareForStore) is
no longer valid in MIPS R6, so we change the default for all MIPS R6
processors to bit 5 (Pref_StoreStreamed).
Leonid Yegoshin [Fri, 14 Nov 2014 11:55:50 +0000 (11:55 +0000)]
MIPS: lib: memcpy: Add MIPS R6 support
MIPS R6 does not support the unaligned load and store instructions
so we add a special MIPS R6 case to copy one byte at a time if we
need to read/write to unaligned memory addresses.
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Leonid Yegoshin [Tue, 28 Oct 2014 10:42:23 +0000 (10:42 +0000)]
MIPS: kernel: unaligned: Add support for the MIPS R6
The load/store unaligned instructions have been removed in MIPS R6
so we need to re-implement the related macros using the regular
load/store instructions. Moreover, the load/store from coprocessor 2
instructions have been reallocated in Release 6 so we will handle them
in the emulator instead.
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Leonid Yegoshin [Tue, 25 Nov 2014 10:08:45 +0000 (10:08 +0000)]
MIPS: kernel: r4k_fpu: Add support for MIPS R6
Add the MIPS R6 related preprocessor definitions for FPU signal
related functions. MIPS R6 only has FR=1 so avoid checking that
bit on the C0/Status register.
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Leonid Yegoshin [Mon, 24 Nov 2014 11:54:19 +0000 (11:54 +0000)]
MIPS: kernel: r4k_switch: Add support for MIPS R6
Add the MIPS R6 related preprocessor definitions for save/restore
FPU related functions. We also set the appropriate ISA level
so the final return instruction "jr ra" will produce the correct
opcode on R6.
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Leonid Yegoshin [Thu, 13 Nov 2014 13:51:51 +0000 (13:51 +0000)]
MIPS: kernel: cpu-probe.c: Add support for MIPS R6
Add MIPS R6 support when decoding the config0 c0 register.
Also add MIPS R6 support when examining the ebase c0 register
to get the core number and when getting the shadow set number
from the srsctl c0 register.
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Leonid Yegoshin [Mon, 24 Nov 2014 09:59:02 +0000 (09:59 +0000)]
MIPS: kernel: cpu-bugs64: Do not check R6 cores for existing 64-bit bugs
The current HW bugs checked in cpu-bugs64, do not apply to R6 cores
and they cause compilation problems due to removed <R6 instructions,
so do not check for them for the time being.
Reviewed-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Markos Chandras [Mon, 24 Nov 2014 14:11:39 +0000 (14:11 +0000)]
MIPS: asm: spinlock: Replace "sub" instruction with "addiu"
"sub $reg, imm" is not a real MIPS instruction. The assembler can
replace that with "addi $reg, -imm". However, addi has been removed
from R6, so we replace the "sub" instruction with the "addiu" one.
Markos Chandras [Mon, 26 Jan 2015 12:44:11 +0000 (12:44 +0000)]
MIPS: asm: Rename GCC_OFF12_ASM to GCC_OFF_SMALL_ASM
The GCC_OFF12_ASM macro is used for 12-bit immediate constrains
but we will also use it for 9-bit constrains on MIPS R6 so we
rename it to something more appropriate.
Cc: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
MIPS R6 changed the 'cache' instruction opcode and reduced the
offset field to 8 bits. This means we now have to adjust the
base register every 256 bytes and as a result of which we can
no longer use the previous cache functions.
Markos Chandras [Wed, 5 Nov 2014 14:17:52 +0000 (14:17 +0000)]
MIPS: asm: asmmacro: Replace "add" instructions with "addu"
The "add" instruction is actually a macro in binutils and depending on
the size of the immediate it can expand to an "addi" instruction.
However, the "addi" instruction traps on overflows which is not
something we want on address calculation.
Leonid Yegoshin [Mon, 27 Oct 2014 11:37:47 +0000 (11:37 +0000)]
MIPS: asm: stackframe: Do not preserve the HI/LO registers on MIPS R6
The HI/LO registers have been removed from MIPS R6. Instructions
such as MULT and DIV have been replaced with a new pair of
instructions for the HI/LO operations for example:
MULT -> MUL, MUH
DIV -> DIV, MOD
So we avoid preserving the pre-R6 HI/LO registers in MIPS R6
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Markos Chandras [Tue, 18 Nov 2014 15:02:32 +0000 (15:02 +0000)]
MIPS: asm: compiler: Add new macros to set ISA and arch asm annotations
There are certain places where the code uses .set mips32 or .set mips64
or .set arch=r4000. In preparation of MIPS R6 support, and in order to
use as less #ifdefs as possible, we define new macros to set similar
annotations for MIPS R6.
Leonid Yegoshin [Mon, 27 Oct 2014 10:12:23 +0000 (10:12 +0000)]
MIPS: Add generic QEMU PRid and cpu type identifiers
Latest versions of QEMU added support for mips32r6-generic and
mips64r6-generic cpu types so add related definitions in preparation
of MIPS R6 support. This is also used for QEMU R2 generic cpus.
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Markos Chandras [Mon, 26 Jan 2015 13:04:33 +0000 (13:04 +0000)]
MIPS: HTW: Prevent accidental HTW start due to nested htw_{start, stop}
activate_mm() and switch_mm() call get_new_mmu_context() which in turn
can enable the HTW before the entryhi is changed with the new ASID.
Since the latter will enable the HTW in local_flush_tlb_all(),
then there is a small timing window where the HTW is running with the
new ASID but with an old pgd since the TLBMISS_HANDLER_SETUP_PGD
hasn't assigned a new one yet. In order to prevent that, we introduce a
simple htw counter to avoid starting HTW accidentally due to nested
htw_{start,stop}() sequences. Moreover, since various IPI calls can
enforce TLB flushing operations on a different core, such an operation
may interrupt another htw_{stop,start} in progress leading inconsistent
updates of the htw_seq variable. In order to avoid that, we disable the
interrupts whenever we update that variable.
Markos Chandras [Mon, 26 Jan 2015 09:40:36 +0000 (09:40 +0000)]
MIPS: asm: pgtable: Prevent HTW race when updating PTEs
Whenever we modify a page table entry, we need to ensure that the HTW
will not fetch a stable entry. And for that to happen we need to ensure
that HTW is stopped before we modify the said entry otherwise the HTW
may already be in the process of reading that entry and fetching the
old information. As a result of which, we replace the htw_reset() calls
with htw_{stop,start} in more appropriate places. This also removes the
remaining users of htw_reset() and as a result we drop that macro
Markos Chandras [Mon, 26 Jan 2015 09:40:34 +0000 (09:40 +0000)]
MIPS: asm: pgtable: Add c0 hazards on HTW start/stop sequences
When we use htw_{start,stop}() outside of htw_reset(), we need
to ensure that c0 changes have been propagated properly before
we attempt to continue with subsequence memory operations.
Markos Chandras [Wed, 21 Jan 2015 10:54:46 +0000 (10:54 +0000)]
MIPS: mm: Add debug information for userland SIGSEGV signals.
Commit 41c594ab65fc ("[MIPS] MT: Improved multithreading support.")
removed useful debug information for userland segmentation faults.
This patch bring this back along with the ability to determine the
name of the object file where the EPC and RA registers point at.
Furthermore, we select the SYSCTL_EXCEPTION_TRACE symbol for MIPS
which is the de facto solution to turn userland exception logging
on and off via the /proc/sys/debug/exception-trace file.
Paul Burton [Thu, 8 Jan 2015 12:17:37 +0000 (12:17 +0000)]
MIPS,prctl: add PR_[GS]ET_FP_MODE prctl options for MIPS
Userland code may be built using an ABI which permits linking to objects
that have more restrictive floating point requirements. For example,
userland code may be built to target the O32 FPXX ABI. Such code may be
linked with other FPXX code, or code built for either one of the more
restrictive FP32 or FP64. When linking with more restrictive code, the
overall requirement of the process becomes that of the more restrictive
code. The kernel has no way to know in advance which mode the process
will need to be executed in, and indeed it may need to change during
execution. The dynamic loader is the only code which will know the
overall required mode, and so it needs to have a means to instruct the
kernel to switch the FP mode of the process.
This patch introduces 2 new options to the prctl syscall which provide
such a capability. The FP mode of the process is represented as a
simple bitmask combining a number of mode bits mirroring those present
in the hardware. Userland can either retrieve the current FP mode of
the process:
mode = prctl(PR_GET_FP_MODE);
or modify the current FP mode of the process:
err = prctl(PR_SET_FP_MODE, new_mode);
Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Matthew Fortune <matthew.fortune@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8899/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
James Hogan [Mon, 19 Jan 2015 12:00:55 +0000 (12:00 +0000)]
MIPS: cevt-r4k: Drop GIC special case
The cevt-r4k driver used to call into the GIC driver to find whether the
timer was pending, but only with External Interrupt Controller (EIC)
mode, where the Cause.IP bits can't be used as they encode the interrupt
priority level (Cause.RIPL) instead.
However commit e9de688dac65 ("irqchip: mips-gic: Support local
interrupts") changed the condition from cpu_has_veic to gic_present.
This fails on cores such as P5600 which have a GIC but the local
interrupts aren't routable by the GIC, causing c0_compare_int_usable()
to consider the interrupt unusable so r4k_clockevent_init() fails.
The previous behaviour, added in commit 98b67c37db33 ("MIPS: Add EIC
support for GIC."), wasn't really correct either as far as I can tell,
since P5600 apparently supports EIC mode too, and in any case the use of
Cause.TI with r2 should have been sufficient anyway since commit 010c108d7af7 ("MIPS: PowerTV: Fix support for timer interrupts with > 64
external IRQs").
Therefore drop the call into the gic driver altogether, and add a
comment in c0_compare_int_pending() to clarify that Cause.TI does get
checked since MIPS r2.
Signed-off-by: James Hogan <james.hogan@imgtec.com> Fixes: e9de688dac65 ("irqchip: mips-gic: Support local interrupts") Reviewed-by: Andrew Bresticker <abrestic@chromium.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Steven J. Hill <steven.hill@imgtec.com> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9077/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Ralf Baechle [Wed, 4 Feb 2015 12:04:03 +0000 (13:04 +0100)]
MIPS: elf2ecoff: Fix warning due to dead code.
HOSTCC arch/mips/boot/elf2ecoff
arch/mips/boot/elf2ecoff.c: In function ‘main’:
arch/mips/boot/elf2ecoff.c:271:8: warning: variable ‘shstrtab’ set but not used [-Wunused-but-set-variable]
char *shstrtab;
Rob Herring [Sat, 10 Jan 2015 02:34:36 +0000 (20:34 -0600)]
MIPS: Add struct pci_ops member names to initialization
Some instances of pci_ops initialization rely on the read/write members'
location in the struct. This is fragile and may break when adding new
members to the beginning of the struct.
[ralf@linux-mips.org: indent = with tabs for consistency.]
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