Ville Syrjälä [Fri, 13 Oct 2023 13:13:59 +0000 (16:13 +0300)]
drm: Fix color LUT rounding
The current implementation of drm_color_lut_extract()
generates weird results. Eg. if we go through all the
values for 16->8bpc conversion we see the following pattern:
So less values map to 0 and more values map 0xff, which
doesn't seem particularly great.
To get just the same number of input values to map to
the same output values we'd just need to drop the rounding
entrirely. But perhaps a better idea would be to follow the
OpenGL int<->float conversion rules, in which case we get
the following results:
Note that since the divisor is constant the compiler
is able to optimize away the integer division in most
cases. The only exception is the _ULL() case on 32bit
architectures since that gets emitted as inline asm
via do_div() and thus the compiler doesn't get to
optimize it.
Ville Syrjälä [Tue, 21 Nov 2023 05:43:24 +0000 (07:43 +0200)]
drm/i915: Implement audio fastset
There's no real reason why we'd need a full modeset for audio
changes. So let's allow audio to be toggled during fastset.
In case the ELD changes while has_audio isn't changing state
we force both audio disable and enable so the new ELD gets
propagated to the audio driver.
Ville Syrjälä [Tue, 21 Nov 2023 05:43:23 +0000 (07:43 +0200)]
drm/i915: Push audio_{enable,disable}() to the pre/post pane update stage
Relocate the audio enable/disable from the full modeset hooks into
the common pre/post plane update stage of the commit. Audio fastset
is within easy reach now.
Ville Syrjälä [Tue, 21 Nov 2023 05:43:21 +0000 (07:43 +0200)]
drm/i915: Convert audio enable/disable into encoder vfuncs
Add encoder vfuncs for audio enable/disable. This will allow
audio to be enabled/disabled during fastsets. An encoder hook
is necessary as on pre-hsw platforms different encoder types
implement audio in different ways.
Ville Syrjälä [Tue, 21 Nov 2023 05:43:18 +0000 (07:43 +0200)]
drm/i915: Wrap g4x+ DP/HDMI audio enable/disable
Put a wrapper around the intel_audio_codec_{enable,disable}()
calls in the g4x+ DP/HDMI code. We shall move the presence
detect enable/disable into the wrappers later.
Ville Syrjälä [Tue, 21 Nov 2023 05:43:17 +0000 (07:43 +0200)]
drm/i915: Push audio enable/disable further out
Push the audio enable/disable to be the last/first thing
respectively that is done in the encoder enable/disable hooks.
The goal is to move it further out of these encoder hooks entirely.
Ville Syrjälä [Tue, 21 Nov 2023 05:43:15 +0000 (07:43 +0200)]
drm/i915: Call intel_pre_plane_updates() also for pipes getting enabled
We used to call intel_pre_plane_updates() for any pipe going through
a modeset whether the pipe was previously enabled or not. This in
fact needed to apply all the necessary clock gating workarounds/etc.
Restore the correct behaviour.
Ville Syrjälä [Tue, 21 Nov 2023 05:43:14 +0000 (07:43 +0200)]
drm/i915: Check pipe active state in {planes,vrr}_{enabling,disabling}()
{planes,vrr}_{enabling,disabling}() are supposed to indicate
whether the specific hardware feature is supposed to be enabling
or disabling. That can only makes sense if the pipe is active
overall. So check for that before we go poking at the hardware.
I think we're semi-safe currently on due to:
- intel_pre_plane_update() doesn't get called when the pipe
was not-active prior to the commit, but this is actually a bug.
This saves vrr_disabling(), and vrr_enabling() is called from
deeper down where we have already checked hw.active.
- active_planes mirrors the crtc's hw.active
Mika Kahola [Thu, 16 Nov 2023 09:05:12 +0000 (11:05 +0200)]
drm/i915/display: Use int type for entry_setup_frames
entry_setup_frames variable is defined as u8. However, the
function call intel_psr_entry_setup_frames() can return
negative error code. There is a type mismatch here, so let's
switch to use int here as well.
Andy Shevchenko [Fri, 3 Nov 2023 20:18:30 +0000 (22:18 +0200)]
drm/i915/dsi: Combine checks in mipi_exec_gpio()
For a couple of cases the branches call the same bxt_gpio_set_value().
As Ville suggested they can be combined by dropping the DISPLAY_VER()
check from Gen 11 to Gen 9. Do it that way.
Andy Shevchenko [Fri, 3 Nov 2023 20:18:29 +0000 (22:18 +0200)]
drm/i915/dsi: Replace poking of CHV GPIOs behind the driver's back
It's a dirty hack in the driver that pokes GPIO registers behind
the driver's back. Moreoever it might be problematic as simultaneous
I/O may hang the system, see the commit 0bd50d719b00 ("pinctrl:
cherryview: prevent concurrent access to GPIO controllers") for
the details. Taking all this into consideration replace the hack
with proper GPIO APIs being used.
Andy Shevchenko [Fri, 3 Nov 2023 20:18:28 +0000 (22:18 +0200)]
drm/i915/dsi: Prepare soc_gpio_set_value() to distinguish GPIO communities
Currently soc_gpio_set_value() supports only a single indexing for GPIO
pin. For CHV case, for example, we will need to distinguish community
based index from the one that VBT is using. Introduce an additional
parameter to soc_gpio_set_value() and its callers.
Andy Shevchenko [Fri, 3 Nov 2023 20:18:27 +0000 (22:18 +0200)]
drm/i915/dsi: Replace poking of VLV GPIOs behind the driver's back
It's a dirty hack in the driver that pokes GPIO registers behind
the driver's back. Moreoever it might be problematic as simultaneous
I/O may hang the system, see the commit 40ecab551232 ("pinctrl:
baytrail: Really serialize all register accesses") for the details.
Taking all this into consideration replace the hack with proper
GPIO APIs being used.
Hans de Goede [Fri, 3 Nov 2023 20:18:25 +0000 (22:18 +0200)]
drm/i915/dsi: Fix wrong initial value for GPIOs in bxt_gpio_set_value()
Fix wrong initial value for GPIOs in bxt_gpio_set_value().
Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Tested-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231103201831.1037416-11-andriy.shevchenko@linux.intel.com
Hans de Goede [Fri, 3 Nov 2023 20:18:24 +0000 (22:18 +0200)]
drm/i915/dsi: Remove GPIO lookup table at the end of intel_dsi_vbt_gpio_init()
To properly deal with GPIOs used in MIPI panel sequences a temporary
GPIO lookup will be used. Since there can only be 1 GPIO lookup table
for the "0000:00:02.0" device this will not work if the GPIO lookup
table used by intel_dsi_vbt_gpio_init() is still registered.
After getting the "backlight" and "panel" GPIOs the lookup table
registered by intel_dsi_vbt_gpio_init() is no longer necessary,
remove it so that another temporary lookup-table for the "0000:00:02.0"
device can be added.
Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Tested-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231103201831.1037416-10-andriy.shevchenko@linux.intel.com
Andy Shevchenko [Fri, 3 Nov 2023 20:18:23 +0000 (22:18 +0200)]
drm/i915/dsi: Replace check with a (missing) MIPI sequence name
Names of the MIPI sequence steps are sequential and defined, no
need to check for the gaps. However in seq_name the MIPI_SEQ_END
is missing. Add it there, and drop unneeded NULL check in
sequence_name().
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Tested-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231103201831.1037416-9-andriy.shevchenko@linux.intel.com
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Tested-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231103201831.1037416-8-andriy.shevchenko@linux.intel.com
Andy Shevchenko [Fri, 3 Nov 2023 20:18:21 +0000 (22:18 +0200)]
drm/i915/dsi: Replace while(1) with one with clear exit condition
Move existing condition to while(), so it will be clear on what
circumstances the loop is successfully finishing.
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Tested-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231103201831.1037416-7-andriy.shevchenko@linux.intel.com
Jani Nikula [Fri, 3 Nov 2023 20:18:20 +0000 (22:18 +0200)]
drm/i915/dsi: bxt/icl GPIO set value do not need gpio source
Drop the unused parameter.
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Tested-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231103201831.1037416-6-andriy.shevchenko@linux.intel.com
Jani Nikula [Fri, 3 Nov 2023 20:18:19 +0000 (22:18 +0200)]
drm/i915/dsi: rename platform specific *_exec_gpio() to *_gpio_set_value()
The lowest level functions are about setting GPIO values, not about
executing any sequences anymore.
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Tested-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231103201831.1037416-5-andriy.shevchenko@linux.intel.com
Jani Nikula [Fri, 3 Nov 2023 20:18:18 +0000 (22:18 +0200)]
drm/i915/dsi: clarify GPIO exec sequence
With the various sequence versions and pointer increments interleaved,
it's a bit hard to decipher what's going on. Add separate paths for
different sequence versions.
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Tested-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231103201831.1037416-4-andriy.shevchenko@linux.intel.com
Jani Nikula [Fri, 3 Nov 2023 20:18:17 +0000 (22:18 +0200)]
drm/i915/dsi: switch mipi_exec_gpio() from dev_priv to i915
Follow the contemporary conventions.
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Tested-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231103201831.1037416-3-andriy.shevchenko@linux.intel.com
Jani Nikula [Fri, 3 Nov 2023 20:18:16 +0000 (22:18 +0200)]
drm/i915/dsi: assume BXT gpio works for non-native GPIO
Purely a guess. Drop the nop function.
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Tested-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231103201831.1037416-2-andriy.shevchenko@linux.intel.com
Imre Deak [Thu, 16 Nov 2023 13:18:41 +0000 (15:18 +0200)]
drm/i915/dp: Reuse intel_dp_{max,effective}_data_rate in intel_link_compute_m_n()
Reuse intel_dp_max_data_rate() and intel_dp_effective_data_rate() in
intel_link_compute_m_n(), instead of open-coding the equivalent. Note
the kbit/sec -> kByte/sec unit change in the M/N values, but this not
reducing the precision, as the link rate value is based anyway on a less
precise 10 kbit/sec value.
Imre Deak [Thu, 16 Nov 2023 13:18:40 +0000 (15:18 +0200)]
drm/i915/dp: Simplify intel_dp_max_data_rate()
Simplify intel_dp_max_data_rate() using
drm_dp_bw_channel_coding_efficiency() to calculate the max data rate for
both DP1.4 and UHBR link rates. This trades a redundant multiply/divide
for readability.
Imre Deak [Thu, 16 Nov 2023 13:18:39 +0000 (15:18 +0200)]
drm/i915/dp: Report a rounded-down value as the maximum data rate
Callers of intel_dp_max_data_rate() use the return value as an upper
bound for the BW a given mode requires. As such the rounding shouldn't
result in a bigger value than the actual upper bound. Use round-down
instead of -closest accordingly.
Imre Deak [Fri, 17 Nov 2023 15:09:29 +0000 (17:09 +0200)]
drm/i915/dp_mst: Fix PBN / MTP_TU size calculation for UHBR rates
Atm the allocated MST PBN value is calculated from the TU size (number
of allocated MTP slots) as
PBN = TU * pbn_div
pbn_div being the link BW for each MTP slot. For DP 1.4 link rates this
worked, as pbn_div there is guraranteed to be an integer number, however
on UHBR this isn't the case. To get a PBN, TU pair where TU is a
properly rounded-up value covering all the BW corresponding to PBN,
calculate first PBN and from PBN the TU value.
Calculate PBN directly from the effective pixel data rate, instead of
calculating it indirectly from the corresponding TU and pbn_div values
(which are in turn derived from the pixel data rate and BW overhead).
Add a helper function to calculate the effective data rate, also adding
a note that callers of intel_dp_link_required() may also need to check
the effective data rate (vs. the data rate w/o the BW overhead).
While at it add a note to check if WA#14013163432 is applicable.
v2:
- Fix PBN calculation, deriving it from the effective data rate directly
instead of using the indirect TU and pbn_div values for this.
- Add a note about WA#14013163432. (Arun)
v3:
- Fix rounding up quotient while calculating remote_tu. (Ville)
Imre Deak [Thu, 16 Nov 2023 13:18:37 +0000 (15:18 +0200)]
drm/i915/dp_mst: Calculate the BW overhead in intel_dp_mst_find_vcpi_slots_for_bpp()
The next patch will calculate the PBN value directly from the pixel data
rate and the BW allocation overhead, not requiring the data, link M/N
and TU values for this. To prepare for that move the calculation of BW
overheads from intel_dp_mst_compute_m_n() to
intel_dp_mst_find_vcpi_slots_for_bpp().
While at it store link_bpp in a .4 fixed point format.
Imre Deak [Thu, 16 Nov 2023 13:18:36 +0000 (15:18 +0200)]
drm/i915/dp: Fix UHBR link M/N values
The link M/N ratio is the data rate / link symbol clock rate, fix things
up accordingly. On DP 1.4 this ratio was correct as the link symbol clock
rate in that case matched the link data rate (in bytes/sec units, the
symbol size being 8 bits), however it wasn't correct for UHBR rates
where the symbol size is 32 bits.
Kudos to Arun noticing in Bspec the incorrect use of link data rate in
the ratio's N value.
Imre Deak [Mon, 20 Nov 2023 12:52:56 +0000 (14:52 +0200)]
drm/dp_mst: Add kunit tests for drm_dp_get_vc_payload_bw()
Add kunit test cases for drm_dp_get_vc_payload_bw() with all the DP1.4
and UHBR link configurations.
v2:
- List test cases in decreasing rate,lane count order matching the
corresponding DP Standard tables. (Ville)
- Add references to the DP Standard tables.
v3:
- Sort the testcases properly.
v4:
- Avoid 'stack frame size x exceeds limit y in
drm_test_dp_mst_calc_pbn_div()' compiler warn. (LKP)
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Lyude Paul <lyude@redhat.com> Cc: dri-devel@lists.freedesktop.org Cc: kernel test robot <lkp@intel.com> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> (v3) Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231120125256.2433782-1-imre.deak@intel.com
Imre Deak [Fri, 17 Nov 2023 15:09:27 +0000 (17:09 +0200)]
drm/dp_mst: Fix PBN divider calculation for UHBR rates
The current way of calculating the pbn_div value, the link BW per each
MTP slot, worked only for DP 1.4 link rates. Fix things up for UHBR
rates calculating with the correct channel coding efficiency based on
the link rate.
v2:
- Return the fractional pbn_div value from drm_dp_get_vc_payload_bw().
v3:
- Fix rounding up quotient while calculating req_slots. (Ville)
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Lyude Paul <lyude@redhat.com> Cc: dri-devel@lists.freedesktop.org Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231117150929.1767227-1-imre.deak@intel.com
Imre Deak [Thu, 16 Nov 2023 13:18:31 +0000 (15:18 +0200)]
drm/dp_mst: Store the MST PBN divider value in fixed point format
On UHBR links the PBN divider is a fractional number, accordingly store
it in fixed point format. For now drm_dp_get_vc_payload_bw() always
returns a whole number and all callers will use only the integer part of
it which should preserve the current behavior. The next patch will fix
drm_dp_get_vc_payload_bw() for UHBR rates returning a fractional number
for those (also accounting for the channel coding efficiency correctly).
Cc: Lyude Paul <lyude@redhat.com> Cc: Harry Wentland <harry.wentland@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Wayne Lin <wayne.lin@amd.com> Cc: amd-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
[Rebased changes in dm_helpers_construct_old_payload() on drm-intel-next] Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231116131841.1588781-2-imre.deak@intel.com
Ville Syrjälä [Fri, 17 Nov 2023 17:18:33 +0000 (19:18 +0200)]
drm/i915/fbc: Bump ivb FBC max surface size to 4kx4k
IVB Bspec says:
"Frame Buffer Compression is only supported with memory surfaces of 4096 lines
or less and pipe source sizes of 4096 pixels by 2048 lines or less. "
so seems like we should be able to bump the offset+size limit to
at least 4kx4k. Make it so.
Ville Syrjälä [Fri, 17 Nov 2023 17:18:31 +0000 (19:18 +0200)]
drm/i915/fbc: Split plane size vs. surface size checks apart
Do separate checks for the visible plane size vs. the surface
size (which I take to mean offset+size). For now both use the
same max w/h, but we can relax the surface size limits as
a followup.
Ville Syrjälä [Tue, 14 Nov 2023 14:23:33 +0000 (16:23 +0200)]
drm/i915: Also check for VGA converter in eDP probe
Unfortunately even the HPD based detection added in
commit cfe5bdfb27fa ("drm/i915: Check HPD live state during eDP probe")
fails to detect that the VBT's eDP/DDI-A is a ghost on
Asus B360M-A (CFL+CNP). On that board eDP/DDI-A has its HPD
asserted despite nothing being actually connected there :(
The straps/fuses also indicate that the eDP port is present.
So if one boots with a VGA monitor connected the eDP probe will
mistake the DP->VGA converter hooked to DDI-E for an eDP panel
on DDI-A.
As a last resort check what kind of DP device we've detected,
and if it looks like a DP->VGA converter then conclude that
the eDP port should be ignored.
Jani Nikula [Tue, 14 Nov 2023 10:45:34 +0000 (12:45 +0200)]
drm/i915: convert vlv_dpio_read()/write() from pipe to phy
vlv_dpio_read() and vlv_dpio_write() really operate on the phy, not
pipe. Passing the pipe instead of the phy as parameter is supposed to be
a convenience, but when the caller has the phy, it becomes an
inconvenience. See e.g. chv_dpio_cmn_power_well_enable() and
assert_chv_phy_powergate().
Figure out the phy in the callers, and pass phy to the dpio functions.
v2: retract one overzealous pipe->phy change (Ville)
Jani Nikula [Tue, 14 Nov 2023 10:45:33 +0000 (12:45 +0200)]
drm/i915: add vlv_pipe_to_phy() helper to replace DPIO_PHY()
Add a helper with better typing and handing for bogus input, and better
in line with vlv_dig_port_to_channel(), vlv_dig_port_to_phy(), and
vlv_pipe_to_channel().
Animesh Manna [Fri, 10 Nov 2023 03:25:18 +0000 (08:55 +0530)]
drm/i915/dsb: DSB code refactoring
Refactor DSB implementation to be compatible with Xe driver.
v1: RFC version.
v2: Make intel_dsb structure opaque from external usage. [Jani]
v3: Rebased on latest.
v4:
- Add boundary check in dsb_buffer_memset(). [Luca]
- Use size_t instead of u32. [Luca]
v5: WARN_ON() added for out of boudary case with some optimization. [Luca]
v6: Rebased on latest and fix a rebase-miss.
Animesh Manna [Wed, 8 Nov 2023 07:23:03 +0000 (12:53 +0530)]
drm/i915/panelreplay: Debugfs support for panel replay
Add debugfs support which will print source and sink status
per connector basis. Existing i915_psr_status and
i915_psr_sink_status will be used to get the source and
sink status of panel replay.
v1: Initial version. [rb-ed by Arun]
v2: Added check for DP 2.0 and connector type in connector_debugfs_add().
v3: Optimization and cosmetic changes. [Jouni]
Cc: Jouni Högander <jouni.hogander@intel.com> Cc: Arun R Murthy <arun.r.murthy@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Signed-off-by: Animesh Manna <animesh.manna@intel.com> Reviewed-by: Jouni Högander <jouni.hogander@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231108072303.3414118-7-animesh.manna@intel.com
drm/i915/xe2lpd: implement WA for underruns while enabling FBC
FIFO underruns are observed when FBC is enabled on plane 2 or
plane 3. Recommended WA is to update the FBC enabling sequence.
The plane binding register bits need to be updated separately
before programming the FBC enable bit.
Mika Kahola [Mon, 13 Nov 2023 09:37:37 +0000 (11:37 +0200)]
drm/i915/display: Use int for entry setup frames
At least one TGL had regression when using u8 types
for entry setup frames calculation. So, let's switch
to use ints instead.
intel_psr_entry_setup_frames() function expects
to return u8 but since in case of error the error
code -ETIME is returned. This doesn't fit into u8
and hence the return value is not as expected.
Swati Sharma [Fri, 10 Nov 2023 10:10:17 +0000 (15:40 +0530)]
drm/i915/dsc: Allow DSC only with fractional bpp when forced from debugfs
If force_dsc_fractional_bpp_en is set through debugfs allow DSC iff
compressed bpp is fractional. Continue if the computed compressed bpp
turns out to be a integer.
v2:
-Use helpers for fractional, integral bits of bits_per_pixel. (Suraj)
-Fix comment (Suraj)
Swati Sharma [Fri, 10 Nov 2023 10:10:16 +0000 (15:40 +0530)]
drm/i915/dsc: Add debugfs entry to validate DSC fractional bpp
DSC_Sink_BPP_Precision entry is added to i915_dsc_fec_support_show
to depict sink's precision.
Also, new debugfs entry is created to enforce fractional bpp.
If Force_DSC_Fractional_BPP_en is set then while iterating over
output bpp with fractional step size we will continue if output_bpp is
computed as integer. With this approach, we will be able to validate
DSC with fractional bpp.
Ankit Nautiyal [Fri, 10 Nov 2023 10:10:13 +0000 (15:40 +0530)]
drm/i915/audio: Consider fractional vdsc bpp while computing tu_data
MTL+ supports fractional compressed bits_per_pixel, with precision of
1/16. This compressed bpp is stored in U6.4 format.
Accommodate the precision during calculation of transfer unit data
for hblank_early calculation.
v2:
-Fix tu_data calculation while dealing with U6.4 format. (Stan)
Ankit Nautiyal [Fri, 10 Nov 2023 10:10:12 +0000 (15:40 +0530)]
drm/i915/display: Consider fractional vdsc bpp while computing m_n values
MTL+ supports fractional compressed bits_per_pixel, with precision of
1/16. This compressed bpp is stored in U6.4 format.
Accommodate this precision while computing m_n values.
v1:
Replace the computation of 'data_clock' with 'data_clock =
DIV_ROUND_UP(data_clock, 16).' (Sui Jingfeng).
v2:
Rebase and pass bits_per_pixel in U6.4 format.
Ankit Nautiyal [Fri, 10 Nov 2023 10:10:11 +0000 (15:40 +0530)]
drm/i915/display: Store compressed bpp in U6.4 format
DSC parameter bits_per_pixel is stored in U6.4 format.
The 4 bits represent the fractional part of the bpp.
Currently we use compressed_bpp member of dsc structure to store
only the integral part of the bits_per_pixel.
To store the full bits_per_pixel along with the fractional part,
compressed_bpp is changed to store bpp in U6.4 formats. Intergral
part is retrieved by simply right shifting the member compressed_bpp by 4.
v2:
-Use to_bpp_int, to_bpp_frac_dec, to_bpp_x16 helpers while dealing
with compressed bpp. (Suraj)
-Fix comment styling. (Suraj)
v3:
-Add separate file for 6.4 fixed point helper(Jani, Nikula)
-Add comment for magic values(Suraj)
v4:
-Fix checkpatch warnings caused by renaming(Suraj)
v5:
-Rebase.
-Use existing helpers for conversion of bpp_int to bpp_x16
and vice versa.
v1: Initial version.
v2:
- Use pr_* flags instead psr_* flags. [Jouni]
- Remove intel_dp_is_edp check as edp1.5 also has panel replay. [Jouni]
v3: Cover letter updated and selective fetch condition check is added
before updating its bit in PSR2_MAN_TRK_CTL register. [Jouni]
v4: Selective fetch related PSR2_MAN_TRK_CTL programmming dropped. [Jouni]
v5: Added PSR2_MAN_TRK_CTL programming as needed for Continuous Full
Frame (CFF) update.
v6: Rebased on latest.
Note: Initial plan is to enable panel replay in full-screen live active
frame update mode. In a incremental approach panel replay will be enabled
in selctive update mode if there is any gap in curent implementation.
Animesh Manna [Wed, 8 Nov 2023 07:23:01 +0000 (12:53 +0530)]
drm/i915/panelreplay: Enable panel replay dpcd initialization for DP
Due to similarity panel replay dpcd initialization got added in psr
function which is specific for edp panel. This patch enables panel
replay initialization for dp connector.
Animesh Manna [Wed, 8 Nov 2023 07:23:00 +0000 (12:53 +0530)]
drm/i915/panelreplay: Initializaton and compute config for panel replay
Modify existing PSR implementation to enable panel replay feature of DP 2.0
which is similar to PSR feature of EDP panel. There is different DPCD
address to check panel capability compare to PSR and vsc sdp header
is different.
v1: Initial version.
v2:
- Set source_panel_replay_support flag under HAS_PANEL_REPLAY()
condition check. [Jouni]
- Code restructured around intel_panel_replay_init
and renamed to intel_panel_replay_init_dpcd. [Jouni]
- Remove the initial code modification around has_psr2 flag. [Jouni]
- Add CAN_PANEL_REPLAY() in intel_encoder_can_psr which is used to
enable in intel_psr_post_plane_update. [Jouni]
v3:
- Initialize both psr and panel-replay. [Jouni]
- Initialize both panel replay and psr if detected. [Jouni]
- Refactoring psr function by introducing _psr_compute_config(). [Jouni]
- Add check for !is_edp while deriving source_panel_replay_support. [Jouni]
- Enable panel replay dpcd initialization in a separate patch. [Jouni]
v4:
- HAS_PANEL_REPLAY() check not needed during sink capability check. [Jouni]
- Set either panel replay source support or psr. [Jouni]
v5:
- HAS_PANEL_REPLAY() removed and use HAS_DP20() instead. [Jouni]
- Move psr related code to intel_psr.c. [Jani]
- Reset sink_panel_replay_support flag during disconnection. [Jani]
v6: return statement restored which is removed by misatke. [Jouni]
v7: cosmetic changes. [Arun]
Ville Syrjälä [Thu, 7 Sep 2023 12:25:41 +0000 (15:25 +0300)]
drm/i915: Do plane/etc. updates more atomically across pipes
Perform all the intel_pre_update_crtc() stuff for all pipes first,
and only then do the intel_update_crtc() vblank evasion stuff for
every pipe back to back. This should make it more likely that
the plane updates from multiple pipes happen on the same frame
(assuming the pipes are running in sync, eg. due to bigjoiner
or port sync).
Ville Syrjälä [Thu, 7 Sep 2023 12:25:40 +0000 (15:25 +0300)]
drm/i915: Split intel_update_crtc() into two parts
Split intel_update_crtc() into two parts such that the first
part performs all the non-vblank evasion preparatory stuff,
and the second part just does the vblank evasion stuff.
For now we just call these back to back so that there is
no funcitonal change.
Ville Syrjälä [Thu, 7 Sep 2023 12:25:39 +0000 (15:25 +0300)]
drm/i915: Drop redundant !modeset check
Since commit 7de5b6b54630 ("drm/i915: Don't flag both full
modeset and fastset at the same time")
intel_crtc_needs_fastset() and intel_crtc_needs_modeset() have
been mutually exclusive. Drop the redundant check.
drm/i915: Query compressed bpp properly using correct DPCD and DP Spec info
Currently we seem to be using wrong DPCD register for reading
compressed bpps, reading min/max input bpc instead of compressed bpp.
Fix that, so that we now apply min/max compressed bpp limitations we
get from DP Spec Table 2-157 DP v2.0 and/or correspondent DPCD
register DP_DSC_MAX_BITS_PER_PIXEL_LOW/HIGH.
This might also allow us to get rid of an ugly compressed bpp
recalculation, which we had to add to make some MST hubs usable.
v2: - Fix operator precedence
v3: - Added debug info about compressed bpps
v4: - Don't try to intersect Sink input bpp and compressed bpps.
v5: - Decrease step while looking for suitable compressed bpp to
accommodate.
v6: - Use helper for getting min and max compressed_bpp (Ankit)
v7: - Fix checkpatch warning (Ankit)
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231030155843.2251023-31-imre.deak@intel.com
Imre Deak [Tue, 24 Oct 2023 01:09:24 +0000 (04:09 +0300)]
drm/i915/dp_mst: Check BW limitations only after all streams are computed
After the previous patch the BW limits on the whole MST topology will be
checked after computing the state for all the streams in the topology.
Accordingly remove the check during the stream's encoder compute config
step, to prevent failing an atomic commit due to a BW limit, if this can
be resolved only by reducing the BW of other streams on the same MST
link.
Imre Deak [Tue, 24 Oct 2023 01:09:23 +0000 (04:09 +0300)]
drm/i915/dp_mst: Improve BW sharing between MST streams
At the moment modesetting a stream CRTC will fail if the stream's BW
along with the current BW of all the other streams on the same MST link
is above the total BW of the MST link. Make the BW sharing more dynamic
by trying to reduce the link bpp of one or more streams on the MST link
in this case.
When selecting a stream to reduce the BW for, take into account which
link segment in the MST topology ran out of BW and which streams go
through this link segment. For instance with A,B,C streams in the same
MST topology A and B may share the BW of a link segment downstream of a
branch device, stream C not downstream of the branch device, hence not
affecting this BW. If this link segment's BW runs out one or both of
stream A/B's BW will be reduced until their total BW is within limits.
While reducing the link bpp for a given stream DSC may need to be
enabled for it, which requires FEC on the whole MST link. Check for this
condition and recompute the state for all streams taking the FEC
overhead into account (on 8b/10b links).
v2:
- Rebase on s/min_bpp_pipes/min_bpp_reached_pipes/ change.
Imre Deak [Tue, 24 Oct 2023 01:09:22 +0000 (04:09 +0300)]
drm/i915/dp_mst: Force modeset CRTC if DSC toggling requires it
Enabling / disabling DSC decompression in the branch device downstream
of the source may reset the whole branch device. To avoid this while the
streams are still active, force a modeset on all CRTC/ports connected to
this branch device.
v2:
- Check the CRTC state for each connector in the topology, instead of
the CRTC being checked for a modeset requirement. (Ville)
- Add DocBook for the new function.
v3:
- Rebased on a change not to use
intel_modeset_pipes_in_mask_early().
Imre Deak [Tue, 24 Oct 2023 01:09:21 +0000 (04:09 +0300)]
drm/i915: Factor out function to clear pipe update flags
Factor out a helper to clear the pipe update flags, used by a follow-up
patch to modeset an MST topology.
v2:
- Move the intel_crtc_needs_modeset() check to the callers. (Ville)
v3 (Ville):
- Rename clear_pipe_update_flags_on_modeset_crtc() to
intel_crtc_flag_modeset().
- Also set crtc_state->uapi.mode_changed in the function.
- Leave out the unrelated change to use
intel_modeset_pipes_in_mask_early().
Imre Deak [Tue, 24 Oct 2023 01:09:20 +0000 (04:09 +0300)]
drm/i915/dp_mst: Enable MST DSC decompression for all streams
Enable DSC decompression for all streams. In particular atm if a sink is
connected to a last branch device that is downstream of the first branch
device connected to the source, decompression is not enabled for it.
Similarly it's not enabled if the sink supports this with the last
branch device passing through the compressed stream to it.
Enable DSC in the above cases as well. Since last branch devices may
handle the decompression for multiple ports, toggling DSC needs to be
refcounted, add this using the DSC AUX device as a reference.
v2:
- Fix refcounting, setting/clearing
connector->dp.dsc_decompression_enabled always as needed. (Stan)
- Make the refcounting more uniform for the SST vs. MST case.
- Add state checks for connector->dp.dsc_decompression_enabled and
connector crtc.
- Sanitize connector DSC decompression state during HW setup.
- s/use_count/ref_count/
v3:
- Remove stale TODO: comment to set the actual decompression_aux.
Imre Deak [Tue, 24 Oct 2023 10:22:18 +0000 (13:22 +0300)]
drm/i915/dp: Enable DSC via the connector decompression AUX
Enable DSC using the DSC AUX device stored for this purpose in the
connector. For clarity add separate functions to enable/disable the
decompression, since these sequences will diverge more in follow-up
patches that also enable/disable DSC passthrough and on MST do the
actual enabling/disabling only for the first/last user of the given
AUX device. As a preparation for the latter refcounting change, also
pass the atomic state to the functions.
While at it set/clear only the DP_DECOMPRESSION_EN flag in the
DP_DSC_ENABLE DPCD register, preserving the reserved register bits.
Besides preserving the reserved register bits, the behavior stays as
before, as DSC is still only enabled for the first MST stream (which a
follow-up patch changes, enabling it for all streams).
v2:
- Add a helper function setting/clearing the decompression flag,
preserving the reserved register bits.
v3:
- Add separate functions to enable/disable decompression and pass the
atomic state to these.
- Add DocBook for both functions.
Imre Deak [Tue, 24 Oct 2023 01:09:17 +0000 (04:09 +0300)]
drm/i915/dp_mst: Enable decompression in the sink from the MST encoder hooks
Enable/disable the DSC decompression in the sink/branch from the MST
encoder hooks. This prepares for an upcoming patch toggling DSC for each
stream as needed, but for now keeps the current behavior, as DSC is only
enabled for the first MST stream.
Imre Deak [Tue, 24 Oct 2023 01:09:16 +0000 (04:09 +0300)]
drm/i915/dp_mst: Handle the Synaptics HBlank expansion quirk
The Synaptics MST hubs expose some sink EDID modes with a reduced HBLANK
period, presumedly to save BW, which the hub expands before forwarding
the stream to the sink. In particular a 4k mode with a standard CVT
HBLANK period is exposed with either a CVT reduced blank RBv1,v2 (80,
160 pixel) or a non-CVT 56 pixel HBLANK period. The DP standard
describes the above HBLANK expansion functionality, but it requires
enabling this explicitly, whereas these hubs apply the expansion
transparently.
In some TBT docks with such a Synaptics hub (DELL WD22TB4) the above modes
will work okay until DSC decompression is enabled in the hub for the given
sink, but after this the same mode will not work reliably in decompressed
mode. In another TBT dock (Thinkpad 40B0) the above modes will not work
in uncompressed/18bpp mode (regardless of whether DSC decompression was
enabled before or not).
As a workaround force enable DSC for such modes. Apply the WA when the
HBLANK period is 300ns or below, matching the above tested modes with a
533.25MHz dotclock and maximum 160 HBLANK pixels.
OTOH DSC for these modes will only work above a certain compressed bpp
threshold which depends on the link rate, so apply this limit as well
in the workaround.
On platforms, pipe/port configurations where DSC is not supported, for
instance on ICL where DSC/MST is still work-in-progress, limit the
minimum link bpp to 24.
Apply the workaround only for Synaptics hubs which support the HBLANK
expansion.
v2:
- Apply the WA whenever the HBLANK period is 300ns or below.
v3:
- Clarify in the commit log the failure modes of the different docks.
- Handle platforms/pipe/port configurations without DSC support.
Imre Deak [Tue, 24 Oct 2023 01:09:14 +0000 (04:09 +0300)]
drm/i915/dp: Wait for FEC detected status in the sink
As required by the DP standard wait for the sink to detect the FEC
decode enabling symbol sent by the source.
There is a difference between SST and MST when the source enables
the FEC encoding: on SST this happens only after enabling the
transcoder, whereas on MST it happens already after enabling the
transcoder function (before enabling the transcoder). Wait for the
detected status at the earliest spot accordingly.
v2:
- Wait for the FEC detected status on SST after the transcoder is
enabled.
Imre Deak [Tue, 24 Oct 2023 01:09:11 +0000 (04:09 +0300)]
drm/i915/dp: Make sure the DSC PPS SDP is disabled whenever DSC is disabled
Atm the DSC PPS SDP will stay enabled after enabling and disabling DSC.
This leaves an output blank after switching off DSC on it. Make sure the
SDP is disabled for an uncompressed output.
v2:
- Disable the SDP already during output disabling. (Ville)
Imre Deak [Tue, 24 Oct 2023 01:09:10 +0000 (04:09 +0300)]
drm/i915/dp_mst: Program the DSC PPS SDP for each stream
Atm the DSC PPS SDP is programmed only if the first stream is compressed
and then it's programmed only for the first stream. This left all other
compressed streams blank. Program the SDP for all streams.
v2:
- Rebase on upstream include "intel_vdsc.h" change.
Imre Deak [Tue, 24 Oct 2023 01:09:09 +0000 (04:09 +0300)]
drm/i915/dp_mst: Add atomic state for all streams on pre-tgl platforms
If an MST stream is modeset, its state must be checked along all the
other streams on the same MST link, for instance to resolve a BW
overallocation of a non-sink MST port or to make sure that the FEC is
enabled/disabled the same way for all these streams.
To prepare for that this patch adds all the stream CRTCs to the atomic
state and marks them for modeset similarly to tgl+ platforms. (If the
state computation doesn't change the state the CRTC is switched back to
fastset mode.)
So far on tgl+ this was required because all streams in the topology
shared the master transcoder. For older platforms this didn't apply but
adding all the state is required now on all platforms based on the
above.
v2:
- Add code and commit log comment clarifying the requirements on old/new
platforms. (Stan)
- Rename the function based on the new semantic. (Ville)
Imre Deak [Tue, 24 Oct 2023 01:09:08 +0000 (04:09 +0300)]
drm/i915/dp_mst: Account for FEC and DSC overhead during BW allocation
Atm, the BW allocated for an MST stream doesn't take into account the
DSC control symbol (EOC) and data alignment overhead on the local (first
downstream) MST link (reflected by the data M/N/TU values) and - besides
the above overheads - the FEC symbol overhead on 8b/10b remote
(after a downstream branch device) MST links.
In addition the FEC overhead used on the local link is a fixed amount,
which only applies to certain modes, but not enough for all modes; add a
code comment clarifying this.
Fix the above by calculating the data M/N values with the total BW
overhead (not including the SSC overhead, since this isn't enabled by
the source device) and using this the PBN and TU values for the local
link and PBN for remote links (including SSC, since this is mandatory
for links after downstream branch devices).
For now keep the current fixed FEC overhead as a minimum, since this is
what bspec requires for audio functionality.
Calculate the effective link BW in a clearer way, applying the channel
coding efficiency based on the coding type. The calculation was correct
for 8b/10b, but not for 128b/132b links; this patch leaves the behavior
for this unchanged, leaving the fix for a follow-up.
v2:
- Fix TU size programmed to the HW, making it match the payload size
programmed to the payload table.
v3:
- Add code comment about the connection between the payload's size in
the payload table and the corresponding PBN value. (Ville)
- Add WARN_ON(remote_m_n.tu < dp_m_n.tu). (Ville)
- Add code comment about factors not accounted for by the BW
calculation in intel_dp_mst_mode_valid_ctx() (and compute config).
(Ville)
- Simplify calculation of PBN to remote_m_n.tu * mst_state->pbn_div.
Imre Deak [Tue, 24 Oct 2023 01:09:07 +0000 (04:09 +0300)]
drm/i915/dp: Pass actual BW overhead to m_n calculation
A follow-up MST patch will need to specify the total BW allocation
overhead, prepare for that here by passing the amount of overhead
to intel_link_compute_m_n(), keeping the existing behavior.
v2:
- Fix passing the correct crtc_state->fec_enable param in
intel_dp_mst_compute_link_config() /
intel_dp_dsc_mst_compute_link_config().
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