MIPS: Netlogic: PIC freq calculation for XLP 9XX/2XX
Update PIC frequency calculation for XLP9XX and 2XX processors using
the correct PLL registers. This should work for all possible board
configurations.
Jayachandran C [Fri, 9 May 2014 11:05:34 +0000 (16:35 +0530)]
MIPS: Netlogic: IRQ mapping for some more SoC blocks
Add IRQ to IRT (PIC interupt table index) mapping for SATA, GPIO, NAND
and SPI interfaces on the XLP SoC. Fix offsets for few blocks and add
device IDs for a few blocks.
Jayachandran C [Tue, 29 Apr 2014 14:37:47 +0000 (20:07 +0530)]
MIPS: Netlogic: Enable access to more than 64GB
The ELPA bit needs to be set in the PAGEGRAIN register to enable
access to >64GB physical address. Update reset.S to do this from
every hardware thread.
Jayachandran C [Fri, 9 May 2014 11:05:14 +0000 (16:35 +0530)]
MIPS: Netlogic: Reduce size of reset code
Update thread wakeup function to use scratch registers for saving SP and
RA. Move the register restore code needed for thread 0 to the calling
function. This reduces the size of code copied to the reset vector.
Tested on mips32 LE/BE and mips64 BE/n64 using
dhcp, ping and various tcpdump filters.
Benchmarking:
Assuming the remote MIPS target uses 192.168.154.181
as its IP address, and the local host uses 192.168.154.136,
the following results can be obtained using the following
tcpdump filter (catches no frames) and a simple
'time ping -f -c 1000000' command.
[root@(none) ~]# tcpdump -p -n -s 0 -i eth0 net 10.0.0.0/24 -d
(000) ldh [12]
(001) jeq #0x800 jt 2 jf 8
(002) ld [26]
(003) and #0xffffff00
(004) jeq #0xa000000 jt 16 jf 5
(005) ld [30]
(006) and #0xffffff00
(007) jeq #0xa000000 jt 16 jf 17
(008) jeq #0x806 jt 10 jf 9
(009) jeq #0x8035 jt 10 jf 17
(010) ld [28]
(011) and #0xffffff00
(012) jeq #0xa000000 jt 16 jf 13
(013) ld [38]
(014) and #0xffffff00
(015) jeq #0xa000000 jt 16 jf 17
(016) ret #65535
It will be used later one for the jalr and wsbh instructions.
[ralf@linux-mips.org: Dropped arch/mips/include/asm/uasm.h segment because
that was already added by 49e9529b9d43773307b8c73bd251b71784830c3d
[MIPS: uasm: add jalr instruction].
Deng-Cheng Zhu [Thu, 29 May 2014 19:26:45 +0000 (12:26 -0700)]
MIPS: math-emu: Add IEEE754 exception statistics to debugfs
Sometimes it's useful to let the user, while doing performance research,
know what in the IEEE754 exceptions has caused many times of FP emulation
when running a specific application. This patch adds 5 more files to
/sys/kernel/debug/mips/fpuemustats/, whose filenames begin with "ieee754".
These stats are in addition to the existing cp1ops, cp1xops, errors, loads
and stores, which may not be useful in understanding the reasons of ieee754
exceptions.
[ralf@linux-mips.org: Fixed reject due to other changes to the kernel
FP assist software.]
Patch was tested on devices with 64 MiB and 256 MiB of RAM.
It documents every part nicely and drops this hacky part of code:
max = off | ((128 << 20) - 1);
Alex Smith [Thu, 29 May 2014 10:10:01 +0000 (11:10 +0100)]
MIPS: octeon: Add interface mode detection for Octeon II
Add interface mode detection for Octeon II. This is necessary to detect
the interface modes correctly on the UBNT E200 board. Code is taken
from the UBNT GPL source release, with some alterations: SRIO, ILK and
RXAUI interface modes are removed and instead return disabled as these
modes are not currently supported.
Signed-off-by: Alex Smith <alex.smith@imgtec.com> Tested-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/7039/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Paul Burton [Tue, 15 Apr 2014 11:24:23 +0000 (12:24 +0100)]
MIPS: Malta: CPS SMP by default
The CONFIG_MIPS_CPS SMP implementation should be able to handle all
cases the CONFIG_MIPS_CMP implementation does, but without requiring
bootloader assistance. It is also required in order to make use of
features such as hotplug & cpuidle core power gating. Enable it by
default for Malta configs that previously enabled the now deprecated
CONFIG_MIPS_CMP, and disable the latter. The local version suffix "cmp"
is removed rather than replaced with "cps" since there are other ways to
tell that the CPS SMP implementation is in use (the "VPE topology" line
in the boot log being one).
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Paul Burton [Mon, 14 Apr 2014 15:25:29 +0000 (16:25 +0100)]
cpuidle: cpuidle-cps: add MIPS CPS cpuidle driver
This patch adds a cpuidle driver for systems based around the MIPS
Coherent Processing System (CPS) architecture. It supports four idle
states:
- The standard MIPS wait instruction.
- The non-coherent wait, clock gated & power gated states exposed by
the recently added pm-cps layer.
The pm-cps layer is used to enter all the deep idle states. Since cores
in the clock or power gated states cannot service interrupts, the
gic_send_ipi_single function is modified to send a power up command for
the appropriate core to the CPC in cases where the target CPU has marked
itself potentially incoherent.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Paul Burton [Wed, 8 Jan 2014 11:23:35 +0000 (11:23 +0000)]
cpuidle: declare cpuidle_dev in cpuidle.h
Declaring this allows drivers which need to initialise each struct
cpuidle_device at initialisation time to make use of the structures
already defined in cpuidle.c, rather than having to wastefully define
their own.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Paul Burton [Mon, 14 Apr 2014 15:16:41 +0000 (16:16 +0100)]
MIPS: cpuidle wait instruction state
Defines a macro intended to allow trivial use of the regular MIPS wait
instruction from cpuidle drivers, which may simply invoke the macro
within their array of states.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Paul Burton [Wed, 16 Apr 2014 10:10:57 +0000 (11:10 +0100)]
MIPS: smp-cps: duplicate core0 CCA on secondary cores
Rather than hardcoding CCA=0x5 for secondary cores, re-use the CCA from
the boot CPU. This allows overrides of the CCA using the cca= kernel
parameter to take effect on all CPUs for consistency.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Paul Burton [Mon, 14 Apr 2014 14:58:45 +0000 (15:58 +0100)]
MIPS: smp-cps: set a coherent default CCA
This patch sets a default CCA suited for use with multi-core SMP on all
current MIPS CPS based systems. It may still be overriden by the cca=
argument on the kernel command line.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Paul Burton [Mon, 14 Apr 2014 14:21:25 +0000 (15:21 +0100)]
MIPS: smp-cps: prevent multi-core SMP with unsuitable CCA
If the user or bootloader sets the CCA to a value which is not suited
for multi-core SMP (ie. anything non-coherent) then limit the system to
using only a single core and warn the user.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Paul Burton [Mon, 14 Apr 2014 13:13:57 +0000 (14:13 +0100)]
MIPS: smp-cps: hotplug support
This patch adds support for offlining CPUs via hotplug when using the
CONFIG_MIPS_CPS SMP implementation. When a CPU is offlined one of 2
things will happen:
- If the CPU is part of a core which implements the MT ASE and there
is at least one other VPE online within that core then the VPE will
be halted by settings its TCHalt bit.
- Otherwise if supported the core will be powered down via the CPC.
- Otherwise the CPU will hang by executing an infinite loop.
Bringing CPUs back online is then a process of either clearing the
appropriate VPEs TCHalt bit or powering up the appropriate core via the
CPC. Throughout the process the struct core_boot_config vpe_mask field
must be maintained such that mips_cps_boot_vpes will start & stop the
correct VPEs.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Paul Burton [Mon, 14 Apr 2014 10:00:56 +0000 (11:00 +0100)]
MIPS: pm-cps: add PM state entry code for CPS systems
This patch adds code to generate entry & exit code for various low power
states available on systems based around the MIPS Coherent Processing
System architecture (ie. those with a Coherence Manager, Global
Interrupt Controller & for >=CM2 a Cluster Power Controller). States
supported are:
- Non-coherent wait. This state first leaves the coherent domain and
then executes a regular MIPS wait instruction. Power savings are
found from the elimination of coherency interventions between the
core and any other coherent requestors in the system.
- Clock gated. This state leaves the coherent domain and then gates
the clock input to the core. This removes all dynamic power from the
core but leaves the core at the mercy of another to restart its
clock. Register state is preserved, but the core can not service
interrupts whilst its clock is gated.
- Power gated. This deepest state removes all power input to the core.
All register state is lost and the core will restart execution from
its BEV when another core powers it back up. Because register state
is lost this state requires cooperation with the CONFIG_MIPS_CPS SMP
implementation in order for the core to exit the state successfully.
The code will detect which states are available on the current system
during boot & generate the entry/exit code for those states. This will
be used by cpuidle & hotplug implementations.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Paul Burton [Fri, 7 Mar 2014 10:42:52 +0000 (10:42 +0000)]
MIPS: smp-cps: use CPC core-other locking
The core which the CPC core-other region relates to is based upon the
core-local core-other addressing register. As its name suggests this
register is shared between all VPEs within a core, and if there is a
possibility that multiple VPEs within a core will attempt to access
another core simultaneously then locking is required. This wasn't
previously a problem with the only user being cpu0 during boot, but will
be an issue once hotplug is implemented & may race with other users such
as cpuidle.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Paul Burton [Mon, 14 Apr 2014 11:21:49 +0000 (12:21 +0100)]
MIPS: smp-cps: flush cache after patching mips_cps_core_entry
The start of mips_cps_core_entry is patched in order to provide the code
with the address of the CM register region at a point where it will be
running non-coherent with the rest of the system. However the cache
wasn't being flushed after that patching which could in principle lead
to secondary cores using an invalid CM base address.
The patching is moved to cps_prepare_cpus since local_flush_icache_range
has not been initialised at the point cps_smp_setup is called.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Paul Burton [Fri, 14 Mar 2014 16:06:16 +0000 (16:06 +0000)]
MIPS: smp-cps: function to determine whether CPS SMP is in use
The core power down state for cpuidle will require that the CPS SMP
implementation is in use. This patch provides a mips_cps_smp_in_use
function which determines whether or not the CPS SMP implementation is
currently in use.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Paul Burton [Mon, 14 Apr 2014 11:04:27 +0000 (12:04 +0100)]
MIPS: smp-cps: rework core/VPE initialisation
When hotplug and/or a powered down idle state are supported cases will
arise where a non-zero VPE must be brought online without VPE 0, and it
where multiple VPEs must be onlined simultaneously. This patch prepares
for that by:
- Splitting struct boot_config into core & VPE boot config structures,
allocated one per core or VPE respectively. This allows for multiple
VPEs to be onlined simultaneously without clobbering each others
configuration.
- Indicating which VPEs should be online within a core at any given
time using a bitmap. This allows multiple VPEs to be brought online
simultaneously and also indicates to VPE 0 whether it should halt
after starting any non-zero VPEs that should be online within the
core. For example if all VPEs within a core are offlined via hotplug
and the user onlines the second VPE within that core:
1) The core will be powered up.
2) VPE 0 will run from the BEV (ie. mips_cps_core_entry) to
initialise the core.
3) VPE 0 will start VPE 1 because its bit is set in the cores
bitmap.
4) VPE 0 will halt itself because its bit is clear in the cores
bitmap.
- Moving the core & VPE initialisation to assembly code which does not
make any use of the stack. This is because if a non-zero VPE is to
be brought online in a powered down core then when VPE 0 of that
core runs it may not have a valid stack, and even if it did then
it's messy to run through parts of generic kernel code on VPE 0
before starting the correct VPE.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Paul Burton [Mon, 3 Mar 2014 12:08:40 +0000 (12:08 +0000)]
MIPS: add kmap_noncoherent to wire a cached non-coherent TLB entry
This is identical to kmap_coherent apart from the cache coherency
attribute used for the TLB entry, so kmap_coherent is abstracted to
kmap_prot which is then called for both kmap_coherent &
kmap_noncoherent. This will be used by a subsequent patch.
Suggested-by: Leonid Yegoshin <leonid.yegoshin@imgtec.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Eunbong Song [Fri, 11 Apr 2014 08:32:54 +0000 (08:32 +0000)]
MIPS: Octeon: Add PCIe2 support in arch_setup_msi_irq()
In arch_setup_msi_irq(), there is no case for PCIe2. So board which have PCIe2 functionality
fails to boot with "Kernel panic - not syncing: arch_setup_msi_irq: Invalid octeon_dma_bar_type"
message. This patch solve this problem.
Brian Norris [Thu, 1 May 2014 06:26:45 +0000 (23:26 -0700)]
MIPS: defconfigs: add MTD_SPI_NOR (new dependency for M25P80)
These defconfigs contain the CONFIG_M25P80 symbol, which is now
dependent on the MTD_SPI_NOR symbol. Add CONFIG_MTD_SPI_NOR to satisfy
the new dependency.
At the same time, drop the now-nonexistent CONFIG_MTD_CHAR symbol.
Aaro Koskinen [Tue, 6 May 2014 12:55:43 +0000 (15:55 +0300)]
MIPS: Add __SANE_USERSPACE_TYPES__ to asm/types.h for LL64
Allow 64-bit userspace programs to use ll64 types. The define name
comes from commit 2c9c6ce0199a4d252e20c531cfdc9d24e39235c0 (powerpc:
Add __SANE_USERSPACE_TYPES__ to asm/types.h for LL64).
The patch allows to compile perf on MIPS64 and eliminates the following
warnings:
tests/attr.c:74:4: error: format '%llu' expects argument of type 'long
long unsigned int', but argument 6 has type '__u64' [-Werror=format=]
MIPS: Lemote 2F: cs5536: mfgpt: depend on !highres
This timer does not support oneshot mode and as such the system remains
in periodic mode and won't support high res timers.
This patch adds a note about this in Kconfig and lets it depend on
!highres so users which want to use high timers don' stuck with this
timer.
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Cc: linux-mips@linux-mips.org Cc: Hua Yan <yanh@lemote.com> Cc: Huacai Chen <chenhc@lemote.com> Cc: Alex Smith <alex.smith@imgtec.com> Cc: Hongliang Tao <taohl@lemote.com> Cc: Wu Zhangjin <wuzhangjin@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/6935/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Leif Lindholm [Mon, 26 May 2014 13:42:49 +0000 (14:42 +0100)]
MIPS: DTS: Fix missing device_type="memory" property in memory nodes
A few platforms lack a 'device_type = "memory"' for their memory
nodes, relying on an old ppc quirk in order to discover its memory.
Add the missing data so that all parsing code can find memory nodes
correctly.
Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org> Acked-by: John Crispin <blogic@openwrt.org> Signed-off-by: Grant Likely <grant.likely@linaro.org> Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: Mark Rutland <mark.rutland@arm.com> Cc: <stable@vger.kernel.org> Cc: gaurav.minocha@alumni.ubc.ca
Patchwork: https://patchwork.linux-mips.org/patch/6989/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Himangi Saraogi [Tue, 20 May 2014 18:09:42 +0000 (23:39 +0530)]
MIPS: SEAD3: Introduce the use of the managed version of kzalloc
This patch moves data allocated using kzalloc to managed data allocated
using devm_kzalloc and cleans now unnecessary kfrees in probe and remove
functions. Also, the now unnecessary labels out_mem and out are done
away with. The error handling code is moved under if and return 0 is now
at the end of the function.
The following Coccinelle semantic patch was used for making the change:
Markos Chandras [Fri, 23 May 2014 12:31:32 +0000 (13:31 +0100)]
MIPS: malta: Remove 'maybe_unused' attribute from ememsize{, _str}
First introduced in e6ca4e5bf11466b5e9423a1e4ea51a8216c4b9b6
"MIPS: malta: malta-memory: Add support for the 'ememsize' variable"
but it is not needed since both variables are visible to the compiler.
Ralf Baechle [Fri, 23 May 2014 14:29:44 +0000 (16:29 +0200)]
MIPS: MT: Remove SMTC support
Nobody is maintaining SMTC anymore and there also seems to be no userbase.
Which is a pity - the SMTC technology primarily developed by Kevin D.
Kissell <kevink@paralogos.com> is an ingenious demonstration for the MT
ASE's power and elegance.
Based on Markos Chandras <Markos.Chandras@imgtec.com> patch
https://patchwork.linux-mips.org/patch/6719/ which while very similar did
no longer apply cleanly when I tried to merge it plus some additional
post-SMTC cleanup - SMTC was a feature as tricky to remove as it was to
merge once upon a time.
Ralf Baechle [Thu, 22 May 2014 15:06:03 +0000 (17:06 +0200)]
MIPS: Remove code protected by CONFIG_SYS_HAS_CPU_RM9000.
RM9000 support was removed a while ago but this bit crept back in through
commit 69f24d17 [MIPS: Optimize current_cpu_type() for better code.] which
had been developed before but merged after RM9000 support was removed.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Reported-by: Paul Bolle <pebolle@tiscali.nl>
Paul Bolle [Thu, 22 May 2014 09:24:19 +0000 (11:24 +0200)]
MIPS: BCM1480: Remove checks for CONFIG_SIBYTE_BCM1480_PROF
There are two checks for CONFIG_SIBYTE_BCM1480_PROF in the tree since
v2.6.15. The related Kconfig symbol has never been added to the tree. So
these checks have always evaluated to false. Besides, one of these
checks guards a call of sbprof_cpu_intr(). But that function is not
defined. Remove all this.
Paul Bolle [Thu, 22 May 2014 09:34:51 +0000 (11:34 +0200)]
MIPS: MSP71xx: Remove checks for two macros
Since v2.6.39 there are checks for CONFIG_MSP_HAS_DUAL_USB and checks
for CONFIG_MSP_HAS_TSMAC in the code. The related Kconfig symbols have
never been added. These checks have evaluated to false for three years
now. Remove them and the code they have been hiding.
Paul Bolle [Tue, 20 May 2014 11:34:36 +0000 (13:34 +0200)]
MIPS: Remove CONFIG_PMCTWILED completely
Commit 8b284dbc2200 ("MIPS: PNX Removing dead CONFIG_PMCTWILED") missed
one reference to CONFIG_PMCTWILED in the code. It also missed one
related reference to pmctwiled_setup(). Remove these references now.
Ralf Baechle [Thu, 22 May 2014 07:55:02 +0000 (09:55 +0200)]
MIPS: c-r4k: Call R4600_HIT_CACHEOP_WAR_IMPL only for 32 byte cache lines.
R4600_HIT_CACHEOP_WAR_IMPL is only needed on R4600 v1.6 and the R4600 has
data cache lines that are always 32 bytes so the call is pointless in
r4k_blast_dcache_page_dc64.
Move microMIPS32_to_MIPS32() to a separate file which only gets built
for mipsMIPS configurations; for other configurations the optimizer
eleminates calls to microMIPS32_to_MIPS32().
MIPS: math-emu: Switch to using the MIPS rounding modes.
Previously math-emu was using the IEEE-754 constants internally. These
were differing by having the constants for rounding to +/- infinity
switched, so a conversion was necessary. This would be entirely
avoidable if the MIPS constants were used throughout, so get rid of
the bloat.
mm_isBranchInstr() did reside in the math emu code even though it logically
is separate and also is used outside the math emu code. In addition GCC 4.9.0
leaves the following unnnecessarily bloated function body for a non-microMIPS
configuration:
which stores arguments that are never going to be used on the stack frame.
Move mm_isBranchInstr() from cp1emu.c to branch.c, then split mm_isBranchInstr()
into a __mm_isBranchInstr() core and a mm_isBranchInstr() wrapper inline function
which only invokes __mm_isBranchInstr() on microMIPS configurations.
This shaves off 112 bytes off the kernel and improves code flow a bit.
o Only define variables in the outermost block
o One empty line at most
o Format comments as per CodingStyle
o Update FSF address in licensing term comment
o Spell FPU and MIPS in all capitals.
o Remove ####-type of lines in comments.
o Try to make things a bit most consistent between sp_*.c / dp_*.c files.
MIPS: math-emu: Move various objects into an ar library.
ieee754d.o contains only debug code and dp_sqrt.o and sp_sqrt.o contain
code which for MIPS I/II/III systems we don't want to link. Again the
savings can be considerable for some systems:
projects / mirror_ubuntu-artful-kernel.git / log