Peter Maydell [Thu, 13 Jan 2022 11:18:24 +0000 (11:18 +0000)]
Merge remote-tracking branch 'remotes/legoater/tags/pull-ppc-20220112' into staging
ppc 7.0 queue:
* New SLOF for PPC970 and POWER5+ (Alexey)
* Fixes for POWER5+ pseries (Cedric)
* Updates of documentation (Leonardo and Thomas)
* First step of exception model cleanup (Fabiano)
* User created PHB3/PHB4 devices (Daniel and Cedric)
# gpg: Signature made Wed 12 Jan 2022 10:43:21 GMT
# gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1
* remotes/legoater/tags/pull-ppc-20220112: (34 commits)
ppc/pnv: use stack->pci_regs[] in pnv_pec_stk_pci_xscom_write()
ppc/pnv: turn pnv_phb4_update_regions() into static
ppc/pnv: Introduce user creatable pnv-phb4 devices
ppc/pnv: turn 'phb' into a pointer in struct PnvPhb4PecStack
ppc/pnv: move PHB4 XSCOM init to phb4_realize()
ppc/pnv: set phb4 properties in stk_realize()
pnv_phb4_pec: use pnv_phb4_pec_get_phb_id() in pnv_pec_dt_xscom()
pnv_phb4_pec.c: move pnv_pec_phb_offset() to pnv_phb4.c
pnv_phb4.c: change TYPE_PNV_PHB4_ROOT_BUS name
pnv_phb3.h: change TYPE_PNV_PHB3_ROOT_BUS name
ppc/pnv: Move num_phbs under Pnv8Chip
ppc/pnv: Complete user created PHB3 devices
ppc/pnv: Reparent user created PHB3 devices to the PnvChip
ppc/pnv: Introduce support for user created PHB3 devices
pnv_phb4.c: check if root port exists in rc_config functions
pnv_phb4.c: make pnv-phb4-root-port user creatable
ppc/pnv: Attach PHB3 root port device when defaults are enabled
pnv_phb4.c: add unique chassis and slot for pnv_phb4_root_port
pnv_phb3.c: add unique chassis and slot for pnv_phb3_root_port
target/ppc: Set the correct endianness for powernv memory dumps
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* remotes/lvivier-gitlab/tags/linux-user-for-7.0-pull-request: (30 commits)
linux-user: Implement capability prctls
linux-user: Implement PR_SET_PDEATHSIG
linux-user: Map signal number in PR_GET_PDEATHSIG
linux-user: Do not special-case NULL for PR_GET_PDEATHSIG
linux-user: Move target_struct.h generic definitions to generic/
linux-user/arm: Move target_oabi_flock64 out of target_structs.h
linux-user/xtensa: Use force_sig_fault
linux-user/sparc: Use force_sig_fault
linux-user/sh4: Use force_sig_fault
linux-user/s390x: Use force_sig_fault
linux-user/riscv: Use force_sig_fault
linux-user/ppc: Use force_sig_fault
linux-user/openrisc: Use force_sig_fault
target/mips: Extract trap code into env->error_code
target/mips: Extract break code into env->error_code
linux-user/mips: Use force_sig_fault
linux-user/mips: Improve do_break
linux-user/microblaze: Fix SIGFPE si_codes
linux-user/microblaze: Use force_sig_fault
linux-user/m68k: Use force_sig_fault
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
ppc/pnv: use stack->pci_regs[] in pnv_pec_stk_pci_xscom_write()
pnv_pec_stk_pci_xscom_write() is pnv_pec_stk_pci_xscom_ops write
callback. It writes values into regs in the stack->nest_regs[] array.
The pnv_pec_stk_pci_xscom_read read callback, on the other hand, returns
values of the stack->pci_regs[]. In fact, at this moment, the only use
of stack->pci_regs[] is in pnv_pec_stk_pci_xscom_read(). There's no code
that is written anything in stack->pci_regs[], which is suspicious.
Considering that stack->nest_regs[] is widely used by the nested
MemoryOps pnv_pec_stk_nest_xscom_ops, in both read and write callbacks,
the conclusion is that we're writing the wrong array in
pnv_pec_stk_pci_xscom_write(). This function should write stack->pci_regs[]
instead.
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Message-Id: <20220111200132.633896-2-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
ppc/pnv: Introduce user creatable pnv-phb4 devices
This patch introduces pnv-phb4 user creatable devices that are created
in a similar manner as pnv-phb3 devices, allowing the user to interact
with the PHBs directly instead of creating PCI Express Controllers that
will create a certain amount of PHBs per controller index.
We accomplish this by doing the following:
- add a pnv_phb4_get_stack() helper to retrieve which stack an user
created phb4 would occupy;
- when dealing with an user created pnv-phb4 (detected by checking if
phb->stack is NULL at the start of phb4_realize()), retrieve its stack
and initialize its properties as done in stk_realize();
- use 'defaults_enabled()' in stk_realize() to avoid creating and
initializing a 'stack->phb' qdev that might be overwritten by an user
created pnv-phb4 device. This process is wrapped into a new helper
called pnv_pec_stk_default_phb_realize().
Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220111131027.599784-5-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
ppc/pnv: turn 'phb' into a pointer in struct PnvPhb4PecStack
At this moment, stack->phb is the plain PnvPHB4 device itself instead of
a pointer to the device. This will present a problem when adding user
creatable devices because we can't deal with this struct and the
realize() callback from the user creatable device.
We can't get rid of this attribute, similar to what we did when enabling
pnv-phb3 user creatable devices, because pnv_phb4_update_regions() needs
to access stack->phb to do its job. This function is called twice in
pnv_pec_stk_update_map(), which is one of the nested xscom write
callbacks (via pnv_pec_stk_nest_xscom_write()). In fact,
pnv_pec_stk_update_map() code comment is explicit about how the order of
the unmap/map operations relates with the PHB subregions.
All of this indicates that this code is tied together in a way that we
either go on a crusade, featuring lots of refactories and redesign and
considerable pain, to decouple stack and phb mapping, or we allow stack
update_map operations to access the associated PHB as it is today even
after introducing pnv-phb4 user devices.
This patch chooses the latter. Instead of getting rid of stack->phb,
turn it into a PHB pointer. This will allow us to assign an user created
PHB to an existing stack later. In this process,
pnv_pec_stk_instance_init() is removed because stack->phb is being
initialized in stk_realize() instead.
Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220111131027.599784-4-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
The 'stack->phb_regs_mr' PHB4 passthrough XSCOM initialization relies on
'stack->phb' being not NULL. Moving 'stack->phb_regs_mr' region_init()
and add_subregion() to phb4_realize() time is a natural thing to do
since it's strictly PHB related.
The remaining XSCOM initialization is also related to 'stack->phb' but
in a different manner. For instance, 'stack->nest_regs_mr'
MemoryRegionOps, 'pnv_pec_stk_nest_xscom_ops', uses
pnv_pec_stk_nest_xscom_write() as a write callback. When trying to write
the PEC_NEST_STK_BAR_EN reg, pnv_pec_stk_update_map() is called. Inside
this function, pnv_phb4_update_regions() is called twice. This function
uses 'stack->phb' to manipulate memory regions of the phb.
This is not a problem now but, when enabling user creatable phb4s, a
stack that doesn't have an associated phb (i.e. stack->phb = NULL) it
will cause a SIGINT during boot in pnv_phb4_update_regions().
All this can be avoided if all XSCOM realize is moved to phb4_realize(),
when we have certainty about the existence of 'stack->phb'. A lot of
code was moved from pnv_phb4_pec.c to pnv_phb4.c due to static constant
and variables being used but the cleaner logic is worth the trouble.
Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220111131027.599784-3-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Moving all phb4 properties setup to stk_realize() keeps this logic in
a single place instead of having it scattered between stk_realize() and
pec_realize().
'phb->index' can be retrieved using stack->stack_no and
pnv_phb4_pec_get_phb_id(), deprecating the use of 'phb-id' alias that
was being used for this purpose in pec_realize().
Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220111131027.599784-2-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
pnv_phb4_pec: use pnv_phb4_pec_get_phb_id() in pnv_pec_dt_xscom()
Relying on stack->phb to write the xscom DT of the PEC is something that
we won't be able to do with user creatable pnv-phb4 devices.
Hopefully, this can be done by using pnv_phb4_pec_get_phb_id(), which is
already used by pnv_pec_realize() to set the phb-id of the stack. Use
the same idea in pnv_pec_dt_xscom() to write ibm,phb-index without the
need to accessing stack->phb, since stack->phb is not granted to be !=
NULL when user creatable phbs are introduced.
Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220110143346.455901-4-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
pnv_phb4_pec.c: move pnv_pec_phb_offset() to pnv_phb4.c
The logic inside pnv_pec_phb_offset() will be useful in the next patch
to determine the stack that should contain a PHB4 device.
Move the function to pnv_phb4.c and make it public since there's no
pnv_phb4_pec.h header. While we're at it, add 'stack_index' as a
parameter and make the function return 'phb-id' directly. And rename it
to pnv_phb4_pec_get_phb_id() to be even clearer about the function
intent.
Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220110143346.455901-3-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Similar to what was happening with pnv-phb3 buses,
TYPE_PNV_PHB4_ROOT_BUS set to "pnv-phb4-root-bus" is a bit too long for
a default root bus name. The usual default name for theses buses in QEMU
are 'pcie', but we want to make a distinction between pnv-phb4 buses and
other PCIE buses, at least as far as default name goes, because not all
PCIE devices are attachable to a pnv-phb4 root-bus type.
Changing the default to 'pnv-phb4-root' allow us to have a shorter name
while making this bus distinct, and the user can always set its own bus
naming via the "id" attribute anyway.
This is the 'info qtree' output after this change, using a powernv9
domain with 2 sockets and default settings enabled:
The TYPE_PNV_PHB3_ROOT_BUS name is used as the default bus name when
the dev has no 'id'. However, pnv-phb3-root-bus is a bit too long to be
used as a bus name.
Most common QEMU buses and PCI controllers are named based on their bus
type (e.g. pSeries spapr-pci-host-bridge is called 'pci'). The most
common name for a PCIE bus controller in QEMU is 'pcie'. Naming it
'pcie' would break the documented use of the pnv-phb3 device, since
'pcie.0' would now refer to the root bus instead of the first root port.
There's nothing particularly wrong with the 'root-bus' name used before,
aside from the fact that 'root-bus' is being used for pnv-phb3 and
pnv-phb4 created buses, which is not quite correct since these buses
aren't implemented the same way in QEMU - you can't plug a
pnv-phb4-root-port into a pnv-phb3 root bus, for example.
This patch renames it as 'pnv-phb3-root', which is a compromise between
the existing and the previously used name. Creating 3 phbs without ID
will result in an "info qtree" output similar to this:
bus: main-system-bus
type System
dev: pnv-phb3, id ""
index = 2 (0x2)
chip-id = 0 (0x0)
x-config-reg-migration-enabled = true
bypass-iommu = false
bus: pnv-phb3-root.2
type pnv-phb3-root
(...)
dev: pnv-phb3, id ""
index = 1 (0x1)
chip-id = 0 (0x0)
x-config-reg-migration-enabled = true
bypass-iommu = false
bus: pnv-phb3-root.1
type pnv-phb3-root
(...)
dev: pnv-phb3, id ""
index = 0 (0x0)
chip-id = 0 (0x0)
x-config-reg-migration-enabled = true
bypass-iommu = false
bus: pnv-phb3-root.0
type pnv-phb3-root
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220105212338.49899-11-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Cédric Le Goater [Wed, 12 Jan 2022 10:28:27 +0000 (11:28 +0100)]
ppc/pnv: Reparent user created PHB3 devices to the PnvChip
The powernv machine uses the object hierarchy to populate the device
tree and each device should be parented to the chip it belongs to.
This is not the case for user created devices which are parented to
the container "/unattached".
Make sure a PHB3 device is parented to its chip by reparenting the
object if necessary.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220105212338.49899-8-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
pnv_phb4.c: check if root port exists in rc_config functions
pnv_phb4_rc_config_read() and pnv_phb4_rc_config_write() are asserting
the existence of the root port. The root port is now optional, and there
will be cases where a pnv-phb4 device won't have a root port attached.
Instead of asserting, check if the root port exists before read/writing
into it.
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220105212338.49899-6-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
pnv_phb4.c: make pnv-phb4-root-port user creatable
We want to create only the absolutely minimal amount of devices when
running with -nodefaults. The root port is something that the machine
can boot up without. But, to do that, we need to provide a way for the
user to add them by hand.
This patch makes pnv-phb4-root-port user creatable and then uses the
pnv_phb_attach_root_port() helper to add a pnv_phb4_root_port only when
running with default settings.
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220105212338.49899-5-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
This error comes from the realize() function of its parent type,
rp_realize() from TYPE_PCIE_ROOT_PORT. pcie_chassis_add_slot() fails
with -EBUSY if there's an existing PCIESlot that has the same
chassis/slot value, regardless of being in a different bus.
One way to prevent this error is simply set chassis and slot values in
the command line. However, since phb3 root buses only supports a single
root port, we can just get an unique chassis/slot value by checking
which root bus the pnv_phb3_root_port is going to be attached, get the
equivalent phb3 device and use its chip-id and index values, which are
guaranteed to be unique.
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220105212338.49899-2-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Fabiano Rosas [Wed, 12 Jan 2022 10:28:27 +0000 (11:28 +0100)]
target/ppc: Set the correct endianness for powernv memory dumps
We use the endianness of interrupts to determine which endianness to
use for the guest kernel memory dump. For machines that support HILE
(powernv8 and up) we have been always generating big endian dump
files.
This patch uses the HILE support recently added to
ppc_interrupts_little_endian to fix the endianness of the dumps for
powernv machines.
Fabiano Rosas [Wed, 12 Jan 2022 10:28:27 +0000 (11:28 +0100)]
target/ppc: Add MSR_ILE support to ppc_interrupts_little_endian
Some CPUs set ILE via an MSR bit. We can make
ppc_interrupts_little_endian handle that case as well. Now we have a
centralized way of determining the endianness of interrupts.
This change has no functional impact.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20220107222601.4101511-6-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Fabiano Rosas [Wed, 12 Jan 2022 10:28:27 +0000 (11:28 +0100)]
target/ppc: Add HV support to ppc_interrupts_little_endian
The ppc_interrupts_little_endian function could be used for interrupts
delivered in Hypervisor mode, so add support for powernv8 and powernv9
to it.
Also drop the comment because it is inaccurate, all CPUs that can run
little endian can have interrupts in little endian. The point is
whether they can take interrupts in an endianness different from
MSR_LE.
This change has no functional impact.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20220107222601.4101511-5-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Thomas Huth [Wed, 12 Jan 2022 10:28:26 +0000 (11:28 +0100)]
MAINTAINERS: Improve the PowerPC machines section
Add some documentation files to the corresponding machine sections
and mention the machine names in the section titles where it is
not so obvious (e.g. that "taihu" is a 405 machine).
Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20220105104800.407570-1-thuth@redhat.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Cédric Le Goater [Wed, 12 Jan 2022 10:28:26 +0000 (11:28 +0100)]
target/ppc: Add extra float instructions to POWER5P processors
ISA v2.03 introduced Floating Round to Integer instructions : frin,
friz, frip, and frim. Add them to POWER5+.
The PPC_FLOAT_EXT flag also includes the fre (Floating Reciprocal
Estimate) instruction which was introduced in ISA v2.0x. The
architecture document says its optional and that might be the reason
why it has been kept under the PPC_FLOAT_EXT flag. This means 970 CPUs
can not use it under QEMU, which doesn't seem to be a problem.
Cédric Le Goater [Wed, 12 Jan 2022 10:28:26 +0000 (11:28 +0100)]
spapr: Fix support of POWER5+ processors
POWER5+ (ISA v2.03) processors are supported by the pseries machine
but they do not have Altivec instructions. Do not advertise support
for it in the DT.
To be noted that this test is in contradiction with the assert in
cap_vsx_apply().
Signed-off-by: Cédric Le Goater <clg@kaod.org> Tested-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220105095142.3990430-3-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Peter Maydell [Tue, 11 Jan 2022 08:29:00 +0000 (08:29 +0000)]
linux-user: Fix clang warning for nios2-linux-user code
The clang in Ubuntu 18.04 (10.0.0-4ubuntu1) produces a warning
on the code added in commit f5ef0e518d03 where we use a
shifted expression in a boolean context:
../../linux-user/elfload.c:2423:16: error: converting the result of '<<' to a boolean always evaluates to true [-Werror,-Wtautological-constant-compare]
} else if (LO_COMMPAGE) {
^
../../linux-user/elfload.c:1102:22: note: expanded from macro 'LO_COMMPAGE'
#define LO_COMMPAGE TARGET_PAGE_SIZE
^
/mnt/nvmedisk/linaro/qemu-from-laptop/qemu/include/exec/cpu-all.h:231:31: note: expanded from macro 'TARGET_PAGE_SIZE'
#define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS)
^
1 error generated.
The warning is bogus because whether LO_COMMPAGE is zero or not
depends on compile-time ifdefs; shut the compiler up by adding
an explicit comparison to zero.
Fixes: f5ef0e518d0331 ("linux-user/nios2: Map a real kuser page") Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Message-id: 20220111082900.3341274-1-peter.maydell@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
linux-user/arm: Move target_oabi_flock64 out of target_structs.h
Place it next to copy_from/to_user_oabi_flock64, the only users,
inside the existing target-specific ifdef. This leaves only
generic ipc structs in target_structs.h.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Message-Id: <20220107042600.149852-2-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Use the new function instead of setting up a target_siginfo_t
and calling queue_signal. Fix missing PC from EXCP_DEBUG by
merging the case with EXCP_BREAKPOINT.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220107213243.212806-21-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Use the new function instead of setting up a target_siginfo_t
and calling queue_signal. Fill in the missing PC for SIGTRAP.
The fault address for POWERPC_EXCP_ISI is nip exactly, not nip - 4.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220107213243.212806-20-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
target/mips: Extract break code into env->error_code
Simplify cpu_loop by doing all of the decode in translate.
This fixes a bug in that cpu_loop was not handling the
different layout of the R6 version of break16. This fixes
a bug in that cpu_loop extracted the wrong bits for the
mips16e break16 instruction.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220107213243.212806-17-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Use the new function instead of setting up a target_siginfo_t
and calling queue_signal. Fill in the missing PC for SIGTRAP
and SIGFPE; use force_sig (SI_KERNEL) for EXCP_DSPDIS.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220107213243.212806-16-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Rename to do_tr_or_bp, as per the kernel function.
Add a 'trap' argument, akin to the kernel's si_code, but clearer.
The return value is always 0, so change the return value to void.
Use force_sig and force_sig_fault.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220107213243.212806-15-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Use the new function instead of setting up a target_siginfo_t
and calling queue_signal. Fill in the missing PC for SIGTRAP
and missing si_code for SIGBUS.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220107213243.212806-6-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
* remotes/jsnow-gitlab/tags/python-pull-request:
simplebench: Fix Python syntax error (reported by LGTM)
python: update type hints for mypy 0.930
Python/aqmp: fix type definitions for mypy 0.920
python/aqmp: use absolute import statement
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Tue, 11 Jan 2022 11:39:31 +0000 (11:39 +0000)]
Merge remote-tracking branch 'remotes/philmd/tags/sdmmc-20220108' into staging
SD/MMC patches queue
- Add SDHC support for SD card SPI-mode (Frank Chang)
# gpg: Signature made Sat 08 Jan 2022 21:56:02 GMT
# gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE
* remotes/philmd/tags/sdmmc-20220108:
hw/sd: Add SDHC support for SD card SPI-mode
hw/sd/sdcard: Rename Write Protect Group variables
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Tue, 11 Jan 2022 10:12:29 +0000 (10:12 +0000)]
Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging
virtio: revert config interrupt changes
Lots of fallout from config interrupt changes. Author wants to rework
the patches. Let's revert quickly so others don't suffer meanwhile.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
# gpg: Signature made Mon 10 Jan 2022 21:03:44 GMT
# gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469
# gpg: issuer "mst@redhat.com"
# gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full]
# gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full]
# Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67
# Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469
* remotes/mst/tags/for_upstream:
Revert "virtio: introduce macro IRTIO_CONFIG_IRQ_IDX"
Revert "virtio-pci: decouple notifier from interrupt process"
Revert "virtio-pci: decouple the single vector from the interrupt process"
Revert "vhost: introduce new VhostOps vhost_set_config_call"
Revert "vhost-vdpa: add support for config interrupt"
Revert "virtio: add support for configure interrupt"
Revert "vhost: add support for configure interrupt"
Revert "virtio-net: add support for configure interrupt"
Revert "virtio-mmio: add support for configure interrupt"
Revert "virtio-pci: add support for configure interrupt"
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Stefan Weil [Fri, 7 Jan 2022 15:30:19 +0000 (16:30 +0100)]
simplebench: Fix Python syntax error (reported by LGTM)
Fixes: b2fcb0c5754c2554b8406376e99a75e9e0a6b7bd Signed-off-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: John Snow <jsnow@redhat.com>
Message-id: 20220107153019.504124-1-sw@weilnetz.de Signed-off-by: John Snow <jsnow@redhat.com>
John Snow [Mon, 10 Jan 2022 19:13:49 +0000 (14:13 -0500)]
python: update type hints for mypy 0.930
Mypy 0.930, released Dec 22, changes the way argparse objects are
considered. Crafting a definition that works under Python 3.6 and an
older mypy alongside newer versions simultaneously is ... difficult,
so... eh. Stub it out with an 'Any' definition to get the CI moving
again.
Oh well.
Signed-off-by: John Snow <jsnow@redhat.com> Reviewed-by: Beraldo Leal <bleal@redhat.com>
Message-id: 20220110191349.1841027-4-jsnow@redhat.com Signed-off-by: John Snow <jsnow@redhat.com>
John Snow [Mon, 10 Jan 2022 19:13:47 +0000 (14:13 -0500)]
python/aqmp: use absolute import statement
pylint's dependency astroid appears to have bugs in 2.9.1 and 2.9.2 (Dec
31 and Jan 3) that appear to erroneously expect the qemu namespace to
have an __init__.py file. astroid 2.9.3 (Jan 9) avoids that problem, but
appears to not understand a relative import within a namespace package.
Update the relative import - it was worth changing anyway, because these
packages will eventually be packaged and distributed separately.
Signed-off-by: John Snow <jsnow@redhat.com> Reviewed-by: Beraldo Leal <bleal@redhat.com>
Message-id: 20220110191349.1841027-2-jsnow@redhat.com Signed-off-by: John Snow <jsnow@redhat.com>
Fixes: 316011b8a7 ("virtio-pci: decouple the single vector from the interrupt process") Cc: "Cindy Lu" <lulu@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Fixes: 497679d510 ("virtio-net: add support for configure interrupt") Cc: "Cindy Lu" <lulu@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Fixes: d48185f1a4 ("virtio-mmio: add support for configure interrupt") Cc: "Cindy Lu" <lulu@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Fixes: d5d24d859c ("virtio-pci: add support for configure interrupt") Cc: "Cindy Lu" <lulu@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
target/m68k: don't word align SP in stack frame if M68K_FEATURE_UNALIGNED_DATA feature enabled
Commit a9431a03f7 ("target/m68k: add M68K_FEATURE_UNALIGNED_DATA feature") added
a new feature for processors from the 68020 onwards which do not require data
accesses to be word aligned.
Unfortunately the original commit missed an additional case whereby the SP is
still word aligned when setting up an additional format 1 stack frame so add the
necessary M68K_FEATURE_UNALIGNED_DATA feature guard.
The macfb VRAM memory region was configured with coalescing rather than dirty
memory logging enabled, causing some areas of the screen not to redraw after
a full screen update.
Laurent Vivier [Fri, 7 Jan 2022 10:50:49 +0000 (11:50 +0100)]
q800: fix segfault with invalid MacROM
"qemu-system-m68k -M q800 -bios /dev/null" crashes with a segfault
in q800_init().
This happens because the code doesn't check that rom_ptr() returned
a non-NULL pointer .
To avoid NULL pointer, don't allow 0 sized file and use bios_size with
rom_ptr().
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/756 Reported-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20220107105049.961489-1-laurent@vivier.eu> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Merge tag 'bsd-user-arm-pull-request' of gitlab.com:bsdimp/qemu into staging
bsd-user: arm (32-bit) support
This series of patches brings in 32-bit arm support for bsd-user. It implements
all the bits needed to do image activation, signal handling, stack management
and threading. This allows us to get to the "Hello World" level. The arm and x86
code are now the same as in the bsd-user fork. For full context, the fork is at
https://github.com/qemu-bsd-user/qemu-bsd-user/tree/blitz (though the the recent
sig{bus,segv} needed updates are incomplete).
v5 changes:
o Moved to using the CPUArchState typedef and move
set_sigtramp_args, get_mcontext, set_mcontext, and
get_ucontext_sigreturn prototypes to
bsd-user/freebsd/target_os_ucontext.h
o Fix issues with arm's set_mcontext related to masking
and remove an unnecessary check.
We're down to only one hunk needing review:
bsd-user/arm/target_arch_signal.c: arm set_mcontext
Warnings that should be ignored:
o make checkpatch has a couple of complaints about the comments for the
signal trampoline, since it's a false positive IMHO.
WARNING: Block comments use a leading /* on a separate line
+ /* 8 */ sys_sigreturn,
WARNING: Block comments use a leading /* on a separate line
+ /* 9 */ sys_exit
# gpg: Signature made Fri 07 Jan 2022 11:36:37 PM PST
# gpg: using RSA key 2035F894B00AA3CF7CCDE1B76C1CD1287DB01100
# gpg: Good signature from "Warner Losh <wlosh@netflix.com>" [unknown]
# gpg: aka "Warner Losh <imp@bsdimp.com>" [unknown]
# gpg: aka "Warner Losh <imp@freebsd.org>" [unknown]
# gpg: aka "Warner Losh <imp@village.org>" [unknown]
# gpg: aka "Warner Losh <wlosh@bsdimp.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 2035 F894 B00A A3CF 7CCD E1B7 6C1C D128 7DB0 1100
* tag 'bsd-user-arm-pull-request' of gitlab.com:bsdimp/qemu: (37 commits)
bsd-user: add arm target build
bsd-user/freebsd/target_os_ucontext.h: Require TARGET_*CONTEXT_SIZE
bsd-user/arm/signal.c: arm get_ucontext_sigreturn
bsd-user/arm/signal.c: arm set_mcontext
bsd-user/arm/signal.c: arm get_mcontext
bsd-user/arm/signal.c: arm set_sigtramp_args
bsd-user/arm/target_arch_signal.h: Define size of *context_t
bsd-user/arm/target_arch_signal.h: arm machine context and trapframe for signals
bsd-user/arm/target_arch_signal.h: arm specific signal registers and stack
bsd-user/arm/target_arch_elf.h: arm get_hwcap2 impl
bsd-user/arm/target_arch_elf.h: arm get hwcap
bsd-user/arm/target_arch_elf.h: arm defines for ELF
bsd-user/arm/target_arch_thread.h: Routines to create and switch to a thread
bsd-user/arm/target_arch_sigtramp.h: Signal Trampoline for arm
bsd-user/arm/target_arch_vmparam.h: Parameters for arm address space
bsd-user/arm/target_arch_reg.h: Implement core dump register copying
bsd-user/arm/target_arch_cpu.h: Implement system call dispatch
bsd-user/arm/target_arch_cpu.h: Implement data abort exceptions
bsd-user/arm/target_arch_cpu.h: Implement trivial EXCP exceptions
bsd-user/arm/target_arch_cpu.h: Dummy target_cpu_loop implementation
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Merge tag 'pull-riscv-to-apply-20220108' of github.com:alistair23/qemu into staging
Second RISC-V PR for QEMU 7.0
- Fix illegal instruction when PMP is disabled
- SiFive PDMA 64-bit support
- SiFive PLIC cleanups
- Mark Hypervisor extension as non experimental
- Enable Hypervisor extension by default
- Support 32 cores on the virt machine
- Corrections for the Vector extension
- Experimental support for 128-bit CPUs
- stval and mtval support for illegal instructions
# gpg: Signature made Fri 07 Jan 2022 09:50:11 PM PST
# gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054
* tag 'pull-riscv-to-apply-20220108' of github.com:alistair23/qemu: (37 commits)
target/riscv: Implement the stval/mtval illegal instruction
target/riscv: Fixup setting GVA
target/riscv: Set the opcode in DisasContext
target/riscv: actual functions to realize crs 128-bit insns
target/riscv: modification of the trans_csrxx for 128-bit support
target/riscv: helper functions to wrap calls to 128-bit csr insns
target/riscv: adding high part of some csrs
target/riscv: support for 128-bit M extension
target/riscv: support for 128-bit arithmetic instructions
target/riscv: support for 128-bit shift instructions
target/riscv: support for 128-bit U-type instructions
target/riscv: support for 128-bit bitwise instructions
target/riscv: accessors to registers upper part and 128-bit load/store
target/riscv: moving some insns close to similar insns
target/riscv: setup everything for rv64 to support rv128 execution
target/riscv: array for the 64 upper bits of 128-bit registers
target/riscv: separation of bitwise logic and arithmetic helpers
target/riscv: additional macros to check instruction support
qemu/int128: addition of div/rem 128-bit operations
exec/memop: Adding signed quad and octo defines
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Warner Losh [Thu, 4 Nov 2021 23:08:04 +0000 (17:08 -0600)]
bsd-user/arm/target_arch_signal.h: Define size of *context_t
Define the native sizes of mcontext_t and ucontext_t so that the tests
in target_os_ucontext.h ensure the size of arm's version of these
structures is correct.
Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
projects / mirror_qemu.git / log