Because CCN's cycle counter always runs, it will generate
an interrupt on overflow even if the relevant perf event
was not requested, causing a spurious warning message.
Fixed now by warning on only normal counter unwanted
overflows. Also cleaning the overflow mask at init now,
not to warn on event previously requested by firmware.
This adds a SoC driver to be used by the ARM RealView
reference boards. We create the "versatile" directory to hold
the different ARM reference designs as per the pattern of the
clk directory layout. The driver utilze the syscon to get to
the register needed. After this we can use sysfs to get at
some SoC properties on RealView DT variants like this:
> cd /sysbus/soc/devices/soc0
> ls
board family machine power subsystem
build fpga manufacturer soc_id uevent
> cat family
Versatile
> cat fpga
Multi-layer AXI
> cat board
HBI-0147
> cat build
03
Linus Walleij [Thu, 22 May 2014 08:20:38 +0000 (10:20 +0200)]
power: reset: driver for the Versatile syscon reboot
This driver enabled us to drive the reboot of the Versatile family
of ARM reference boards. Even though only the RealView boards are
supported initially, these boards all have the same procedure for
reboot:
- Write a magic value into an unlocking register
- Write another magic value into a reset control register
The driver will be reusable for Versatile and possibly also the
Integrator family of reference boards.
Cc: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> Cc: David Woodhouse <dwmw2@infradead.org> Acked-By: Sebastian Reichel <sre@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Linus Walleij [Wed, 21 May 2014 22:34:16 +0000 (00:34 +0200)]
leds: add a driver for syscon-based LEDs
This makes it possible to create a set of LEDs from a syscon
MFD instance, which is lean mean and clean on the ARM
reference designs and can replace the Versatile LEDs driver
in the long run, as well as other custom syscon LEDs drivers.
Merge tag 'sunxi-drivers-for-3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into next/drivers
Pull "Allwinner drivers additions for 3.18" from Maxime Ripard:
Nothing major, just handling the RTC driver changes needed for the A31/A23.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* tag 'sunxi-drivers-for-3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux:
rtc: sunxi: Depend on platforms sun4i/sun7i that actually have the rtc
rtc: sun6i: Add sun6i RTC driver
Olof Johansson [Wed, 24 Sep 2014 17:35:48 +0000 (10:35 -0700)]
Merge tag 'drivers-soc-ti-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone into next/drivers
Merge "soc: Keystone SOC Navigator drivers for 3.18" from Santosh Shilimkar:
Keystone SOC Navigator drivers for 3.18
The Keystone Multi-core Navigator contains QMSS and packet DMA
subsystems which interwork together to form the Navigator cloud
used by various subsystems like NetCP, SRIO, SideBand Crypto
engines etc.
The Keystone Navigator DMA driver sets up the dma channels and flows for
the QMSS(Queue Manager SubSystem) who triggers the actual data movements
across clients using destination queues. Every client modules like
NETCP(Network Coprocessor), SRIO(Serial Rapid IO) and CRYPTO
Engines has its own instance of packet dma hardware. QMSS has also
an internal packet DMA module which is used as an infrastructure
DMA with zero copy.
Initially this driver was proposed as DMA engine driver but since the
hardware is not typical DMA engine and hence doesn't comply with typical
DMA engine driver needs, that approach was naked. Link to that
discussion -
https://lkml.org/lkml/2014/3/18/340
As aligned, now we pair the Navigator DMA with its companion Navigator
QMSS subsystem driver.
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Kumar Gala <galak@codeaurora.org> Cc: Olof Johansson <olof@lixom.net> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Grant Likely <grant.likely@linaro.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Sandeep Nair <sandeep_n@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
The Keystone Navigator DMA driver sets up the dma channels and flows for
the QMSS(Queue Manager SubSystem) who triggers the actual data movements
across clients using destination queues. Every client modules like
NETCP(Network Coprocessor), SRIO(Serial Rapid IO) and CRYPTO
Engines has its own instance of packet dma hardware. QMSS has also
an internal packet DMA module which is used as an infrastructure
DMA with zero copy.
Initially this driver was proposed as DMA engine driver but since the
hardware is not typical DMA engine and hence doesn't comply with typical
DMA engine driver needs, that approach was naked. Link to that
discussion -
https://lkml.org/lkml/2014/3/18/340
As aligned, now we pair the Navigator DMA with its companion Navigator
QMSS subsystem driver.
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Kumar Gala <galak@codeaurora.org> Cc: Olof Johansson <olof@lixom.net> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Grant Likely <grant.likely@linaro.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Sandeep Nair <sandeep_n@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Sandeep Nair [Fri, 28 Feb 2014 15:47:50 +0000 (10:47 -0500)]
soc: ti: add Keystone Navigator QMSS driver
The QMSS (Queue Manager Sub System) found on Keystone SOCs is one of
the main hardware sub system which forms the backbone of the Keystone
Multi-core Navigator. QMSS consist of queue managers, packed-data structure
processors(PDSP), linking RAM, descriptor pools and infrastructure
Packet DMA.
The Queue Manager is a hardware module that is responsible for accelerating
management of the packet queues. Packets are queued/de-queued by writing or
reading descriptor address to a particular memory mapped location. The PDSPs
perform QMSS related functions like accumulation, QoS, or event management.
Linking RAM registers are used to link the descriptors which are stored in
descriptor RAM. Descriptor RAM is configurable as internal or external memory.
The QMSS driver manages the PDSP setups, linking RAM regions,
queue pool management (allocation, push, pop and notify) and descriptor
pool management. The specifics on the device tree bindings for
QMSS can be found in:
Documentation/devicetree/bindings/soc/keystone-navigator-qmss.txt
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Kumar Gala <galak@codeaurora.org> Cc: Olof Johansson <olof@lixom.net> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Grant Likely <grant.likely@linaro.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Sandeep Nair <sandeep_n@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
The QMSS (Queue Manager Sub System) found on Keystone SOCs is one of
the main hardware sub system which forms the backbone of the Keystone
Multi-core Navigator. QMSS consist of queue managers, packed-data structure
processors(PDSP), linking RAM, descriptor pools and infrastructure
Packet DMA.
The Queue Manager is a hardware module that is responsible for accelerating
management of the packet queues. Packets are queued/de-queued by writing or
reading descriptor address to a particular memory mapped location. The PDSPs
perform QMSS related functions like accumulation, QoS, or event management.
Linking RAM registers are used to link the descriptors which are stored in
descriptor RAM. Descriptor RAM is configurable as internal or external memory.
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Kumar Gala <galak@codeaurora.org> Cc: Olof Johansson <olof@lixom.net> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Grant Likely <grant.likely@linaro.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Sandeep Nair <sandeep_n@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Olof Johansson [Wed, 24 Sep 2014 05:10:18 +0000 (22:10 -0700)]
Merge tag 'mailbox-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/drivers
Mailbox related changes for omaps to get it to work with
device tree.
* tag 'mailbox-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
mailbox/omap: add support for parsing dt devices
Documentation: dt: add omap mailbox bindings
Olof Johansson [Wed, 24 Sep 2014 05:08:40 +0000 (22:08 -0700)]
Merge tag 'intc-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/drivers
Merge "omap intc changes for v3.18 merge window" from Tony Lindgren:
Interrupt code related clean-up for omap2 and 3 to make
it ready to move to drivers/irqchip. Note that this series
does not yet move the interrupt code to drivers, that will
be posted separately as a follow-up series.
Note that this branch has a dependency to patches both
in fixes-v3.18-not-urgent and soc-for-v3.18 and is based on
a merge. Without doing the merge, off-idle would not work
properly for git bisect.
* tag 'intc-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (325 commits)
arm: omap: intc: switch over to linear irq domain
arm: omap: irq: get rid of ifdef hack
arm: omap: irq: introduce omap_nr_pending
arm: omap: irq: remove nr_irqs argument
arm: omap: irq: remove unnecessary header
arm: omap: irq: drop omap2_intc_handle_irq()
arm: omap: irq: drop omap3_intc_handle_irq()
arm: omap: irq: call set_handle_irq() from .init_irq
arm: omap: irq: move some more code around
arm: boot: dts: omap2/3/am33xx: drop ti,intc-size
arm: omap: irq: drop ti,intc-size support
arm: boot: dts: am33xx/omap3: fix intc compatible flag
arm: omap: irq: use compatible flag to figure out number of IRQ lines
arm: omap: irq: add specific compatibles for omap3 and am33xx devices
arm: omap: irq: drop .handle_irq and .init_irq fields
arm: omap: irq: use IRQCHIP_DECLARE macro
arm: omap: irq: call set_handle_irq() from intc_of_init
arm: omap: irq: make intc_of_init static
arm: omap: irq: reorganize code a little bit
arm: omap: irq: always define omap3 support
...
Olof Johansson [Wed, 24 Sep 2014 04:58:35 +0000 (21:58 -0700)]
Merge tag 'at91-drivers2' of git://github.com/at91linux/linux-at91 into next/drivers
Merge " Second drivers series for AT91/3.18" from Nicolas Ferre:
- move of the PIT (basic timer) from mach-at91 to its proper location:
drivers/clocksource
- big cleanup of this driver along the way
* tag 'at91-drivers2' of git://github.com/at91linux/linux-at91:
ARM: at91: PIT: Move the driver to drivers/clocksource
ARM: at91: Give the PIT irq as an argument of at91sam926x_pit_init
ARM: at91: Convert the boards to the init_time callback
ARM: at91: soc: Add init_time callback
ARM: at91: PIT: (Almost) remove the global variables
ARM: at91: PIT: use request_irq instead of setup_irq
ARM: at91: PIT: Use pr_fmt
ARM: at91: PIT: Use consistent exit path in probe
ARM: at91: dt: Remove init_time definitions
ARM: at91: PIT: Rework probe functions
ARM: at91: PIT: Use of_have_populated_dt instead of CONFIG_OF
ARM: at91: PIT: Use DIV_ROUND_CLOSEST to compute the cycles
ARM: at91: generic.h: Add include safe guards
ARM: at91: PIT: Follow the general coding rules
Chen-Yu Tsai [Tue, 26 Aug 2014 03:54:56 +0000 (11:54 +0800)]
rtc: sunxi: Depend on platforms sun4i/sun7i that actually have the rtc
Now that we have Kconfig options for individual sunxi platforms, let
the rtc-sunxi driver depend on the platforms that actually have this
hardware, sun4i and sun7i.
Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Chen-Yu Tsai [Tue, 26 Aug 2014 03:54:55 +0000 (11:54 +0800)]
rtc: sun6i: Add sun6i RTC driver
This patch introduces the driver for the RTC in the Allwinner A31 and
A23 SoCs.
Unlike the RTC found in A10/A20 SoCs, which was part of the timer, the
RTC in A31/A23 are a separate hardware block, which also contain a few
controls for the RTC block hardware (a regulator and RTC block GPIO pin
latches), while also having separate interrupts for the alarms.
The hardware is different enough to make a different driver for it.
of_iomap(), which is called from omap_init_irq_of(),
already takes care of making sure we have a valid
resource to deal with. Because of that, we can
safely remove our explicit call to of_address_to_resource().
Acked-by: Jason Cooper <jason@lakedaemon.net> Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Felipe Balbi [Mon, 15 Sep 2014 21:15:01 +0000 (16:15 -0500)]
irqchip: add irq-omap-intc.h header
OMAP INTC irqchip driver will be moved under
drivers/irqchip/ soon but we still have a dependency
with mach-omap2 when it comes to idle functions.
In order to make it easy to share those function
prototypes with OMAP PM code, we introduce this new
header.
To avoid modifying several board-files and some of
the PM-related code, we just include the new header
from common.h which was already included by all
users of IRQ-related PM code.
Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Felipe Balbi [Tue, 9 Sep 2014 00:54:58 +0000 (17:54 -0700)]
arm: omap: intc: switch over to linear irq domain
now that we don't need to support legacy board-files,
we can completely switch over to a linear irq domain
and make use of irq_alloc_domain_generic_chips() to
allocate all generic irq chips for us.
Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Felipe Balbi [Tue, 9 Sep 2014 00:54:57 +0000 (17:54 -0700)]
arm: omap: irq: get rid of ifdef hack
we don't need the ifdef if we have omap_nr_pending
telling us how many pending registers we have
on current platform. This solves a possible
problem where we could try to handle bogus
interrupts on OMAP2 and OMAP3 if using single
zImage kernel, because we would end up reading
the following pending FIQ register.
Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Felipe Balbi [Tue, 9 Sep 2014 00:54:51 +0000 (17:54 -0700)]
arm: omap: irq: move some more code around
We want .init_irq to call set_irq_handle() for
legacy platforms. Note that this code will also
be dropped once omap2/3 devices are completely
moved to DT.
Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Felipe Balbi [Tue, 9 Sep 2014 00:54:32 +0000 (17:54 -0700)]
arm: omap: irq: start to remove irq_banks array
We have a single bank in that array, this patch
is in preparation to remove that array. It just
shifts everything to a new set of functions
for register IO while also removing old ones.
Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
of_device_ids (i.e. compatible strings and the respective data) are not
supposed to change at runtime. All functions working with of_device_ids
provided by <linux/of.h> work with const of_device_ids. So mark the
non-const function parameters and structs for OMAP2+ as const, too.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Tony Lindgren <tony@atomide.com>
Suman Anna [Wed, 10 Sep 2014 19:20:59 +0000 (14:20 -0500)]
mailbox/omap: add support for parsing dt devices
Logic has been added to the OMAP2+ mailbox code to parse the
mailbox dt nodes and construct the different sub-mailboxes
associated with the instance. The DT representation of the
sub-mailbox devices is different from legacy platform data
representation to allow flexibility of interrupt configuration
between Tx and Rx fifos (to also possibly allow simplex devices
in the future). The DT representation gathers similar information
that was being passed previously through the platform data, except
for the interrupt type information, which is gathered through driver
compatible match data.
The non-DT support has to be maintained for now to not break
OMAP3 legacy boot, and the legacy-style code will be cleaned
up once OMAP3 is also converted to DT-boot only.
Cc: Jassi Brar <jassisinghbrar@gmail.com> Cc: Rob Herring <robh+dt@kernel.org> Signed-off-by: Suman Anna <s-anna@ti.com> Acked-by: Pavel Machek <pavel@ucw.cz> Signed-off-by: Tony Lindgren <tony@atomide.com>
Suman Anna [Wed, 10 Sep 2014 19:20:58 +0000 (14:20 -0500)]
Documentation: dt: add omap mailbox bindings
Add the device tree bindings document for OMAP2+ mailbox.
Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Merge tag 'socfpga_driver_for_v3.18' of git://git.rocketboards.org/linux-socfpga-next into next/drivers
Pull "SOCFPGA driver update for v3.18" from Dinh Nguyen:
This is the EDAC driver for EDAC. Boris had given me permission to
take this patch together with it's DTS component. The DTS portion was in the
previous pull request.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* tag 'socfpga_driver_for_v3.18' of git://git.rocketboards.org/linux-socfpga-next:
edac: altera: Add Altera SDRAM EDAC support
Mark Brown [Sat, 6 Sep 2014 10:14:16 +0000 (11:14 +0100)]
ARM: omap: Remove stray ARCH_HAS_OPP references
OPP is now a normal kernel library selected by its users rather than a
feature that architectures need to enable so ARCH_HAS_OPP serves no
function any more - remove the selects.
Signed-off-by: Mark Brown <broonie@kernel.org> Acked-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
ARM: OMAP5: Add hook in SoC initcalls to enable pm initialization
With consolidated code, now we can add the required hooks for
OMAP5 to enable power management.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
[nm@ti.com: minor rebase updates] Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kevin Hilman <khilman@linaro.org> Tested-by: Kevin Hilman <khilman@linaro.org>
Rajendra Nayak [Mon, 27 May 2013 10:16:44 +0000 (15:46 +0530)]
ARM: OMAP5 / DRA7: Enable CPU RET on suspend
On OMAP5 / DRA7, prevent a CPU powerdomain OFF and resulting MPU OSWR
and instead attempt a CPU RET and side effect, MPU RET in suspend.
NOTE: the hardware was originally designed to be capable of achieving
deep power states such as OFF and OSWR, however due to various issues
and risks, deepest valid state was determined to be CSWR - hence we use
the errata framework to handle this case.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[nm@ti.com: updates] Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kevin Hilman <khilman@linaro.org> Tested-by: Kevin Hilman <khilman@linaro.org>
ARM: OMAP5 / DRA7: PM: Provide a dummy startup function for CPU hotplug
Dont assume that all OMAP4+ code will be able to use OMAP4 hotplug
logic. On OMAP5, DRA7, we do not need this in place yet, also,
currently the CPU startup pointer is located in omap4_cpu_pm_info
instead of cpu_pm_ops.
So, isolate the function to hotplug_restart pointer in cpu_pm_ops
where it should have belonged, initalize them as per valid startup
pointers for OMAP4430/60 as in current logic, however provide
dummy_cpu_resume to be the startup location as well.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
[nm@ti.com: split this out of original code and isolate it] Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kevin Hilman <khilman@linaro.org> Tested-by: Kevin Hilman <khilman@linaro.org>
Rajendra Nayak [Fri, 3 May 2013 10:04:40 +0000 (15:34 +0530)]
ARM: OMAP5 / DRA7: PM: Avoid all SAR saves
Get rid of all assumptions about always having a sar base on *all*
OMAP4+ platforms. We dont need one on DRA7 and it is not necessary at
this point for OMAP5 either.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[nm@ti.com: Split and optimize] Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kevin Hilman <khilman@linaro.org> Tested-by: Kevin Hilman <khilman@linaro.org>
In addition to the standard power-management technique, the OMAP5 / DRA7
MPU subsystem also employs an SR3-APG (mercury) power management
technology to reduce leakage.
It allows for full logic and memories retention on MPU_C0 and MPU_C1 and
is controlled by the PRCM_MPU. Only "Fast-mode" is supported on the
OMAP5 and DRA7 family of processors.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
[nm@ti.com: minor consolidation] Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kevin Hilman <khilman@linaro.org> Tested-by: Kevin Hilman <khilman@linaro.org>
Enables MPUSS ES2 power management mode using ES2_PM_MODE in
AMBA_IF_MODE register.
0x0: OMAP5 ES1 behavior, CPU cores would enter and exit OFF mode together.
Broken! Fortunately, we do not support this anymore.
0x1: OMAP5 ES2, DRA7 behavior, CPU cores are allowed to enter/exit OFF mode
independently.
This is one time settings thanks to always ON domain.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
[nm@ti.com: minor conflict resolutions, consolidation for DRA7] Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kevin Hilman <khilman@linaro.org> Tested-by: Kevin Hilman <khilman@linaro.org>
ARM: OMAP5 / DRA7: PM: Set MPUSS-EMIF clock-domain static dependency
With EMIF clock-domain put under hardware supervised control, memory
corruption and untraceable crashes are observed on OMAP5. Further
investigation revealed that there is a weakness in the PRCM on this
specific dynamic depedency.
The recommendation is to set MPUSS static dependency towards EMIF
clock-domain to avoid issues. This recommendation holds good for DRA7
family of devices as well.
ARM: OMAP5 / DRA7: PM: Update CPU context register offset
On OMAP5, RM_CPUi_CPUi_CONTEXT offset has changed. Update the code
so that same code works for OMAP4+ devices. DRA7 and OMAP5 have the same
context offset as well.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
[rnayak@ti.com: for DRA7] Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[nm@ti.com: rebase, split/merge etc..] Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kevin Hilman <khilman@linaro.org> Tested-by: Kevin Hilman <khilman@linaro.org>
Nishanth Menon [Fri, 6 Jun 2014 06:17:37 +0000 (01:17 -0500)]
ARM: OMAP4+: PM: use only valid low power state for suspend
We are using power domain state as RET and logic state as OFF. This
state is OSWR. This may not always be supported on ALL power domains. In
fact, on certain power domains, this might result in a hang on certain
platforms. Instead, depend on powerdomain data to provide accurate
information about the supported powerdomain states and use the
appropriate function to query and use it as part of suspend path.
Nishanth Menon [Fri, 6 Jun 2014 02:40:39 +0000 (21:40 -0500)]
ARM: OMAP4+: PM: Make logic state programmable
Move the logic state as different for each power domain. This allows us
to customize the deepest power state we should target over all for each
powerdomain in the follow on patches.
Nishanth Menon [Fri, 6 Jun 2014 06:04:20 +0000 (01:04 -0500)]
ARM: OMAP2+: powerdomain: introduce logic for finding valid power domain
powerdomain configuration in OMAP is done using PWRSTCTRL register for
each power domain. However, PRCM lets us write any value we'd like to
the logic and power domain target states, however the SoC integration
tends to actually function only at a few discrete states. These valid
states are already in our powerdomains_xxx_data.c file.
So, provide a function to easily query valid low power state that the
power domain is allowed to go to.
Based on work originally done by Jean Pihet <j-pihet@ti.com>
https://patchwork.kernel.org/patch/1325091/ . There is no attempt to
create a new powerdomain solution here, except fixing issues seen
attempting invalid programming attempts. Future consolidation to the
generic powerdomain framework should consider this requirement as
well.
Similar solutions have been done in product kernels in the past such
as:
https://android.googlesource.com/kernel/omap.git/+blame/android-omap-panda-3.0/arch/arm/mach-omap2/pm44xx.c
Nishanth Menon [Tue, 12 Aug 2014 12:05:19 +0000 (07:05 -0500)]
ARM: OMAP3+: PRM: register interrupt information from DT
Allow the PRM interrupt information to be picked up from device tree.
OMAP3 may use legacy boot and needs to be compatible with old dtbs
(without interrupt populated), for these, we use the value which is
pre-populated.
Nishanth Menon [Thu, 22 May 2014 20:19:29 +0000 (15:19 -0500)]
ARM: OMAP4+: PRM: register interrupt information from DT
Allow the PRM interrupt information to be picked up from device tree.
the only exception is for OMAP4 which uses values pre-populated and allows
compatibility with older dtb.
Nishanth Menon [Thu, 22 May 2014 19:53:54 +0000 (14:53 -0500)]
ARM: OMAP4+: prminst: provide function to find prm_dev instance offset
PRM device instance can vary depending on SoC. We already handle the
same during reset of the device, However, this is also needed
for other logic instances. So, first abstract this out to a generic
function.
Merge tag 'at91-drivers' of git://github.com/at91linux/linux-at91 into next/drivers
Merge "First batch of AT91 drivers for 3.18" from Nicolas Ferre:
- reset, poweroff and ram drivers are moved to their proper
location instead of being in mach-at91 directory. They now use
the appropriate frameworks.
- big amount of removal of these machine specific drivers and use
of the newly created drivers. This lead to an overhaul of the setup.c AT91
startup code.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* tag 'at91-drivers' of git://github.com/at91linux/linux-at91: (31 commits)
power: reset: at91-poweroff: fix wakeup status register index
ARM: at91/power/reset: fix Kconfig "depends on" directive
ARM: at91: fix ramc standby function registration
ARM: at91: Remove rstc and shdwc headers
ARM: at91: Remove rstc and shdwnc global base addresses
ARM: at91/pm: Remove show_reset_status function
ARM: at91: Remove poweroff code
ARM: at91: Register the poweroff driver
ARM: at91: Remove poweroff DT probing
ARM: at91: Remove reset code from the machine code
ARM: at91: Call at91_register_devices in the board files
ARM: at91: Probe the reset driver
ARM: at91/soc: Introduce register_devices callback
ARM: at91: Remove the old-style reset probing
ARM: at91: Rework ramc mapping code
ARM: at91: setup: Switch to pr_fmt
ARM: at91: remove old irq material
ARM: at91: make use of the new AIC driver for dt enabled boards
ARM: at91: enclose at91_aic_xx calls in IS_ENABLED(CONFIG_OLD_IRQ_AT91) blocks
ARM: at91: introduce OLD_IRQ_AT91 Kconfig option
...
This patch adds support for the CycloneV and ArriaV SDRAM controllers.
Correction and reporting of SBEs, Panic on DBEs.
There was a discussion thread on whether this driver should be an mfd driver
or just make use of syscon, which is already a mfd. Ultimately, the
decision to use a simple syscon interface was reached.[1]
[1] https://lkml.org/lkml/2014/7/30/514
[dinguyen] Fixed Kconfig to have EDAC_ALTERA_MC as a tristate to prevent a
build failure for allmodconfig.
ARM: dts: am335x-bone*: Fix model name and update compatibility information
Beaglebone white and beaglebone black differ in tiny little aspects.
This is the reason why we maintain seperate dts for these platforms.
However, there is no real way to decode from dtb which platform it is
since compatible and model name are the same for both platforms.
Fix this so that beaglebone black and beaglebone are identifiable,
while maintaining compatibility for older zImages which might use old
beaglebone compatible flag for black as well.
Reported-by: Tom Rini <trini@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Nishanth Menon [Thu, 28 Aug 2014 20:45:03 +0000 (15:45 -0500)]
ARM: dts: omap4-panda: Fix model and SoC family details
Currently we claim that omap4-panda and omap4-panda-es are essentially
the same, but they are not since PandaBoard-ES uses OMAP4460 and
PandaBoard uses OMAP4430.
So, split the common definition and make the model name available.
Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Maxime Ripard [Tue, 1 Jul 2014 09:33:25 +0000 (11:33 +0200)]
ARM: at91: Convert the boards to the init_time callback
Now that we have the init_time callback in the at91_init_soc structure, convert
all the boards and SoC to this.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Boris BREZILLON <boris.brezillon@free-electrons.com> Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
projects / mirror_ubuntu-zesty-kernel.git / log