]> git.proxmox.com Git - mirror_ubuntu-eoan-kernel.git/commit
arm64: Fix barriers used for page table modifications
authorCatalin Marinas <catalin.marinas@arm.com>
Mon, 9 Jun 2014 10:55:03 +0000 (11:55 +0100)
committerCatalin Marinas <catalin.marinas@arm.com>
Thu, 24 Jul 2014 09:25:42 +0000 (10:25 +0100)
commit7f0b1bf04511348995d6fce38c87c98a3b5cb781
tree87753459f2311e56a783cd4dcaceb768bf5ce494
parent383c2799113b00a5f12c820ff0fd3dfca9e5be89
arm64: Fix barriers used for page table modifications

The architecture specification states that both DSB and ISB are required
between page table modifications and subsequent memory accesses using the
corresponding virtual address. When TLB invalidation takes place, the
tlb_flush_* functions already have the necessary barriers. However, there are
other functions like create_mapping() for which this is not the case.

The patch adds the DSB+ISB instructions in the set_pte() function for
valid kernel mappings. The invalid pte case is handled by tlb_flush_*
and the user mappings in general have a corresponding update_mmu_cache()
call containing a DSB. Even when update_mmu_cache() isn't called, the
kernel can still cope with an unlikely spurious page fault by
re-executing the instruction.

In addition, the set_pmd, set_pud() functions gain an ISB for
architecture compliance when block mappings are created.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Reported-by: Leif Lindholm <leif.lindholm@linaro.org>
Acked-by: Steve Capper <steve.capper@linaro.org>
Cc: Will Deacon <will.deacon@arm.com>
Cc: <stable@vger.kernel.org>
arch/arm64/include/asm/cacheflush.h
arch/arm64/include/asm/pgtable.h
arch/arm64/include/asm/tlbflush.h