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drm/i915: start writing infoframes at address 0 on gen 4
2012-05-08 Paulo Zanonidrm/i915: start writing infoframes at address 0 on...
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
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2012-05-08 Paulo Zanonidrm/i915: change coding style of the write_infoframe...
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
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2012-05-08 Paulo Zanonidrm/i915: DSL_LINEMASK is 12 bits only on gen2
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
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2012-05-03 Paulo Zanonidrm/i915: enable dip before writing data on gen4
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
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2012-05-03 Paulo Zanonidrm/i915: make DBLCLK modes work
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
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2012-05-03 Paulo Zanonidrm/i915: rename AVI InfoFrame field 'PR' to 'YQ_CN_PR'
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
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2012-04-20 Paulo Zanonidrm: add DRM_MODE_FLAG_DBLCLK to CEA modes requiring it
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
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2012-04-20 Paulo Zanonidrm: add the VIC number to the CEA EDID modes
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
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2012-02-14 Paulo Zanonidrm/i915: add missing SDVO bits for interlaced modes...
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
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2012-02-10 Paulo Zanonidrm/i915: set interlaced bits for TRANSCONF
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
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2012-01-06 Paulo Zanonidrm/i915/sdvo: always set positive sync polarity
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
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2011-12-16 Paulo Zanonidrm/i915: add PCH info to i915_capabilities
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
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2011-12-16 Paulo Zanonidrm/i915: set the right SDVO transcoder for CPT
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
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