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target/riscv: Set opcode to env->bins for illegal/virtual instruction fault
2023-05-05 Weiwei Litarget/riscv: Set opcode to env->bins for illegal/virtual...
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20230330034636.44585-1-liweiwei@iscas.ac.cn>
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2023-05-05 Weiwei Litarget/riscv: Fix addr type for get_physical_address
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20230329101928.83856-1-liweiwei@iscas.ac.cn>
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2023-05-05 Weiwei Litarget/riscv: Remove redundant parentheses
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20230327080858.39703-8-liweiwei@iscas.ac.cn>
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2023-05-05 Weiwei Litarget/riscv: Remove check on RVH for riscv_cpu_set_virt_enabled
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20230327080858.39703-5-liweiwei@iscas.ac.cn>
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2023-05-05 Weiwei Litarget/riscv: Remove check on RVH for riscv_cpu_virt_enabled
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20230327080858.39703-4-liweiwei@iscas.ac.cn>
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2023-05-05 Weiwei Litarget/riscv: Remove redundant check on RVH
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20230327080858.39703-3-liweiwei@iscas.ac.cn>
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2023-05-05 Weiwei Litarget/riscv: Remove redundant call to riscv_cpu_virt_enabled
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20230327080858.39703-2-liweiwei@iscas.ac.cn>
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2023-05-05 Weiwei Litarget/riscv: Add support for Zce
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20230307081403.61950-11-liweiwei@iscas.ac.cn>
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2023-05-05 Weiwei Lidisas/riscv.c: add disasm support for Zc*
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20230307081403.61950-10-liweiwei@iscas.ac.cn>
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2023-05-05 Weiwei Litarget/riscv: expose properties for Zc* extension
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20230307081403.61950-9-liweiwei@iscas.ac.cn>
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2023-05-05 Weiwei Litarget/riscv: add support for Zcmt extension
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20230307081403.61950-8-liweiwei@iscas.ac.cn>
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2023-05-05 Weiwei Litarget/riscv: add support for Zcmp extension
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20230307081403.61950-7-liweiwei@iscas.ac.cn>
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2023-05-05 Weiwei Litarget/riscv: add support for Zcb extension
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20230307081403.61950-6-liweiwei@iscas.ac.cn>
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2023-05-05 Weiwei Litarget/riscv: add support for Zcd extension
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20230307081403.61950-5-liweiwei@iscas.ac.cn>
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2023-05-05 Weiwei Litarget/riscv: add support for Zcf extension
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20230307081403.61950-4-liweiwei@iscas.ac.cn>
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2023-05-05 Weiwei Litarget/riscv: add support for Zca extension
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20230307081403.61950-3-liweiwei@iscas.ac.cn>
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2023-05-05 Weiwei Litarget/riscv: add cfg properties for Zc* extension
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20230307081403.61950-2-liweiwei@iscas.ac.cn>
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2023-05-05 Weiwei Litarget/riscv: Simplify arguments for riscv_csrrw_check
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20230309071329.45932-5-liweiwei@iscas.ac.cn>
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2023-05-05 Weiwei Litarget/riscv: Simplify type conversion for CPURISCVState
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20230309071329.45932-4-liweiwei@iscas.ac.cn>
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2023-05-05 Weiwei Litarget/riscv: Simplify getting RISCVCPU pointer from env
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20230309071329.45932-3-liweiwei@iscas.ac.cn>
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2023-05-05 Weiwei Litarget/riscv: Avoid env_archcpu() when reading RISCVCPUConfig
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20230309071329.45932-2-liweiwei@iscas.ac.cn>
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2023-05-02 Weiwei Liaccel/tcg: Uncache the host address for instruction...
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20230422130329.23555-6-liweiwei@iscas.ac.cn>
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2023-04-04 Weiwei Liaccel/tcg: Fix overwrite problems of tcg_cflags
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20230331150609.114401-6-liweiwei@iscas.ac.cn>
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2023-03-02 Weiwei Litarget/riscv: Export Svadu property
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-ID: <20230224040852.37109-7-liweiwei@iscas.ac.cn>
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2023-03-02 Weiwei Litarget/riscv: Add *envcfg.HADE related check in address...
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-ID: <20230224040852.37109-6-liweiwei@iscas.ac.cn>
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2023-03-02 Weiwei Litarget/riscv: Add *envcfg.PBMTE related check in address...
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-ID: <20230224040852.37109-5-liweiwei@iscas.ac.cn>
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2023-03-02 Weiwei Litarget/riscv: Add csr support for svadu
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-ID: <20230224040852.37109-4-liweiwei@iscas.ac.cn>
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2023-03-02 Weiwei Litarget/riscv: Fix the relationship of PBMTE/STCE fields...
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-ID: <20230224040852.37109-3-liweiwei@iscas.ac.cn>
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2023-03-02 Weiwei Litarget/riscv: Fix the relationship between menvcfg...
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-ID: <20230224040852.37109-2-liweiwei@iscas.ac.cn>
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2023-03-02 Weiwei Litarget/riscv: Add support for Zicond extension
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-ID: <20230221091009.36545-1-liweiwei@iscas.ac.cn>
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2023-03-01 Weiwei Litarget/riscv: Expose properties for Zv* extensions
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-ID: <20230215020539.4788-15-liweiwei@iscas.ac.cn>
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2023-03-01 Weiwei Litarget/riscv: Simplify check for EEW = 64 in trans_rvv...
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-ID: <20230215020539.4788-14-liweiwei@iscas.ac.cn>
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2023-03-01 Weiwei Litarget/riscv: Fix check for vector load/store instructions...
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-ID: <20230215020539.4788-13-liweiwei@iscas.ac.cn>
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2023-03-01 Weiwei Litarget/riscv: Add support for Zvfh/zvfhmin extensions
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-ID: <20230215020539.4788-12-liweiwei@iscas.ac.cn>
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2023-03-01 Weiwei Litarget/riscv: Remove redundunt check for zve32f and...
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-ID: <20230215020539.4788-11-liweiwei@iscas.ac.cn>
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2023-03-01 Weiwei Litarget/riscv: Replace check for F/D to Zve32f/Zve64d...
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-ID: <20230215020539.4788-10-liweiwei@iscas.ac.cn>
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2023-03-01 Weiwei Litarget/riscv: Simplify check for Zve32f and Zve64f
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-ID: <20230215020539.4788-9-liweiwei@iscas.ac.cn>
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2023-03-01 Weiwei Litarget/riscv: Indent fixes in cpu.c
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-ID: <20230215020539.4788-8-liweiwei@iscas.ac.cn>
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2023-03-01 Weiwei Litarget/riscv: Add property check for Zvfh{min} extensions
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-ID: <20230215020539.4788-7-liweiwei@iscas.ac.cn>
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2023-03-01 Weiwei Litarget/riscv: Fix relationship between V, Zve*, F and D
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-ID: <20230215020539.4788-6-liweiwei@iscas.ac.cn>
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2023-03-01 Weiwei Litarget/riscv: Add cfg properties for Zv* extensions
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-ID: <20230215020539.4788-5-liweiwei@iscas.ac.cn>
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2023-03-01 Weiwei Litarget/riscv: Simplify the check for Zfhmin and Zhinxmin
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-ID: <20230215020539.4788-4-liweiwei@iscas.ac.cn>
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2023-03-01 Weiwei Litarget/riscv: Fix the relationship between Zhinxmin...
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-ID: <20230215020539.4788-3-liweiwei@iscas.ac.cn>
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2023-03-01 Weiwei Litarget/riscv: Fix the relationship between Zfhmin and Zfh
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-ID: <20230215020539.4788-2-liweiwei@iscas.ac.cn>
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2022-09-26 Weiwei Litarget/riscv: fix csr check for cycle{h}, instret{h...
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20220817083756.12471-1-liweiwei@iscas.ac.cn>
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2022-09-07 Weiwei Litarget/riscv: Fix priority of csr related check in...
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20220803123652.3700-1-liweiwei@iscas.ac.cn>
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2022-09-07 Weiwei Litarget/riscv: Simplify the check in hmode to reuse...
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20220718130955.11899-7-liweiwei@iscas.ac.cn>
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2022-09-07 Weiwei Litarget/riscv: Fix checks in hmode/hmode32
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20220718130955.11899-6-liweiwei@iscas.ac.cn>
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2022-09-07 Weiwei Litarget/riscv: Add check for csrs existed with U extension
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20220718130955.11899-5-liweiwei@iscas.ac.cn>
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2022-09-07 Weiwei Litarget/riscv: Fix checkpatch warning may triggered...
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20220718130955.11899-4-liweiwei@iscas.ac.cn>
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2022-09-07 Weiwei Litarget/riscv: H extension depends on I extension
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20220718130955.11899-3-liweiwei@iscas.ac.cn>
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2022-09-07 Weiwei Litarget/riscv: Add check for supported privilege mode...
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20220718130955.11899-2-liweiwei@iscas.ac.cn>
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2022-09-07 Weiwei Litarget/riscv: move zmmul out of the experimental properties
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20220710101546.3907-1-liweiwei@iscas.ac.cn>
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2022-06-09 Weiwei Litarget/riscv: add support for zmmul extension v0.1
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20220531030732.3850-1-liweiwei@iscas.ac.cn>
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2022-05-24 Weiwei Litarget/riscv: check 'I' and 'E' after checking 'G'...
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20220518012611.6772-1-liweiwei@iscas.ac.cn>
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2022-04-29 Weiwei Litarget/riscv: add scalar crypto related extenstion...
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20220426095204.24142-1-liweiwei@iscas.ac.cn>
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2022-04-29 Weiwei Litarget/riscv: rvk: expose zbk* and zk* properties
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20220423023510.30794-15-liweiwei@iscas.ac.cn>
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2022-04-29 Weiwei Lidisas/riscv.c: rvk: add disas support for Zbk* and...
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20220423023510.30794-14-liweiwei@iscas.ac.cn>
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2022-04-29 Weiwei Litarget/riscv: rvk: add CSR support for Zkr
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20220423023510.30794-13-liweiwei@iscas.ac.cn>
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2022-04-29 Weiwei Litarget/riscv: rvk: add support for zksed/zksh extension
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20220423023510.30794-12-liweiwei@iscas.ac.cn>
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2022-04-29 Weiwei Litarget/riscv: rvk: add support for sha512 related instructio...
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20220423023510.30794-11-liweiwei@iscas.ac.cn>
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2022-04-29 Weiwei Litarget/riscv: rvk: add support for sha512 related instructio...
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20220423023510.30794-10-liweiwei@iscas.ac.cn>
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2022-04-29 Weiwei Litarget/riscv: rvk: add support for sha256 related instructio...
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20220423023510.30794-9-liweiwei@iscas.ac.cn>
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2022-04-29 Weiwei Litarget/riscv: rvk: add support for zkne/zknd extension...
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20220423023510.30794-8-liweiwei@iscas.ac.cn>
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2022-04-29 Weiwei Litarget/riscv: rvk: add support for zknd/zkne extension...
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20220423023510.30794-7-liweiwei@iscas.ac.cn>
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2022-04-29 Weiwei Licrypto: move sm4_sbox from target/arm
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20220423023510.30794-6-liweiwei@iscas.ac.cn>
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2022-04-29 Weiwei Litarget/riscv: rvk: add support for zbkx extension
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20220423023510.30794-5-liweiwei@iscas.ac.cn>
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2022-04-29 Weiwei Litarget/riscv: rvk: add support for zbkc extension
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20220423023510.30794-4-liweiwei@iscas.ac.cn>
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2022-04-29 Weiwei Litarget/riscv: rvk: add support for zbkb extension
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20220423023510.30794-3-liweiwei@iscas.ac.cn>
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2022-04-29 Weiwei Litarget/riscv: rvk: add cfg properties for zbk* and zk*
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20220423023510.30794-2-liweiwei@iscas.ac.cn>
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2022-04-22 Weiwei Litarget/riscv: fix start byte for vmv<nf>r.v when vstart...
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20220330021316.18223-1-liweiwei@iscas.ac.cn>
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2022-04-22 Weiwei Litarget/riscv: optimize helper for vmv<nr>r.v
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20220325085902.29500-2-liweiwei@iscas.ac.cn>
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2022-04-22 Weiwei Litarget/riscv: optimize condition assign for scale < 0
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20220325085902.29500-1-liweiwei@iscas.ac.cn>
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2022-03-03 Weiwei Litarget/riscv: expose zfinx, zdinx, zhinx{min} properties
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20220211043920.28981-7-liweiwei@iscas.ac.cn>
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2022-03-03 Weiwei Litarget/riscv: add support for zhinx/zhinxmin
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20220211043920.28981-6-liweiwei@iscas.ac.cn>
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2022-03-03 Weiwei Litarget/riscv: add support for zdinx
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20220211043920.28981-5-liweiwei@iscas.ac.cn>
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2022-03-03 Weiwei Litarget/riscv: add support for zfinx
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20220211043920.28981-4-liweiwei@iscas.ac.cn>
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2022-03-03 Weiwei Litarget/riscv: hardwire mstatus.FS to zero when enable...
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20220211043920.28981-3-liweiwei@iscas.ac.cn>
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2022-03-03 Weiwei Litarget/riscv: add cfg properties for zfinx, zdinx and...
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20220211043920.28981-2-liweiwei@iscas.ac.cn>
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2022-02-16 Weiwei Litarget/riscv: add support for svpbmt extension
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20220204022658.18097-6-liweiwei@iscas.ac.cn>
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2022-02-16 Weiwei Litarget/riscv: add support for svinval extension
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20220204022658.18097-5-liweiwei@iscas.ac.cn>
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2022-02-16 Weiwei Litarget/riscv: add support for svnapot extension
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20220204022658.18097-4-liweiwei@iscas.ac.cn>
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2022-02-16 Weiwei Litarget/riscv: add PTE_A/PTE_D/PTE_U bits check for...
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20220204022658.18097-3-liweiwei@iscas.ac.cn>
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