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2017-09-11 | Rodrigo Vivi | drm/i915/psr: Re-org Activate after enable Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...msgid/20170907230041.22978-9-rodrigo.vivi@intel.com |
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2017-09-11 | Rodrigo Vivi | drm/i915/psr: Move hsw_enable_source after enabling... Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...msgid/20170907230041.22978-8-rodrigo.vivi@intel.com |
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2017-09-11 | Rodrigo Vivi | drm/i915/psr: Re-create a hsw_psr_enable_source. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...msgid/20170907230041.22978-7-rodrigo.vivi@intel.com |
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2017-09-11 | Rodrigo Vivi | drm/i915/psr: Unify VSC setup functions. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...msgid/20170907230041.22978-6-rodrigo.vivi@intel.com |
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2017-09-11 | Rodrigo Vivi | drm/i915/psr: Add activate vfunc. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...msgid/20170907230041.22978-5-rodrigo.vivi@intel.com |
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2017-09-11 | Rodrigo Vivi | drm/i915/psr: hsw_psr_activate. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...msgid/20170907230041.22978-4-rodrigo.vivi@intel.com |
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2017-09-11 | Rodrigo Vivi | drm/i915/psr: vfunc for disabling source. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...msgid/20170907230041.22978-3-rodrigo.vivi@intel.com |
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2017-09-11 | Rodrigo Vivi | drm/i915/psr: Avoid any PSR stuff on platforms without... Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...msgid/20170907230041.22978-2-rodrigo.vivi@intel.com |
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2017-09-06 | Rodrigo Vivi | drm/i915/cnl: WaThrottleEUPerfToAvoidTDBackPressure... Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...msgid/20170906220325.24524-1-rodrigo.vivi@intel.com |
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2017-09-06 | Rodrigo Vivi | drm/i915: Display WA #1133 WaFbcSkipSegments:cnl, glk Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...msgid/20170905193013.31710-1-rodrigo.vivi@intel.com |
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2017-09-06 | Nanley Chery | drm/i915/cnl: Allow the reg_read ioctl to read the... Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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2017-09-05 | Rodrigo Vivi | drm/i915/cnp: Wa 1181: Fix Backlight issue Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...patch/msgid/20170831045223.3960-1-rodrigo.vivi@intel.com |
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2017-09-02 | Zhi Wang | drm/i915: Fix the missing PPAT cache attributes on CNL Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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2017-08-31 | Rodrigo Vivi | drm/i915/cnl: Fix DP max voltage Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...msgid/20170831145356.15932-1-rodrigo.vivi@intel.com |
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2017-08-31 | Rodrigo Vivi | drm/i915/cnl: Fix DDI hdmi level selection. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...msgid/20170829232230.23051-7-rodrigo.vivi@intel.com |
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2017-08-31 | Rodrigo Vivi | drm/i915/cnl: Move ddi buf trans related functions up. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...msgid/20170829232230.23051-6-rodrigo.vivi@intel.com |
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2017-08-31 | Rodrigo Vivi | drm/i915/cnl: Move voltage check into ddi buf trans... Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...msgid/20170829232230.23051-5-rodrigo.vivi@intel.com |
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2017-08-31 | Rodrigo Vivi | drm/i915: Enable voltage swing before enabling DDI_BUF_CTL. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...msgid/20170829232230.23051-4-rodrigo.vivi@intel.com |
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2017-08-31 | Rodrigo Vivi | drm/i915: Align vswing sequences with old ddi buffer... Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...msgid/20170829232230.23051-3-rodrigo.vivi@intel.com |
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2017-08-31 | Rodrigo Vivi | drm/i915: decouple gen9 and gen10 dp signal levels. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...msgid/20170829232230.23051-2-rodrigo.vivi@intel.com |
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2017-08-31 | Rodrigo Vivi | drm/i915: Introduce intel_ddi_dp_level. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...msgid/20170829232230.23051-1-rodrigo.vivi@intel.com |
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2017-08-31 | Rodrigo Vivi | drm/i915/cnl: Avoid ioremap_wc on Cannonlake as well. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...msgid/20170829230907.21363-1-rodrigo.vivi@intel.com |
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2017-08-31 | Rodrigo Vivi | drm/i915/cnl: WaDisableI2mCycleOnWRPort Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...msgid/20170829230751.21047-1-rodrigo.vivi@intel.com |
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2017-08-31 | Rodrigo Vivi | drm/i915/cnl: WA FtrEnableFastAnisoL1BankingFix Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...msgid/20170829230723.20898-1-rodrigo.vivi@intel.com |
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2017-08-31 | Rodrigo Vivi | drm/i915: Stop using long platform names on clock gating... Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...msgid/20170829052026.15038-1-rodrigo.vivi@intel.com |
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2017-08-24 | Oscar Mateo | drm/i915: Make some RPS functions static Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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2017-08-23 | Rodrigo Vivi | drm/i915/cnl: WaForceContextSaveRestoreNonCoherent Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...msgid/20170823203504.10012-1-rodrigo.vivi@intel.com |
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2017-08-23 | Oscar Mateo | drm/i915/cnl: WaPushConstantDereferenceHoldDisable Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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2017-08-22 | Rodrigo Vivi | drm/i915/cfl: Coffee Lake works on Kaby Lake PCH. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...patch/msgid/20170821235056.9015-1-rodrigo.vivi@intel.com |
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2017-08-22 | Paulo Zanoni | drm/i915/cnl: extract cnl_set_procmon_ref_values Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...msgid/20170822000356.17330-2-rodrigo.vivi@intel.com |
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2017-08-22 | Paulo Zanoni | drm/i915/cnl: simplify cnl_procmon_values handling Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...msgid/20170822000356.17330-1-rodrigo.vivi@intel.com |
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2017-08-18 | Rodrigo Vivi | drm/i915/cnl: Apply large line width optimization Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...patch/msgid/20170815231651.975-4-rodrigo.vivi@intel.com |
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2017-08-18 | Rodrigo Vivi | drm/i915/cnl: WaDisableEnhancedSBEVertexCaching Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...patch/msgid/20170815231651.975-3-rodrigo.vivi@intel.com |
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2017-08-18 | Rodrigo Vivi | drm/i915/cnl: Add WaDisableReplayBufferBankArbitrationOptimi... Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...patch/msgid/20170815231651.975-2-rodrigo.vivi@intel.com |
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2017-08-18 | Rodrigo Vivi | drm/i915/cnl: Introduce initial Cannonlake Workarounds. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...patch/msgid/20170815231651.975-1-rodrigo.vivi@intel.com |
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2017-08-16 | Rodrigo Vivi | drm/i915/cnl: Reuse skl_wm_get_hw_state on Cannonlake. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...msgid/20170809205248.11917-6-rodrigo.vivi@intel.com |
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2017-08-16 | Paulo Zanoni | drm/i915/gen10: implement gen 10 watermarks calculations Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...msgid/20170811233825.32083-1-rodrigo.vivi@intel.com |
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2017-08-16 | Rodrigo Vivi | drm/i915/cnl: Fix LSPCON support. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...msgid/20170816030403.11368-1-rodrigo.vivi@intel.com |
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2017-08-15 | Rodrigo Vivi | drm/i915/cnl: Setup PAT Index. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...patch/msgid/20170815232539.3562-1-rodrigo.vivi@intel.com |
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2017-08-15 | Jim Bride | drm/i915/edp: Allow alternate fixed mode for eDP if... Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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2017-08-11 | Rodrigo Vivi | drm/i915: Introduce intel_hpd_pin function. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...msgid/20170811182650.14327-2-rodrigo.vivi@intel.com |
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2017-08-11 | Rodrigo Vivi | drm/i915: Simplify hpd pin to port Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...msgid/20170811182650.14327-1-rodrigo.vivi@intel.com |
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2017-08-11 | Rodrigo Vivi | drm/i915/cnl: Dump the right pll registers when dumping... Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...msgid/20170810224525.18278-1-rodrigo.vivi@intel.com |
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2017-08-11 | Rodrigo Vivi | drm/i915/cnl: Add allowed DP rates for Cannonlake. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...msgid/20170810224008.15571-1-rodrigo.vivi@intel.com |
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2017-08-11 | Matthias Kaehlcke | drm/i915: Return correct EDP voltage swing table for... Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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2017-08-10 | Rodrigo Vivi | drm/i915/cnl: Add slice and subslice information to... Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...msgid/20170809200702.11236-1-rodrigo.vivi@intel.com |
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2017-08-10 | Paulo Zanoni | drm/i915/gen10: fix WM latency printing Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...msgid/20170809205248.11917-4-rodrigo.vivi@intel.com |
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2017-08-10 | Paulo Zanoni | drm/i915/gen10: fix the gen 10 SAGV block time Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...msgid/20170809205248.11917-3-rodrigo.vivi@intel.com |
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2017-08-10 | Rodrigo Vivi | drm/i915/cnl: Enable SAGV for Cannonlake. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...msgid/20170809205248.11917-2-rodrigo.vivi@intel.com |
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2017-08-10 | Paulo Zanoni | drm/i915/gen10+: use the SKL code for reading WM latencies Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...msgid/20170809205248.11917-1-rodrigo.vivi@intel.com |
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2017-08-10 | Rodrigo Vivi | drm/i915: Avoid null dereference if mst_port is unset. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...msgid/20170810145043.24047-1-rodrigo.vivi@intel.com |
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2017-08-09 | Jim Bride | drm/i915/psr: Preserve SRD_CTL bit 29 on PSR init Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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2017-08-08 | Rodrigo Vivi | drm/i915/cnl: Removing missing DDI_E bits from CNL. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...msgid/20170808193237.17410-1-rodrigo.vivi@intel.com |
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2017-08-03 | Praveen Paneri | drm/i915: enable WaDisableDopClkGating for skl Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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2017-08-03 | Rodrigo Vivi | drm/i915: Fix PCH names for KBP and CNP. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...patch/msgid/20170731185220.758-1-rodrigo.vivi@intel.com |
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2017-07-11 | Rodrigo Vivi | drm/i915/cnl: Add missing type case. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...msgid/20170710205852.28352-1-rodrigo.vivi@intel.com |
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2017-07-10 | Rodrigo Vivi | drm/i915/cnl: Add max allowed Cannonlake DC. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1499373908-26761-1-git-send-email-rodrigo.vivi@intel.com |
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2017-07-07 | Rodrigo Vivi | drm/i915/cnl: Get DDI clock based on PLLs. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1499374321-31152-1-git-send-email-rodrigo.vivi@intel.com |
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2017-07-07 | Rodrigo Vivi | drm/i915/cnl: Inherit RPS stuff from previous platforms. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1499373673-25066-1-git-send-email-rodrigo.vivi@intel.com |
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2017-07-07 | Rodrigo Vivi | drm/i915/cnl: Gen10 render context size. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1499375184-5725-1-git-send-email-rodrigo.vivi@intel.com |
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2017-07-07 | Rodrigo Vivi | drm/i915/cnl: Don't trust VBT's alternate pin for port... Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1499375295-6454-1-git-send-email-rodrigo.vivi@intel.com |
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2017-07-06 | Rodrigo Vivi | drm/i915/cnl: Cannonlake color init. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1499374873-2454-1-git-send-email-rodrigo.vivi@intel.com |
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2017-07-06 | Rodrigo Vivi | drm/i915/cnl: Add force wake for gen10+. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1499302831-17773-1-git-send-email-rodrigo.vivi@intel.com |
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2017-07-06 | Paulo Zanoni | x86/gpu: CNL uses the same GMS values as SKL Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1499302845-17856-1-git-send-email-rodrigo.vivi@intel.com |
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2017-06-30 | Navare, Manasi D | drm/i915/cnl: Fix the CURSOR_COEFF_MASK used in DDI... Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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2017-06-29 | Rodrigo Vivi | drm/i915/cfl: Fix Workarounds. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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2017-06-19 | Rodrigo Vivi | drm/i915/cnl: Fix RMW on ddi vswing sequence. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1497897572-22520-1-git-send-email-rodrigo.vivi@intel.com |
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2017-06-16 | Rodrigo Vivi | drm/i915/cfl: Introduce Coffee Lake workarounds. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1497653398-15722-1-git-send-email-rodrigo.vivi@intel.com |
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2017-06-15 | Rodrigo Vivi | Revert "drm/i915/skl: New ddb allocation algorithm" Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1497376350-3400-1-git-send-email-rodrigo.vivi@intel.com |
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2017-06-12 | Rodrigo Vivi | drm/i915/cfl: Basic DDI plumbing for Coffee Lake. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1497045770-21302-1-git-send-email-rodrigo.vivi@intel.com |
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2017-06-12 | Kahola, Mika | drm/i915/cnl: Enable wrpll computation for CNL Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1497047175-27250-18-git-send-email-rodrigo.vivi@intel.com |
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2017-06-12 | Rodrigo Vivi | drm/i915/cnl: LSPCON support is gen9+ Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1497047175-27250-17-git-send-email-rodrigo.vivi@intel.com |
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2017-06-12 | Rodrigo Vivi | drm/i915/cnl: Enable fifo underrun for Cannonlake. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1497047175-27250-16-git-send-email-rodrigo.vivi@intel.com |
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2017-06-12 | Rodrigo Vivi | drm/i915/cnl: Fix Cannonlake scaler mode programing. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1497047175-27250-15-git-send-email-rodrigo.vivi@intel.com |
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2017-06-12 | Rodrigo Vivi | drm/i915: Use HAS_CSR instead of gen number on DMC... Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1497047175-27250-14-git-send-email-rodrigo.vivi@intel.com |
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2017-06-12 | Anusha Srivatsa | drm/i915/DMC/CNL: Load DMC on CNL Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1497047175-27250-13-git-send-email-rodrigo.vivi@intel.com |
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2017-06-12 | Clint Taylor | drm/i915/cnl: Enable loadgen_select bit for vswing... Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1497047175-27250-12-git-send-email-rodrigo.vivi@intel.com |
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2017-06-12 | Rodrigo Vivi | drm/i915/cnl: Implement voltage swing sequence. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1497047175-27250-11-git-send-email-rodrigo.vivi@intel.com |
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2017-06-12 | Rodrigo Vivi | drm/i915/cnl: Add DDI Buffer translation tables for... Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1497047175-27250-10-git-send-email-rodrigo.vivi@intel.com |
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2017-06-12 | Rodrigo Vivi | drm/i915/cnl: Add registers related to voltage swing... Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1497047175-27250-9-git-send-email-rodrigo.vivi@intel.com |
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2017-06-12 | Rodrigo Vivi | drm/i915: Add MMIO helper for 6 ports with different... Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1497047175-27250-8-git-send-email-rodrigo.vivi@intel.com Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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2017-06-12 | Rodrigo Vivi | drm/i915/cnl: Initialize PLLs Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1497047175-27250-7-git-send-email-rodrigo.vivi@intel.com |
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2017-06-12 | Kahola, Mika | drm/i915: Configure DPLL's for Cannonlake Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1497047175-27250-6-git-send-email-rodrigo.vivi@intel.com |
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2017-06-12 | Rodrigo Vivi | drm/i915/cnl: DDI - PLL mapping Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1497047175-27250-5-git-send-email-rodrigo.vivi@intel.com |
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2017-06-12 | Rodrigo Vivi | drm/i915/cnl: Allow dynamic cdclk changes on CNL Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1497047175-27250-4-git-send-email-rodrigo.vivi@intel.com |
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2017-06-12 | Ville Syrjälä | drm/i915/cnl: Implement CNL display init/unit sequence Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1497047175-27250-3-git-send-email-rodrigo.vivi@intel.com |
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2017-06-12 | Ville Syrjälä | drm/i915/cnl: Implement .set_cdclk() for CNL Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1497047175-27250-2-git-send-email-rodrigo.vivi@intel.com |
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2017-06-12 | Ville Syrjälä | drm/i915/cnl: Implement .get_display_clock_speed()... Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1497047175-27250-1-git-send-email-rodrigo.vivi@intel.com |
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2017-06-09 | Rodrigo Vivi | drm/i915/cfl: Coffee Lake reuses Kabylake DMC. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1497038550-30910-1-git-send-email-rodrigo.vivi@intel.com |
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2017-06-09 | Anusha Srivatsa | drm/i915/huc: Load HuC on Coffee Lake Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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2017-06-09 | Anusha Srivatsa | drm/i915/guc: Load GuC on Coffee Lake Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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2017-06-09 | Anusha Srivatsa | drm/i915/cfl: Add Coffee Lake PCI IDs for U Sku. Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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2017-06-09 | Anusha Srivatsa | drm/i915/cfl: Add Coffee Lake PCI IDs for H Sku. Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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2017-06-09 | Anusha Srivatsa | drm/i915/cfl: Add Coffee Lake PCI IDs for S Skus. Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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2017-06-08 | Rodrigo Vivi | drm/i915/cfl: Introduce Display workarounds for Coffee... Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1496937000-8450-3-git-send-email-rodrigo.vivi@intel.com |
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2017-06-08 | Rodrigo Vivi | drm/i915/cfl: Coffee Lake uses CNP PCH. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1496937000-8450-2-git-send-email-rodrigo.vivi@intel.com |
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2017-06-08 | Rodrigo Vivi | drm/i915/cfl: Introduce Coffee Lake platform definition. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1496937000-8450-1-git-send-email-rodrigo.vivi@intel.com |
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2017-06-07 | Rodrigo Vivi | drm/i915: Unify GT* and GT3 definitions Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1496765166-7068-1-git-send-email-rodrigo.vivi@intel.com |
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2017-06-07 | Rodrigo Vivi | drm/i915: Remove unnecessary PORT3 definition. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1496700722-13755-1-git-send-email-rodrigo.vivi@intel.com |
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2017-06-07 | Rodrigo Vivi | drm/i915/cnl: Also need power well sanitize. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1496781040-20888-11-git-send-email-rodrigo.vivi@intel.com |
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