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drm/i915: Enable voltage swing before enabling DDI_BUF_CTL.
2017-08-31 Rodrigo Vividrm/i915: Enable voltage swing before enabling DDI_BUF_CTL.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-08-31 Rodrigo Vividrm/i915: Align vswing sequences with old ddi buffer...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-08-31 Rodrigo Vividrm/i915: decouple gen9 and gen10 dp signal levels.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-08-31 Rodrigo Vividrm/i915: Introduce intel_ddi_dp_level.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-08-31 Rodrigo Vividrm/i915/cnl: Avoid ioremap_wc on Cannonlake as well.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-08-31 Rodrigo Vividrm/i915/cnl: WaDisableI2mCycleOnWRPort
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-08-31 Rodrigo Vividrm/i915/cnl: WA FtrEnableFastAnisoL1BankingFix
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-08-31 Rodrigo Vividrm/i915: Stop using long platform names on clock gating...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-08-23 Rodrigo Vividrm/i915/cnl: WaForceContextSaveRestoreNonCoherent
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-08-22 Rodrigo Vividrm/i915/cfl: Coffee Lake works on Kaby Lake PCH.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-08-18 Rodrigo Vividrm/i915/cnl: Apply large line width optimization
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-08-18 Rodrigo Vividrm/i915/cnl: WaDisableEnhancedSBEVertexCaching
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-08-18 Rodrigo Vividrm/i915/cnl: Add WaDisableReplayBufferBankArbitrationOptimi...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-08-18 Rodrigo Vividrm/i915/cnl: Introduce initial Cannonlake Workarounds.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-08-16 Rodrigo Vividrm/i915/cnl: Reuse skl_wm_get_hw_state on Cannonlake.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-08-16 Rodrigo Vividrm/i915/cnl: Fix LSPCON support.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-08-15 Rodrigo Vividrm/i915/cnl: Setup PAT Index.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-08-11 Rodrigo Vividrm/i915: Introduce intel_hpd_pin function.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-08-11 Rodrigo Vividrm/i915: Simplify hpd pin to port
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-08-11 Rodrigo Vividrm/i915/cnl: Dump the right pll registers when dumping...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-08-11 Rodrigo Vividrm/i915/cnl: Add allowed DP rates for Cannonlake.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-08-10 Rodrigo Vividrm/i915/cnl: Add slice and subslice information to...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-08-10 Rodrigo Vividrm/i915/cnl: Enable SAGV for Cannonlake.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-08-10 Rodrigo Vividrm/i915: Avoid null dereference if mst_port is unset.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-08-08 Rodrigo Vividrm/i915/cnl: Removing missing DDI_E bits from CNL.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-08-03 Rodrigo Vividrm/i915: Fix PCH names for KBP and CNP.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-07-11 Rodrigo Vividrm/i915/cnl: Add missing type case.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-07-10 Rodrigo Vividrm/i915/cnl: Add max allowed Cannonlake DC.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-07-07 Rodrigo Vividrm/i915/cnl: Get DDI clock based on PLLs.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-07-07 Rodrigo Vividrm/i915/cnl: Inherit RPS stuff from previous platforms.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-07-07 Rodrigo Vividrm/i915/cnl: Gen10 render context size.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-07-07 Rodrigo Vividrm/i915/cnl: Don't trust VBT's alternate pin for port...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-07-06 Rodrigo Vividrm/i915/cnl: Cannonlake color init.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-07-06 Rodrigo Vividrm/i915/cnl: Add force wake for gen10+.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-07-03 Rodrigo Vividrm/i915/cfl: Fix Workarounds.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-06-29 Rodrigo Vividrm/i915/cfl: Fix Workarounds.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-06-26 Rodrigo Vividrm/i915/cnl: Fix RMW on ddi vswing sequence.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-06-19 Rodrigo Vividrm/i915/cnl: Fix RMW on ddi vswing sequence.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-06-16 Rodrigo Vividrm/i915/cfl: Introduce Coffee Lake workarounds.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-06-15 Rodrigo ViviRevert "drm/i915/skl: New ddb allocation algorithm"
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-06-12 Rodrigo Vividrm/i915/cfl: Basic DDI plumbing for Coffee Lake.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-06-12 Rodrigo Vividrm/i915/cnl: LSPCON support is gen9+
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-06-12 Rodrigo Vividrm/i915/cnl: Enable fifo underrun for Cannonlake.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-06-12 Rodrigo Vividrm/i915/cnl: Fix Cannonlake scaler mode programing.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-06-12 Rodrigo Vividrm/i915: Use HAS_CSR instead of gen number on DMC...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-06-12 Rodrigo Vividrm/i915/cnl: Implement voltage swing sequence.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-06-12 Rodrigo Vividrm/i915/cnl: Add DDI Buffer translation tables for...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-06-12 Rodrigo Vividrm/i915/cnl: Add registers related to voltage swing...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-06-12 Rodrigo Vividrm/i915: Add MMIO helper for 6 ports with different...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-06-12 Rodrigo Vividrm/i915/cnl: Initialize PLLs
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-06-12 Rodrigo Vividrm/i915/cnl: DDI - PLL mapping
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-06-12 Rodrigo Vividrm/i915/cnl: Allow dynamic cdclk changes on CNL
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-06-09 Rodrigo Vividrm/i915/cfl: Coffee Lake reuses Kabylake DMC.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-06-08 Rodrigo Vividrm/i915/cfl: Introduce Display workarounds for Coffee...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-06-08 Rodrigo Vividrm/i915/cfl: Coffee Lake uses CNP PCH.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-06-08 Rodrigo Vividrm/i915/cfl: Introduce Coffee Lake platform definition.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-06-07 Rodrigo Vividrm/i915: Unify GT* and GT3 definitions
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-06-07 Rodrigo Vividrm/i915: Remove unnecessary PORT3 definition.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-06-07 Rodrigo Vividrm/i915/cnl: Also need power well sanitize.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-06-07 Rodrigo Vividrm/i915/cnl: Cannonlake has same MOCS table than Skylake.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-06-07 Rodrigo Vividrm/i915/cnl: Configure EU slice power gating.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-06-07 Rodrigo Vividrm/i915/cnl: Add Cannonlake PCI IDs for Y-skus.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-06-07 Rodrigo Vividrm/i915/cnl: Add Cannonlake PCI IDs for U-skus.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-06-07 Rodrigo Vividrm/i915/cnl: Cannonlake uses CNP PCH.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-06-07 Rodrigo Vividrm/i915/cnl: Introduce Cannonlake platform defition.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-06-02 Rodrigo Vividrm/i915/cnp: Panel Power sequence changes for CNP...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-06-02 Rodrigo Vividrm/i915/cnp: add CNP gmbus support
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-06-02 Rodrigo Vividrm/i915/cnp: Backlight support for CNP.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-06-02 Rodrigo Vividrm/i915/cnp: Get/set proper Raw clock frequency on...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-06-02 Rodrigo Vividrm/i915/cnp: Introduce Cannonpoint PCH.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-02-20 Rodrigo Vividrm/i915: DMC 1.03 for Geminilake
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-01-24 Rodrigo Vividrm/i915: Introduce IS_GEN9_BC for Skylake and Kabylake.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-01-24 Rodrigo Vividrm/i915/kbl: Apply WaIncreaseDefaultTLBEntries on...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-01-10 Rodrigo Vividrm/i915/glk: Add missing bits to allow runtime pm...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-01-03 Rodrigo Vividrm/i915: Update SKL SRV GT4 pci ids reference.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2016-12-20 Rodrigo Vividrm/i915: Remove useless VLV_FEATURE Macro.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2016-12-19 Rodrigo Vividrm/i915: Simplify gem stolen initialization.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2016-12-19 Rodrigo Vividrm/i915: Rename get stolen functions for LP platforms...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2016-12-19 Rodrigo Vividrm/i915: Expand is_lp backwards to gen8_lp and gen7_lp.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2016-12-02 Rodrigo Vividrm/i915: Only poll DW3_A when init DDI PHY for ports...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2016-12-01 Rodrigo Vividrm/i915: Create a common GEN9_LP_FEATURE.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2016-10-20 Rodrigo Vividrm/i915: KBL - Recommended buffer translation programming...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2016-10-20 Rodrigo Vividrm/i915: Move down skl/kbl ddi iboost and n_edp_entires...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2016-09-14 Rodrigo ViviRevert "drm/i915/psr: Make idle_frames sensible again"
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2016-09-13 Rodrigo ViviRevert "drm/i915/psr: Make idle_frames sensible again"
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2016-08-08 Rodrigo Vividrm: Avoid printing negative values for unsigned variables.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2016-08-05 Rodrigo Vividrm/i915: Use drm official vblank_no_hw_counter callback.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2016-08-05 Rodrigo Vividrm/i915: Fix copy_to_user usage for pipe_crc
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2016-07-25 Rodrigo Vividrm/i915/guc: Revert "drm/i915/guc: enable GuC loading...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2016-07-19 Rodrigo Vividrm/i915/guc: Revert "drm/i915/guc: enable GuC loading...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2016-07-18 Rodrigo Vividrm/i915/kbl: Introduce the first official DMC for...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2016-07-15 Rodrigo Vividrm/i915: Introduce Kabypoint PCH for Kabylake H/DT.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2016-07-07 Rodrigo Vividrm/i915: Introduce Kabypoint PCH for Kabylake H/DT.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2016-06-29 Rodrigo Vividrm/i915: Removing PCI IDs that are no longer listed...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2016-06-29 Rodrigo Vividrm/i915: Add more Kabylake PCI IDs.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2016-06-28 Rodrigo Vividrm/i915: Removing PCI IDs that are no longer listed...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2016-06-28 Rodrigo Vividrm/i915: Add more Kabylake PCI IDs.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2016-05-05 Rodrigo Vividrm/i915/kbl: Introduce the first official DMC for...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2016-03-30 Rodrigo Vividrm/i915/kbl: Remove preliminary_hw_support protection...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2016-02-17 Rodrigo Vividrm/i915: Enable PSR by default on Haswell and Broadwell.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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