projects / mirror_qemu.git / search
| 2023-02-06 | Philipp Tomsich | target/riscv: update disas.c for xnor/orn/andn and... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-20 | Daniel Henrique... | hw/riscv/virt.c: move create_fw_cfg() back to virt_machine_i... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-20 | Richard Henderson | target/riscv: Remove helper_set_rod_rounding_mode Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-20 | Richard Henderson | target/riscv: Introduce helper_set_rounding_mode_chkfrm Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-20 | Richard Henderson | tcg/riscv: Use tcg_pcrel_diff in tcg_out_ldst Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-20 | Andrew Bresticker | target/riscv: Trap on writes to stimecmp from VS when... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-20 | Andrew Bresticker | target/riscv: Fix up masking of vsip/vsie accesses Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-20 | Daniel Henrique... | hw/riscv: use ms->fdt in riscv_socket_fdt_write_distance_mat... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-20 | Daniel Henrique... | hw/riscv: use MachineState::fdt in riscv_socket_fdt_write_id() Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-20 | Daniel Henrique... | hw/riscv/virt.c: remove 'is_32_bit' param from create_fdt_so... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-20 | Daniel Henrique... | hw/riscv/sifive_u.c: simplify create_fdt() Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-20 | Daniel Henrique... | hw/riscv/virt.c: simplify create_fdt() Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-20 | Daniel Henrique... | hw/riscv/spike.c: simplify create_fdt() Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-20 | Bin Meng | target/riscv: Use TARGET_FMT_lx for env->mhartid Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-20 | Daniel Henrique... | target/riscv/cpu.c: do not skip misa logic in riscv_cpu_real... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-20 | Daniel Henrique... | target/riscv/cpu: set cpu->cfg in register_cpu_props() Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-20 | Daniel Henrique... | hw/riscv/boot.c: use MachineState in riscv_load_kernel() Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-20 | Daniel Henrique... | hw/riscv/boot.c: use MachineState in riscv_load_initrd() Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-20 | Daniel Henrique... | hw/riscv: write bootargs 'chosen' FDT after riscv_load_kernel() Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-20 | Daniel Henrique... | hw/riscv: write initrd 'chosen' FDT inside riscv_load_initrd() Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-20 | Daniel Henrique... | hw/riscv/spike.c: load initrd right after riscv_load_kernel() Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-20 | Daniel Henrique... | hw/riscv/boot.c: exit early if filename is NULL in... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-20 | Daniel Henrique... | hw/riscv/sifive_u: use 'fdt' from MachineState Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-20 | Daniel Henrique... | hw/riscv/spike: use 'fdt' from MachineState Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-20 | Daniel Henrique... | tests/avocado: add RISC-V OpenSBI boot test Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-20 | Dongxue Zhang | target/riscv/cpu.c: Fix elen check Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-20 | Bin Meng | hw/riscv: spike: Decouple create_fdt() dependency to... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-20 | Bin Meng | hw/riscv/boot.c: Introduce riscv_find_firmware() Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-20 | Daniel Henrique... | hw/riscv/boot.c: introduce riscv_default_firmware_name() Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-20 | Daniel Henrique... | hw/riscv/boot.c: make riscv_find_firmware() static Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-20 | Bin Meng | hw/riscv: spike: Remove the out-of-date comments Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-20 | Bin Meng | hw/char: riscv_htif: Support console output via proxy... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-20 | Bin Meng | hw/char: riscv_htif: Remove forward declarations for... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-20 | Bin Meng | hw/char: riscv_htif: Move registers from CPUArchState... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-20 | Bin Meng | hw/char: riscv_htif: Use conventional 's' for HTIFState Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-20 | Bin Meng | hw/char: riscv_htif: Drop useless assignment of memory... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-20 | Bin Meng | hw/char: riscv_htif: Drop {to, from}host_size in HTIFState Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-20 | Bin Meng | hw/char: riscv_htif: Avoid using magic numbers Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-06 | Bin Meng | hw/intc: sifive_plic: Fix the pending register range... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-06 | Bin Meng | hw/riscv: opentitan: Drop "hartid-base" and "priority... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-06 | Bin Meng | hw/intc: sifive_plic: Change "priority-base" to start... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-06 | Bin Meng | hw/riscv: virt: Fix the value of "riscv, ndev" in the dtb Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-06 | Bin Meng | hw/riscv: sifive_u: Avoid using magic number for "riscv... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-06 | Bin Meng | hw/riscv: sifive_e: Fix the number of interrupt sources... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-06 | Bin Meng | hw/riscv: microchip_pfsoc: Fix the number of interrupt... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-06 | Bin Meng | hw/intc: sifive_plic: Update "num-sources" property... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-06 | Bin Meng | hw/intc: sifive_plic: Use error_setg() to propagate... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-06 | Bin Meng | hw/intc: sifive_plic: Improve robustness of the PLIC... Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-06 | Bin Meng | hw/intc: sifive_plic: Drop PLICMode_H Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-06 | Bin Meng | hw/riscv: spike: Remove misleading comments Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-06 | Bin Meng | hw/riscv: Sort machines Kconfig options in alphabetical... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-06 | Bin Meng | hw/riscv: Fix opentitan dependency to SIFIVE_PLIC Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-06 | Bin Meng | hw/intc: Select MSI_NONBROKEN in RISC-V AIA interrupt... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-06 | Bin Meng | hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-06 | Christoph Muellner | RISC-V: Add Zawrs ISA extension support Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-06 | Bin Meng | target/riscv: Clear mstatus.MPRV when leaving M-mode... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-06 | Bin Meng | target/riscv: Simplify helper_sret() a little bit Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-06 | Richard Henderson | target/riscv: Set pc_succ_insn for !rvc illegal insn Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-06 | Bin Meng | target/riscv: Fix mret exception cause when no pmp... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-06 | Jim Shu | hw/intc: sifive_plic: fix out-of-bound access of source_prio... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-06 | Conor Dooley | hw/{misc, riscv}: pfsoc: add system controller as unimplemented Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-06 | Conor Dooley | hw/riscv: pfsoc: add missing FICs as unimplemented Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-06 | Conor Dooley | hw/misc: pfsoc: add fabric clocks to ioscb Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-06 | Bin Meng | target/riscv: Add some comments for sstatus CSR in... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-06 | Jim Shu | target/riscv: support cache-related PMU events in virtual... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-06 | Atish Patra | hw/riscv: virt: Remove the redundant ipi-id property Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-06 | Anup Patel | target/riscv: Typo fix in sstc() predicate Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-06 | Frédéric Pétrot | hw/intc: sifive_plic: Renumber the S irqs for numa... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-06 | LIU Zhiwei | target/riscv: Add itrigger_enabled field to CPURISCVState Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-06 | LIU Zhiwei | target/riscv: Enable native debug itrigger Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-06 | LIU Zhiwei | target/riscv: Add itrigger support when icount is enabled Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-06 | LIU Zhiwei | target/riscv: Add itrigger support when icount is not... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-06 | Mayuresh Chitale | target/riscv: generate virtual instruction exception Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-06 | Mayuresh Chitale | target/riscv: smstateen check for h/s/envcfg Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-06 | Mayuresh Chitale | target/riscv: Add smstateen support Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-06 | Wilfred Mallawa | hw/riscv/opentitan: add aon_timer base unimpl Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-06 | Wilfred Mallawa | hw/riscv/opentitan: bump opentitan Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-06 | Richard Henderson | tcg/riscv: Fix base register for user-only qemu_ld/st Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-06 | Richard Henderson | tcg/riscv: Fix reg overlap case in tcg_out_addsub2 Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-06 | Richard Henderson | tcg/riscv: Fix range matched by TCG_CT_CONST_M12 Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-01-06 | LIU Zhiwei | target/riscv: Fix PMP propagation for tlb Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-10-14 | Alistair Francis | target/riscv: pmp: Fixup TLB size calculation Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-10-14 | Jim Shu | hw/intc: sifive_plic: change interrupt priority register... Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-10-14 | Jim Shu | hw/intc: sifive_plic: fix hard-coded max priority level Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-10-14 | Yang Liu | disas/riscv.c: rvv: Add disas support for vector instructions Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-10-14 | Sunil V L | hw/riscv: virt: Enable booting S-mode firmware from... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-10-14 | Sunil V L | hw/riscv: virt: Move create_fw_cfg() prior to loading... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-10-14 | Sunil V L | hw/arm, loongarch: Move load_image_to_fw_cfg() to common... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-10-14 | Wilfred Mallawa | hw/ssi: ibex_spi: fixup/add rw1c functionality Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-10-14 | Wilfred Mallawa | hw/ssi: ibex_spi: fixup coverity issue Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-10-14 | Bin Meng | hw/riscv: Update comment for qtest check in riscv_find_firmw... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-09-27 | Yang Liu | target/riscv: rvv-1.0: vf[w]redsum distinguish between... Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-09-27 | Yang Liu | target/riscv: rvv-1.0: Simplify vfwredsum code Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-09-27 | Frank Chang | target/riscv: debug: Add initial support of type 6... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-09-27 | Frank Chang | target/riscv: debug: Check VU/VS modes for type 2 trigger Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-09-27 | Frank Chang | target/riscv: debug: Create common trigger actions... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-09-27 | Frank Chang | target/riscv: debug: Introduce tinfo CSR Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-09-27 | Frank Chang | target/riscv: debug: Restrict the range of tselect... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-09-27 | Frank Chang | target/riscv: debug: Introduce tdata1, tdata2, and... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2022-09-27 | Frank Chang | target/riscv: debug: Introduce build_tdata1() to build... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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