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target/riscv: Add properties for BF16 extensions
2023-07-10 Weiwei Litarget/riscv: Add properties for BF16 extensions
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-07-10 Weiwei Litarget/riscv: update cur_pmbase/pmmask based on mode...
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-07-10 Weiwei Litarget/riscv: Add additional xlen for address when...
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-07-10 Weiwei Litarget/riscv: Remove redundant assignment to SXL
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-07-10 Weiwei Litarget/riscv: Support MSTATUS.MPV/GVA only when RVH...
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-07-10 Weiwei Litarget/riscv: Make MPV only work when MPP != PRV_M
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-06-13 Weiwei Litarget/riscv: Fix initialized value for cur_pmmask
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-06-13 Weiwei Litarget/riscv: Remove pc_succ_insn from DisasContext
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-06-13 Weiwei Litarget/riscv: Enable PC-relative translation
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-06-13 Weiwei Litarget/riscv: Use true diff for gen_pc_plus_diff
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-06-13 Weiwei Litarget/riscv: Change gen_set_pc_imm to gen_update_pc
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-06-13 Weiwei Litarget/riscv: Change gen_goto_tb to work on displacements
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-06-13 Weiwei Litarget/riscv: Introduce cur_insn_len into DisasContext
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-06-13 Weiwei Litarget/riscv: Fix target address to update badaddr
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-06-13 Weiwei Lidisas/riscv.c: Remove redundant parentheses
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-06-13 Weiwei Lidisas/riscv.c: Fix lines with over 80 characters
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-06-13 Weiwei Lidisas/riscv.c: Remove unused decomp_rv32/64 value for...
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-06-13 Weiwei Lidisas/riscv.c: Support disas for Z*inx extensions
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-06-13 Weiwei Lidisas/riscv.c: Support disas for Zcm* extensions
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-06-13 Weiwei Litarget/riscv: Pass RISCVCPUConfig as target_info to...
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-06-13 Weiwei Litarget/riscv: Split RISCVCPUConfig declarations from...
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-06-13 Weiwei Lidisas: Change type of disassemble_info.target_info...
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-06-13 Weiwei Litarget/riscv: Update cur_pmmask/base when xl changes
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-06-13 Weiwei Litarget/riscv: Fix pointer mask transformation for vector...
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-06-13 Weiwei Litarget/riscv: Deny access if access is partially inside...
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-06-13 Weiwei Litarget/riscv: Separate pmp_update_rule() in pmpcfg_csr_write
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-06-13 Weiwei Litarget/riscv: Flush TLB only when pmpcfg/pmpaddr really...
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-06-13 Weiwei Litarget/riscv: Flush TLB when pmpaddr is updated
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-06-13 Weiwei Litarget/riscv: Update the next rule addr in pmpaddr_csr_write()
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-06-13 Weiwei Litarget/riscv: Flush TLB when MMWP or MML bits are changed
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-06-13 Weiwei Litarget/riscv: Remove unused paramters in pmp_hart_has_privs_...
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-06-13 Weiwei Litarget/riscv: Make RLB/MML/MMWP bits writable only...
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-06-13 Weiwei Litarget/riscv: Change the return type of pmp_hart_has_privs...
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-06-13 Weiwei Litarget/riscv: Make the short cut really work in pmp_hart_has...
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-06-13 Weiwei Litarget/riscv: Move pmp_get_tlb_size apart from get_physical_...
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-06-13 Weiwei Litarget/riscv: Update pmp_get_tlb_size()
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-06-13 Weiwei Litarget/riscv: Update check for Zca/Zcf/Zcd
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-06-13 Weiwei Litarget/riscv: Mask the implicitly enabled extensions...
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-06-13 Weiwei Litarget/riscv: Move zc* out of the experimental properties
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-05-05 Weiwei Litarget/riscv: Use check for relationship between Zdinx...
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-05-05 Weiwei Litarget/riscv: Legalize MPP value in write_mstatus
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-05-05 Weiwei Litarget/riscv: Use PRV_RESERVED instead of PRV_H
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-05-05 Weiwei Litarget/riscv: Fix the mstatus.MPP value after executing...
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-05-05 Weiwei Lihw/riscv: Add signature dump function for spike to...
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-05-05 Weiwei Litarget/riscv: Fix lines with over 80 characters
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-05-05 Weiwei Litarget/riscv: Fix format for comments
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-05-05 Weiwei Litarget/riscv: Fix format for indentation
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-05-05 Weiwei Litarget/riscv: Remove riscv_cpu_virt_enabled()
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-05-05 Weiwei Litarget/riscv: Set opcode to env->bins for illegal/virtual...
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-05-05 Weiwei Litarget/riscv: Fix addr type for get_physical_address
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-05-05 Weiwei Litarget/riscv: Remove redundant parentheses
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-05-05 Weiwei Litarget/riscv: Remove check on RVH for riscv_cpu_set_virt_enabled
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-05-05 Weiwei Litarget/riscv: Remove check on RVH for riscv_cpu_virt_enabled
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-05-05 Weiwei Litarget/riscv: Remove redundant check on RVH
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-05-05 Weiwei Litarget/riscv: Remove redundant call to riscv_cpu_virt_enabled
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-05-05 Weiwei Litarget/riscv: Add support for Zce
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-05-05 Weiwei Lidisas/riscv.c: add disasm support for Zc*
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-05-05 Weiwei Litarget/riscv: expose properties for Zc* extension
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-05-05 Weiwei Litarget/riscv: add support for Zcmt extension
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-05-05 Weiwei Litarget/riscv: add support for Zcmp extension
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-05-05 Weiwei Litarget/riscv: add support for Zcb extension
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-05-05 Weiwei Litarget/riscv: add support for Zcd extension
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-05-05 Weiwei Litarget/riscv: add support for Zcf extension
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-05-05 Weiwei Litarget/riscv: add support for Zca extension
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-05-05 Weiwei Litarget/riscv: add cfg properties for Zc* extension
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-05-05 Weiwei Litarget/riscv: Simplify arguments for riscv_csrrw_check
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-05-05 Weiwei Litarget/riscv: Simplify type conversion for CPURISCVState
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-05-05 Weiwei Litarget/riscv: Simplify getting RISCVCPU pointer from env
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-05-05 Weiwei Litarget/riscv: Avoid env_archcpu() when reading RISCVCPUConfig
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-05-02 Weiwei Liaccel/tcg: Uncache the host address for instruction...
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-04-04 Weiwei Liaccel/tcg: Fix overwrite problems of tcg_cflags
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-03-02 Weiwei Litarget/riscv: Export Svadu property
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-03-02 Weiwei Litarget/riscv: Add *envcfg.HADE related check in address...
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-03-02 Weiwei Litarget/riscv: Add *envcfg.PBMTE related check in address...
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-03-02 Weiwei Litarget/riscv: Add csr support for svadu
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-03-02 Weiwei Litarget/riscv: Fix the relationship of PBMTE/STCE fields...
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-03-02 Weiwei Litarget/riscv: Fix the relationship between menvcfg...
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-03-02 Weiwei Litarget/riscv: Add support for Zicond extension
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-03-01 Weiwei Litarget/riscv: Expose properties for Zv* extensions
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-03-01 Weiwei Litarget/riscv: Simplify check for EEW = 64 in trans_rvv...
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-03-01 Weiwei Litarget/riscv: Fix check for vector load/store instructions...
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-03-01 Weiwei Litarget/riscv: Add support for Zvfh/zvfhmin extensions
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-03-01 Weiwei Litarget/riscv: Remove redundunt check for zve32f and...
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-03-01 Weiwei Litarget/riscv: Replace check for F/D to Zve32f/Zve64d...
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-03-01 Weiwei Litarget/riscv: Simplify check for Zve32f and Zve64f
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-03-01 Weiwei Litarget/riscv: Indent fixes in cpu.c
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-03-01 Weiwei Litarget/riscv: Add property check for Zvfh{min} extensions
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-03-01 Weiwei Litarget/riscv: Fix relationship between V, Zve*, F and D
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-03-01 Weiwei Litarget/riscv: Add cfg properties for Zv* extensions
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-03-01 Weiwei Litarget/riscv: Simplify the check for Zfhmin and Zhinxmin
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-03-01 Weiwei Litarget/riscv: Fix the relationship between Zhinxmin...
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2023-03-01 Weiwei Litarget/riscv: Fix the relationship between Zfhmin and Zfh
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2022-09-26 Weiwei Litarget/riscv: fix csr check for cycle{h}, instret{h...
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2022-09-07 Weiwei Litarget/riscv: Fix priority of csr related check in...
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2022-09-07 Weiwei Litarget/riscv: Simplify the check in hmode to reuse...
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2022-09-07 Weiwei Litarget/riscv: Fix checks in hmode/hmode32
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2022-09-07 Weiwei Litarget/riscv: Add check for csrs existed with U extension
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2022-09-07 Weiwei Litarget/riscv: Fix checkpatch warning may triggered...
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2022-09-07 Weiwei Litarget/riscv: H extension depends on I extension
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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2022-09-07 Weiwei Litarget/riscv: Add check for supported privilege mode...
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
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