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drm/i915: Organize GLK_COLORS.
2017-10-03 Rodrigo Vividrm/i915: Organize GLK_COLORS.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20171003063652.17248-3-rodrigo.vivi@intel.com
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2017-10-03 Rodrigo Vividrm/i915: Organize GEN features inheritance.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20171003063652.17248-2-rodrigo.vivi@intel.com
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2017-10-03 Rodrigo Vividrm/i915/skl: Fix has_ipc on skl and document WaDisableIPC.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20171003063652.17248-1-rodrigo.vivi@intel.com
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2017-10-02 David Weinehalldrm/i915: Add has_psr-flag to gen9lp
Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-09-28 Rodrigo Vividrm/i915: Also discard second CRC on gen8+ platforms.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...patch/msgid/20170928002040.7917-1-rodrigo.vivi@intel.com
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2017-09-28 vathsala nagarajudrm/i915/psr: Set frames before SU entry for psr2
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-09-28 vathsala nagarajudrm/dp: Add defines for latency in sink
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-09-27 Rodrigo Vividrm/i915: Avoid using dev_priv->info.gen directly.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170926211346.12009-1-rodrigo.vivi@intel.com
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2017-09-26 Ben Widawskydrm/i915/cnl: Add support slice/subslice/eu configs
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170920183525.20530-1-rodrigo.vivi@intel.com
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2017-09-22 Oscar Mateodrm/i915/cnl: Add Gen10 LRC size
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-09-21 Anuj Phogatdrm/i915/kbl: Change a KBL pci id to GT2 from GT1.5
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-09-19 Rodrigo Vividrm/i915/cfl: Remove alpha support protection.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170907230632.25650-1-rodrigo.vivi@intel.com
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2017-09-19 Rodrigo Vividrm/i915/cnp: Display Wa #1179: WaHardHangonHotPlug
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170919215703.25947-1-rodrigo.vivi@intel.com
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2017-09-18 Rodrigo Vividrm/i915/cnp: Don't touch other PCH clock gating bits.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170908234534.17986-1-rodrigo.vivi@intel.com
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2017-09-18 Chris Wilsondrm/i915: Remove unused 'in_vbl' from i915_get_crtc_scanoutpos()
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-09-18 Lee, Shawn Cdrm/i915/cnp: set min brightness from VBT
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-09-18 Uma ShankarRevert "drm/i915/bxt: Disable device ready before shutdown...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-09-18 Lee, Shawn Cdrm/i915/bxt: set min brightness from VBT
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-09-18 Christophe JAILLETdrm/i915: Fix an error handling in 'intel_framebuffer_init()'
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-09-18 Changbin Dudrm/i915/gvt: Fix incorrect PCI BARs reporting
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-09-18 Radhakrishna Sripadadrm/i915: Do not enable DRRS when PSR is enabled
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-09-14 Manasi Navaredrm/i915/cnl: Change the macro name to DPLL_CFGCR0_DCO_FRACT...
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-09-13 Rodrigo Vividrm/i915: Refresh VLV/CHV PSR comments on HW PSR_state...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...patch/msgid/20170912183059.5086-1-rodrigo.vivi@intel.com
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2017-09-12 Dhinakaran Pandiyandrm/i915/spt+: Don't reset invalid AUX channel interrupt...
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-09-11 Rodrigo Vividrm/i915/psr: Add enable_source vfunc.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170907230041.22978-12-rodrigo.vivi@intel.com
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2017-09-11 Rodrigo Vividrm/i915/psr: Add enable_sink vfunc.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170907230041.22978-11-rodrigo.vivi@intel.com
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2017-09-11 Rodrigo Vividrm/i915/psr: Add setup VSC vfunc.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170907230041.22978-10-rodrigo.vivi@intel.com
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2017-09-11 Rodrigo Vividrm/i915/psr: Re-org Activate after enable
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170907230041.22978-9-rodrigo.vivi@intel.com
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2017-09-11 Rodrigo Vividrm/i915/psr: Move hsw_enable_source after enabling...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170907230041.22978-8-rodrigo.vivi@intel.com
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2017-09-11 Rodrigo Vividrm/i915/psr: Re-create a hsw_psr_enable_source.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170907230041.22978-7-rodrigo.vivi@intel.com
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2017-09-11 Rodrigo Vividrm/i915/psr: Unify VSC setup functions.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170907230041.22978-6-rodrigo.vivi@intel.com
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2017-09-11 Rodrigo Vividrm/i915/psr: Add activate vfunc.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170907230041.22978-5-rodrigo.vivi@intel.com
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2017-09-11 Rodrigo Vividrm/i915/psr: hsw_psr_activate.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170907230041.22978-4-rodrigo.vivi@intel.com
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2017-09-11 Rodrigo Vividrm/i915/psr: vfunc for disabling source.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170907230041.22978-3-rodrigo.vivi@intel.com
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2017-09-11 Rodrigo Vividrm/i915/psr: Avoid any PSR stuff on platforms without...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170907230041.22978-2-rodrigo.vivi@intel.com
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2017-09-06 Rodrigo Vividrm/i915/cnl: WaThrottleEUPerfToAvoidTDBackPressure...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170906220325.24524-1-rodrigo.vivi@intel.com
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2017-09-06 Rodrigo Vividrm/i915: Display WA #1133 WaFbcSkipSegments:cnl, glk
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170905193013.31710-1-rodrigo.vivi@intel.com
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2017-09-06 Rodrigo ViviMerge tag 'gvt-fixes-2017-09-06' of https://github...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-09-06 Nanley Cherydrm/i915/cnl: Allow the reg_read ioctl to read the...
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-09-06 Chris Wilsondrm/i915: Re-enable GTT following a device reset
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-09-06 Ville Syrjälädrm/i915: Annotate user relocs with __user
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-09-05 Rodrigo Vividrm/i915/cnp: Wa 1181: Fix Backlight issue
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...patch/msgid/20170831045223.3960-1-rodrigo.vivi@intel.com
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2017-09-05 Chris Wilsondrm/i915: Silence sparse by using gfp_t
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-09-05 Ville Syrjälädrm/i915: Add __rcu to radix tree slot pointer
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-09-05 Zhi Wangdrm/i915: Fix the missing PPAT cache attributes on CNL
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-09-02 Zhi Wangdrm/i915: Fix the missing PPAT cache attributes on CNL
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-09-01 Ville Syrjälädrm/i915: Fix enum pipe vs. enum transcoder for the...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-09-01 Ville Syrjälädrm/i915: Make i2c lock ops static
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-09-01 Ville Syrjälädrm/i915: Make i9xx_load_ycbcr_conversion_matrix()...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-09-01 Manasi Navaredrm/i915/edp: Increase T12 panel delay to 900 ms to...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-08-31 Rodrigo Vividrm/i915/cnl: Fix DP max voltage
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170831145356.15932-1-rodrigo.vivi@intel.com
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2017-08-31 Rodrigo Vividrm/i915/cnl: Fix DDI hdmi level selection.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170829232230.23051-7-rodrigo.vivi@intel.com
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2017-08-31 Rodrigo Vividrm/i915/cnl: Move ddi buf trans related functions up.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170829232230.23051-6-rodrigo.vivi@intel.com
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2017-08-31 Rodrigo Vividrm/i915/cnl: Move voltage check into ddi buf trans...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170829232230.23051-5-rodrigo.vivi@intel.com
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2017-08-31 Rodrigo Vividrm/i915: Enable voltage swing before enabling DDI_BUF_CTL.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170829232230.23051-4-rodrigo.vivi@intel.com
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2017-08-31 Rodrigo Vividrm/i915: Align vswing sequences with old ddi buffer...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170829232230.23051-3-rodrigo.vivi@intel.com
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2017-08-31 Rodrigo Vividrm/i915: decouple gen9 and gen10 dp signal levels.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170829232230.23051-2-rodrigo.vivi@intel.com
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2017-08-31 Rodrigo Vividrm/i915: Introduce intel_ddi_dp_level.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170829232230.23051-1-rodrigo.vivi@intel.com
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2017-08-31 Rodrigo Vividrm/i915/cnl: Avoid ioremap_wc on Cannonlake as well.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170829230907.21363-1-rodrigo.vivi@intel.com
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2017-08-31 Rodrigo Vividrm/i915/cnl: WaDisableI2mCycleOnWRPort
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170829230751.21047-1-rodrigo.vivi@intel.com
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2017-08-31 Rodrigo Vividrm/i915/cnl: WA FtrEnableFastAnisoL1BankingFix
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170829230723.20898-1-rodrigo.vivi@intel.com
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2017-08-31 Rodrigo Vividrm/i915: Stop using long platform names on clock gating...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170829052026.15038-1-rodrigo.vivi@intel.com
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2017-08-30 Chris Wilsondrm/i915: Ignore duplicate VMA stored within the per...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-08-30 Ville Syrjälädrm/i915: Skip fence alignemnt check for the CCS plane
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-08-30 Ville Syrjälädrm/i915: Treat fb->offsets[] as a raw byte offset...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-08-30 Chris Wilsondrm/i915: Always wake the device to flush the GTT
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-08-30 Chris Wilsondrm/i915: Recreate vmapping even when the object is...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-08-30 Chris Wilsondrm/i915: Quietly cancel FBC activation if CRTC is...
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-08-24 Oscar Mateodrm/i915: Make some RPS functions static
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-08-23 Rodrigo Vividrm/i915/cnl: WaForceContextSaveRestoreNonCoherent
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170823203504.10012-1-rodrigo.vivi@intel.com
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2017-08-23 Oscar Mateodrm/i915/cnl: WaPushConstantDereferenceHoldDisable
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-08-22 Rodrigo Vividrm/i915/cfl: Coffee Lake works on Kaby Lake PCH.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...patch/msgid/20170821235056.9015-1-rodrigo.vivi@intel.com
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2017-08-22 Paulo Zanonidrm/i915/cnl: extract cnl_set_procmon_ref_values
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170822000356.17330-2-rodrigo.vivi@intel.com
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2017-08-22 Paulo Zanonidrm/i915/cnl: simplify cnl_procmon_values handling
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170822000356.17330-1-rodrigo.vivi@intel.com
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2017-08-18 Rodrigo Vividrm/i915/cnl: Apply large line width optimization
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...patch/msgid/20170815231651.975-4-rodrigo.vivi@intel.com
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2017-08-18 Rodrigo Vividrm/i915/cnl: WaDisableEnhancedSBEVertexCaching
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...patch/msgid/20170815231651.975-3-rodrigo.vivi@intel.com
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2017-08-18 Rodrigo Vividrm/i915/cnl: Add WaDisableReplayBufferBankArbitrationOptimi...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...patch/msgid/20170815231651.975-2-rodrigo.vivi@intel.com
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2017-08-18 Rodrigo Vividrm/i915/cnl: Introduce initial Cannonlake Workarounds.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...patch/msgid/20170815231651.975-1-rodrigo.vivi@intel.com
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2017-08-16 Rodrigo Vividrm/i915/cnl: Reuse skl_wm_get_hw_state on Cannonlake.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170809205248.11917-6-rodrigo.vivi@intel.com
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2017-08-16 Paulo Zanonidrm/i915/gen10: implement gen 10 watermarks calculations
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170811233825.32083-1-rodrigo.vivi@intel.com
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2017-08-16 Rodrigo Vividrm/i915/cnl: Fix LSPCON support.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170816030403.11368-1-rodrigo.vivi@intel.com
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2017-08-15 Rodrigo Vividrm/i915/cnl: Setup PAT Index.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...patch/msgid/20170815232539.3562-1-rodrigo.vivi@intel.com
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2017-08-15 Jim Bridedrm/i915/edp: Allow alternate fixed mode for eDP if...
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-08-11 Rodrigo Vividrm/i915: Introduce intel_hpd_pin function.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170811182650.14327-2-rodrigo.vivi@intel.com
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2017-08-11 Rodrigo Vividrm/i915: Simplify hpd pin to port
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170811182650.14327-1-rodrigo.vivi@intel.com
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2017-08-11 Rodrigo Vividrm/i915/cnl: Dump the right pll registers when dumping...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170810224525.18278-1-rodrigo.vivi@intel.com
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2017-08-11 Rodrigo Vividrm/i915/cnl: Add allowed DP rates for Cannonlake.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170810224008.15571-1-rodrigo.vivi@intel.com
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2017-08-11 Matthias Kaehlckedrm/i915: Return correct EDP voltage swing table for...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-08-10 Rodrigo Vividrm/i915/cnl: Add slice and subslice information to...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170809200702.11236-1-rodrigo.vivi@intel.com
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2017-08-10 Paulo Zanonidrm/i915/gen10: fix WM latency printing
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170809205248.11917-4-rodrigo.vivi@intel.com
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2017-08-10 Paulo Zanonidrm/i915/gen10: fix the gen 10 SAGV block time
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170809205248.11917-3-rodrigo.vivi@intel.com
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2017-08-10 Rodrigo Vividrm/i915/cnl: Enable SAGV for Cannonlake.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170809205248.11917-2-rodrigo.vivi@intel.com
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2017-08-10 Paulo Zanonidrm/i915/gen10+: use the SKL code for reading WM latencies
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170809205248.11917-1-rodrigo.vivi@intel.com
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2017-08-10 Rodrigo Vividrm/i915: Avoid null dereference if mst_port is unset.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170810145043.24047-1-rodrigo.vivi@intel.com
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2017-08-09 Jim Bridedrm/i915/psr: Preserve SRD_CTL bit 29 on PSR init
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-08-08 Rodrigo Vividrm/i915/cnl: Removing missing DDI_E bits from CNL.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170808193237.17410-1-rodrigo.vivi@intel.com
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2017-08-03 Praveen Paneridrm/i915: enable WaDisableDopClkGating for skl
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-08-03 Rodrigo Vividrm/i915: Fix PCH names for KBP and CNP.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...patch/msgid/20170731185220.758-1-rodrigo.vivi@intel.com
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2017-07-11 Rodrigo Vividrm/i915/cnl: Add missing type case.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170710205852.28352-1-rodrigo.vivi@intel.com
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2017-07-10 Rodrigo Vividrm/i915/cnl: Add max allowed Cannonlake DC.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1499373908-26761-1-git-send-email-rodrigo.vivi@intel.com
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