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Merge tag 'hw-misc-20231019' of https://github.com/philmd/qemu into staging
2023-10-18 Jiajie Chenlinux-user/elfload: Enable LSX/LASX in HWCAP for LoongArch
Signed-off-by: Jiajie Chen <c@jia.je>
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2023-10-13 Jiajie Chentarget/loongarch: fix ASXE flag conflict
Signed-off-by: Jiajie Chen <c@jia.je>
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2023-09-16 Jiajie Chentcg/loongarch64: Implement 128-bit load & store
Signed-off-by: Jiajie Chen <c@jia.je>
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2023-09-15 Jiajie Chentcg/loongarch64: Lower rotli_vec to vrotri
Signed-off-by: Jiajie Chen <c@jia.je>
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2023-09-15 Jiajie Chentcg/loongarch64: Lower rotv_vec ops to LSX
Signed-off-by: Jiajie Chen <c@jia.je>
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2023-09-15 Jiajie Chentcg/loongarch64: Lower vector shift integer ops
Signed-off-by: Jiajie Chen <c@jia.je>
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2023-09-15 Jiajie Chentcg/loongarch64: Lower bitsel_vec to vbitsel
Signed-off-by: Jiajie Chen <c@jia.je>
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2023-09-15 Jiajie Chentcg/loongarch64: Lower vector shift vector ops
Signed-off-by: Jiajie Chen <c@jia.je>
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2023-09-15 Jiajie Chentcg/loongarch64: Lower vector saturated ops
Signed-off-by: Jiajie Chen <c@jia.je>
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2023-09-15 Jiajie Chentcg/loongarch64: Lower vector min max ops
Signed-off-by: Jiajie Chen <c@jia.je>
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2023-09-15 Jiajie Chentcg/loongarch64: Lower mul_vec to vmul
Signed-off-by: Jiajie Chen <c@jia.je>
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2023-09-15 Jiajie Chentcg/loongarch64: Lower neg_vec to vneg
Signed-off-by: Jiajie Chen <c@jia.je>
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2023-09-15 Jiajie Chentcg/loongarch64: Lower vector bitwise operations
Signed-off-by: Jiajie Chen <c@jia.je>
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2023-09-15 Jiajie Chentcg/loongarch64: Lower add/sub_vec to vadd/vsub
Signed-off-by: Jiajie Chen <c@jia.je>
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2023-09-15 Jiajie Chentcg/loongarch64: Lower cmp_vec to vseq/vsle/vslt
Signed-off-by: Jiajie Chen <c@jia.je>
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2023-09-15 Jiajie Chentcg: pass vece to tcg_target_const_match()
Signed-off-by: Jiajie Chen <c@jia.je>
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2023-09-15 Jiajie Chentcg/loongarch64: Lower basic tcg vec ops to LSX
Signed-off-by: Jiajie Chen <c@jia.je>
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2023-09-15 Jiajie Chentcg/loongarch64: Import LSX instructions
Signed-off-by: Jiajie Chen <c@jia.je>
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2023-08-24 Jiajie Chenhw/loongarch: Fix ACPI processor id off-by-one error
Signed-off-by: Jiajie Chen <c@jia.je>
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2023-08-24 Jiajie Chentarget/loongarch: Split fcc register to fcc0-7 in gdbstub
Signed-off-by: Jiajie Chen <c@jia.je>
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2023-08-24 Jiajie Chentarget/loongarch: Add LoongArch32 cpu la132
Signed-off-by: Jiajie Chen <c@jia.je>
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2023-08-24 Jiajie Chentarget/loongarch: Sign extend results in VA32 mode
Signed-off-by: Jiajie Chen <c@jia.je>
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2023-08-24 Jiajie Chentarget/loongarch: Truncate high 32 bits of address...
Signed-off-by: Jiajie Chen <c@jia.je>
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2023-08-24 Jiajie Chentarget/loongarch: Extract set_pc() helper
Signed-off-by: Jiajie Chen <c@jia.je>
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2023-08-24 Jiajie Chentarget/loongarch: Extract make_address_pc() helper
Signed-off-by: Jiajie Chen <c@jia.je>
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2023-08-24 Jiajie Chentarget/loongarch: Extract make_address_i() helper
Signed-off-by: Jiajie Chen <c@jia.je>
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2023-08-24 Jiajie Chentarget/loongarch: Extract make_address_x() helper
Signed-off-by: Jiajie Chen <c@jia.je>
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2023-08-24 Jiajie Chentarget/loongarch: Add LA64 & VA32 to DisasContext
Signed-off-by: Jiajie Chen <c@jia.je>
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2023-08-24 Jiajie Chentarget/loongarch: Support LoongArch32 VPPN
Signed-off-by: Jiajie Chen <c@jia.je>
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2023-08-24 Jiajie Chentarget/loongarch: Support LoongArch32 DMW
Signed-off-by: Jiajie Chen <c@jia.je>
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2023-08-24 Jiajie Chentarget/loongarch: Support LoongArch32 TLB entry
Signed-off-by: Jiajie Chen <c@jia.je>
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2023-08-24 Jiajie Chentarget/loongarch: Add GDB support for loongarch32 mode
Signed-off-by: Jiajie Chen <c@jia.je>
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2023-08-24 Jiajie Chentarget/loongarch: Add new object class for loongarch32...
Signed-off-by: Jiajie Chen <c@jia.je>
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2023-08-24 Jiajie Chentarget/loongarch: Add function to check current arch
Signed-off-by: Jiajie Chen <c@jia.je>
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2023-06-16 Jiajie Chentarget/loongarch: Fix CSR.DMW0-3.VSEG check
Signed-off-by: Jiajie Chen <c@jia.je>
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