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2017-10-20 | Madhav Chauhan | drm/i915: Parse DSI backlight/cabc ports. Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com> ...1507898700-20016-1-git-send-email-madhav.chauhan@intel.com |
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2017-06-15 | Madhav Chauhan | drm/i915/glk: Add cold boot sequence for GLK DSI Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com> ...1497340095-5877-2-git-send-email-madhav.chauhan@intel.com |
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2017-06-15 | Madhav Chauhan | drm/i915/glk: Split GLK DSI device ready functionality Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com> ...1497340095-5877-1-git-send-email-madhav.chauhan@intel.com |
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2017-05-15 | Madhav Chauhan | drm/i915/glk: Calculate high/low switch count for GLK Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com> ...1494336565-19185-1-git-send-email-madhav.chauhan@intel.com |
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2017-04-06 | Madhav Chauhan | drm/i915/glk: limit pixel clock to 99% of cdclk workaround Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com> ...1491397463-13637-1-git-send-email-madhav.chauhan@intel.com |
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2017-03-02 | Madhav Chauhan | drm/i915/glk: Fix DSI enable I/O sequence Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com> ...1488393082-30660-1-git-send-email-madhav.chauhan@intel.com |
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2017-02-28 | Madhav Chauhan | drm/i915/glk: Validate only DSI PORT A PLL divider Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com> ...1487335415-14766-8-git-send-email-madhav.chauhan@intel.com |
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2016-12-02 | Madhav Chauhan | drm/i915/glk: Update Port PLL enable sequence for Geminilkae Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com> |
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