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target/riscv: Fix page_check_range use in fault-only-first
2023-09-11 LIU Zhiweitarget/riscv: Fix page_check_range use in fault-only...
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
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2023-07-10 LIU Zhiweitarget/riscv: Use xl instead of mxl for disassemble
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
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2023-05-05 LIU Zhiweitarget/riscv: Add a tb flags field for vstart
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
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2023-05-05 LIU Zhiweitarget/riscv: Encode the FS and VS on a normal way...
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
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2023-05-05 LIU Zhiweitarget/riscv: Add a general status enum for extensions
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
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2023-05-05 LIU Zhiweitarget/riscv: Extract virt enabled state from tb flags
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
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2023-05-05 LIU Zhiweitarget/riscv: Convert env->virt to a bool env->virt_enabled
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
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2023-05-05 LIU Zhiweitarget/riscv: Fix itrigger when icount is used
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
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2023-05-05 LIU Zhiweitarget/riscv: Fix priv version dependency for vector...
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
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2023-02-23 LIU Zhiweitarget/riscv: Fix vslide1up.vf and vslide1down.vf
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
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2023-01-06 LIU Zhiweitarget/riscv: Add itrigger_enabled field to CPURISCVState
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
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2023-01-06 LIU Zhiweitarget/riscv: Enable native debug itrigger
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
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2023-01-06 LIU Zhiweitarget/riscv: Add itrigger support when icount is enabled
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
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2023-01-06 LIU Zhiweitarget/riscv: Add itrigger support when icount is not...
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
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2023-01-06 LIU Zhiweitarget/riscv: Fix PMP propagation for tlb
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
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2022-02-16 LIU Zhiweitarget/riscv: Fix vill field write in vtype
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2022-01-21 LIU Zhiweitarget/riscv: Relax UXL field for debugging
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2022-01-21 LIU Zhiweitarget/riscv: Enable uxl field write
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2022-01-21 LIU Zhiweitarget/riscv: Set default XLEN for hypervisor
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2022-01-21 LIU Zhiweitarget/riscv: Adjust scalar reg in vector with XLEN
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2022-01-21 LIU Zhiweitarget/riscv: Adjust vector address with mask
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2022-01-21 LIU Zhiweitarget/riscv: Fix check range for first fault only
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2022-01-21 LIU Zhiweitarget/riscv: Remove VILL field in VTYPE
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2022-01-21 LIU Zhiweitarget/riscv: Adjust vsetvl according to XLEN
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2022-01-21 LIU Zhiweitarget/riscv: Split out the vill from vtype
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2022-01-21 LIU Zhiweitarget/riscv: Split pm_enabled into mask and base
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2022-01-21 LIU Zhiweitarget/riscv: Calculate address according to XLEN
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2022-01-21 LIU Zhiweitarget/riscv: Alloc tcg global for cur_pm[mask|base]
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2022-01-21 LIU Zhiweitarget/riscv: Create current pm fields in env
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2022-01-21 LIU Zhiweitarget/riscv: Adjust csr write mask with XLEN
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2022-01-21 LIU Zhiweitarget/riscv: Relax debug check for pm write
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2022-01-21 LIU Zhiweitarget/riscv: Use gdb xml according to max mxlen
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2022-01-21 LIU Zhiweitarget/riscv: Extend pc for runtime pc write
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2022-01-21 LIU Zhiweitarget/riscv: Ignore the pc bits above XLEN
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2022-01-21 LIU Zhiweitarget/riscv: Create xl field in env
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2022-01-21 LIU Zhiweitarget/riscv: Sign extend pc for different XLEN
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2022-01-21 LIU Zhiweitarget/riscv: Sign extend link reg for jal and jalr
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2022-01-21 LIU Zhiweitarget/riscv: Don't save pc when exception return
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2022-01-21 LIU Zhiweitarget/riscv: Adjust pmpcfg access with mxl
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2021-12-20 LIU Zhiweitarget/riscv: rvv-1.0: add vcsr register
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2021-12-20 LIU Zhiweitarget/riscv: rvv-1.0: add sstatus VS field
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2021-12-20 LIU Zhiweitarget/riscv: rvv-1.0: add mstatus VS field
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2021-09-20 LIU Zhiweitarget/riscv: Fix satp write
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2021-09-01 LIU Zhiweitarget/riscv: Add User CSRs read-only check
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2021-09-01 LIU Zhiweitarget/riscv: Don't wrongly override isa version
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2021-06-29 LIU Zhiweitcg: Implement tcg_gen_vec_add{sub}32_tl
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2021-06-29 LIU Zhiweitcg: Add tcg_gen_vec_shl{shr}{sar}8i_i32
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2021-06-29 LIU Zhiweitcg: Add tcg_gen_vec_shl{shr}{sar}16i_i32
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2021-06-29 LIU Zhiweitcg: Add tcg_gen_vec_add{sub}8_i32
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2021-06-29 LIU Zhiweitcg: Add tcg_gen_vec_add{sub}16_i32
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2021-06-07 LIU Zhiweitarget/riscv: Pass the same value to oprsz and maxsz.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2021-05-11 LIU Zhiweitarget/riscv: Fixup saturate subtract function
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2020-08-28 LIU Zhiweisoftfloat: Define misc operations for bfloat16
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2020-08-28 LIU Zhiweisoftfloat: Define convert operations for bfloat16
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2020-08-28 LIU Zhiweisoftfloat: Define operations for bfloat16
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2020-08-22 LIU Zhiweitarget/riscv: check before allocating TCG temps
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2020-08-22 LIU Zhiweitarget/riscv: Clean up fmv.w.x
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2020-07-22 LIU Zhiweitarget/riscv: fix vector index load/store constraints
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2020-07-22 LIU Zhiweitarget/riscv: Quiet Coverity complains about vamo*
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2020-07-15 LIU Zhiweifpu/softfloat: fix up float16 nan recognition
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2020-07-02 LIU Zhiweitarget/riscv: configure and turn on vector extension...
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector compress instruction
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector register gather instruction
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector slide instructions
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2020-07-02 LIU Zhiweitarget/riscv: floating-point scalar move instructions
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2020-07-02 LIU Zhiweitarget/riscv: integer scalar move instruction
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2020-07-02 LIU Zhiweitarget/riscv: integer extract instruction
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector element index instruction
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector iota instruction
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2020-07-02 LIU Zhiweitarget/riscv: set-X-first mask bit
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2020-07-02 LIU Zhiweitarget/riscv: vmfirst find-first-set mask bit
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector mask population count vmpopc
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector mask-register logical instructions
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector widening floating-point reduction...
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector single-width floating-point reduction...
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector wideing integer reduction instructions
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector single-width integer reduction...
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2020-07-02 LIU Zhiweitarget/riscv: narrowing floating-point/integer type...
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2020-07-02 LIU Zhiweitarget/riscv: widening floating-point/integer type...
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector floating-point/integer type-convert...
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector floating-point merge instructions
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector floating-point classify instructions
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector floating-point compare instructions
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector floating-point sign-injection...
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector floating-point min/max instructions
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector floating-point square-root instruction
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector widening floating-point fused...
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector single-width floating-point fused...
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector widening floating-point multiply
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector single-width floating-point multiply...
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector widening floating-point add/subtract...
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector single-width floating-point add...
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector narrowing fixed-point clip instructions
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector single-width scaling shift instructions
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector widening saturating scaled multiply-add
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector single-width fractional multiply...
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector single-width averaging add and...
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector single-width saturating add and...
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector integer merge and move instructions
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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2020-07-02 LIU Zhiweitarget/riscv: vector widening integer multiply-add...
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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