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2015-04-16 | Satheeshakrishna M | drm/i915/bxt: Determine programmed frequency Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com... |
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2015-04-16 | Satheeshakrishna M | drm/i915/bxt: Determine PLL attached to pipe Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com... |
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2015-04-16 | Satheeshakrishna M | drm/i915/bxt: Assign PLL for pipe Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com... |
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2015-04-16 | Satheeshakrishna M | drm/i915/bxt: BXT clock divider calculation Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com... |
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2015-04-16 | Satheeshakrishna M | drm/i915/bxt: Define bxt DDI PLLs and implement enable... Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com... |
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2015-04-16 | Satheeshakrishna M | drm/i915/bxt: Restrict PORT_CLK_SEL programming below... Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com> |
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2015-04-14 | Satheeshakrishna M | drm/i915/bxt: Define BXT power domains Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com... |
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2015-04-09 | Satheeshakrishna M | drm/i915/bxt: Add IS_BROXTON macro Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com> |
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2015-02-13 | Satheeshakrishna M | drm/i915/skl: Implementation of SKL display power well... Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com... |
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2015-01-27 | Satheeshakrishna M | drm/i915/skl: Adding power domains for AUX controllers Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com> |
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2014-11-14 | Satheeshakrishna M | drm/i915/skl: Implementation of SKL DPLL programming Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com... |
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2014-11-14 | Satheeshakrishna M | drm/i915/skl: Adjust the port PLL selection code Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com> |
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2014-11-14 | Satheeshakrishna M | drm/i915/skl: Define shared DPLLs for Skylake Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com... |
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2014-11-14 | Satheeshakrishna M | drm/i915/skl: Query DPLL attached to port on SKL Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com> |
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2014-11-14 | Satheeshakrishna M | drm/i915/skl: Determine enabled PLL and its linkrate... Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com... |
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2014-11-14 | Satheeshakrishna M | drm/i915/skl: CD clock back calculation for SKL Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com> |
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2014-11-14 | Satheeshakrishna M | drm/i915/skl: Structure/enum definitions for SKL clocks Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com... |
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2014-11-14 | Satheeshakrishna M | drm/i915/skl: Register definitions for SKL Clocks Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com... |
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2014-09-24 | Satheeshakrishna M | drm/i915/skl: Sunrise Point PCH detection Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com> |
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2014-09-24 | Satheeshakrishna M | drm/i915/skl: Restore pipe B/C interrupts Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com> |
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2014-09-24 | Satheeshakrishna M | drm/i915/skl: SKL backlight enabling Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com> |
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2014-09-24 | Satheeshakrishna M | drm/i915/skl: vfuncs for skl eld and global resource Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com... |
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2014-09-24 | Satheeshakrishna M | drm/i915/skl: SKL pipe misc programming Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com> |
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2014-09-24 | Satheeshakrishna M | drm/i915/skl: Add an IS_SKYLAKE macro Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com> |
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