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drm/i915/cnl: Fix PLL mapping.
2017-10-16 Rodrigo Vividrm/i915/cnl: Fix PLL mapping.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20171003220859.21352-2-rodrigo.vivi@intel.com
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2017-10-16 Rodrigo Vividrm/i915/cnl: WaRsUseTimeoutMode
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170822235828.18322-1-rodrigo.vivi@intel.com
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2017-10-03 Rodrigo Vividrm/i915: Organize GLK_COLORS.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20171003063652.17248-3-rodrigo.vivi@intel.com
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2017-10-03 Rodrigo Vividrm/i915: Organize GEN features inheritance.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20171003063652.17248-2-rodrigo.vivi@intel.com
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2017-10-03 Rodrigo Vividrm/i915/skl: Fix has_ipc on skl and document WaDisableIPC.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20171003063652.17248-1-rodrigo.vivi@intel.com
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2017-09-28 Rodrigo Vividrm/i915: Also discard second CRC on gen8+ platforms.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...patch/msgid/20170928002040.7917-1-rodrigo.vivi@intel.com
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2017-09-27 Rodrigo Vividrm/i915: Avoid using dev_priv->info.gen directly.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170926211346.12009-1-rodrigo.vivi@intel.com
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2017-09-19 Rodrigo Vividrm/i915/cfl: Remove alpha support protection.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170907230632.25650-1-rodrigo.vivi@intel.com
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2017-09-19 Rodrigo Vividrm/i915/cnp: Display Wa #1179: WaHardHangonHotPlug
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170919215703.25947-1-rodrigo.vivi@intel.com
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2017-09-18 Rodrigo Vividrm/i915/cnp: Don't touch other PCH clock gating bits.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170908234534.17986-1-rodrigo.vivi@intel.com
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2017-09-13 Rodrigo Vividrm/i915: Refresh VLV/CHV PSR comments on HW PSR_state...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...patch/msgid/20170912183059.5086-1-rodrigo.vivi@intel.com
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2017-09-11 Rodrigo Vividrm/i915/psr: Add enable_source vfunc.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170907230041.22978-12-rodrigo.vivi@intel.com
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2017-09-11 Rodrigo Vividrm/i915/psr: Add enable_sink vfunc.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170907230041.22978-11-rodrigo.vivi@intel.com
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2017-09-11 Rodrigo Vividrm/i915/psr: Add setup VSC vfunc.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170907230041.22978-10-rodrigo.vivi@intel.com
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2017-09-11 Rodrigo Vividrm/i915/psr: Re-org Activate after enable
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170907230041.22978-9-rodrigo.vivi@intel.com
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2017-09-11 Rodrigo Vividrm/i915/psr: Move hsw_enable_source after enabling...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170907230041.22978-8-rodrigo.vivi@intel.com
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2017-09-11 Rodrigo Vividrm/i915/psr: Re-create a hsw_psr_enable_source.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170907230041.22978-7-rodrigo.vivi@intel.com
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2017-09-11 Rodrigo Vividrm/i915/psr: Unify VSC setup functions.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170907230041.22978-6-rodrigo.vivi@intel.com
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2017-09-11 Rodrigo Vividrm/i915/psr: Add activate vfunc.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170907230041.22978-5-rodrigo.vivi@intel.com
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2017-09-11 Rodrigo Vividrm/i915/psr: hsw_psr_activate.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170907230041.22978-4-rodrigo.vivi@intel.com
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2017-09-11 Rodrigo Vividrm/i915/psr: vfunc for disabling source.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170907230041.22978-3-rodrigo.vivi@intel.com
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2017-09-11 Rodrigo Vividrm/i915/psr: Avoid any PSR stuff on platforms without...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170907230041.22978-2-rodrigo.vivi@intel.com
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2017-09-06 Rodrigo Vividrm/i915/cnl: WaThrottleEUPerfToAvoidTDBackPressure...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170906220325.24524-1-rodrigo.vivi@intel.com
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2017-09-06 Rodrigo Vividrm/i915: Display WA #1133 WaFbcSkipSegments:cnl, glk
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170905193013.31710-1-rodrigo.vivi@intel.com
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2017-09-06 Rodrigo ViviMerge tag 'gvt-fixes-2017-09-06' of https://github...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-09-05 Rodrigo Vividrm/i915/cnp: Wa 1181: Fix Backlight issue
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...patch/msgid/20170831045223.3960-1-rodrigo.vivi@intel.com
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2017-08-31 Rodrigo Vividrm/i915/cnl: Fix DP max voltage
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170831145356.15932-1-rodrigo.vivi@intel.com
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2017-08-31 Rodrigo Vividrm/i915/cnl: Fix DDI hdmi level selection.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170829232230.23051-7-rodrigo.vivi@intel.com
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2017-08-31 Rodrigo Vividrm/i915/cnl: Move ddi buf trans related functions up.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170829232230.23051-6-rodrigo.vivi@intel.com
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2017-08-31 Rodrigo Vividrm/i915/cnl: Move voltage check into ddi buf trans...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170829232230.23051-5-rodrigo.vivi@intel.com
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2017-08-31 Rodrigo Vividrm/i915: Enable voltage swing before enabling DDI_BUF_CTL.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170829232230.23051-4-rodrigo.vivi@intel.com
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2017-08-31 Rodrigo Vividrm/i915: Align vswing sequences with old ddi buffer...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170829232230.23051-3-rodrigo.vivi@intel.com
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2017-08-31 Rodrigo Vividrm/i915: decouple gen9 and gen10 dp signal levels.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170829232230.23051-2-rodrigo.vivi@intel.com
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2017-08-31 Rodrigo Vividrm/i915: Introduce intel_ddi_dp_level.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170829232230.23051-1-rodrigo.vivi@intel.com
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2017-08-31 Rodrigo Vividrm/i915/cnl: Avoid ioremap_wc on Cannonlake as well.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170829230907.21363-1-rodrigo.vivi@intel.com
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2017-08-31 Rodrigo Vividrm/i915/cnl: WaDisableI2mCycleOnWRPort
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170829230751.21047-1-rodrigo.vivi@intel.com
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2017-08-31 Rodrigo Vividrm/i915/cnl: WA FtrEnableFastAnisoL1BankingFix
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170829230723.20898-1-rodrigo.vivi@intel.com
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2017-08-31 Rodrigo Vividrm/i915: Stop using long platform names on clock gating...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170829052026.15038-1-rodrigo.vivi@intel.com
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2017-08-30 Rodrigo Vividrm/tve200: Pass NULL format_modifier to drm_simple_display_...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170825201612.23056-1-rodrigo.vivi@intel.com
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2017-08-23 Rodrigo Vividrm/i915/cnl: WaForceContextSaveRestoreNonCoherent
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170823203504.10012-1-rodrigo.vivi@intel.com
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2017-08-22 Rodrigo Vividrm/i915/cfl: Coffee Lake works on Kaby Lake PCH.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...patch/msgid/20170821235056.9015-1-rodrigo.vivi@intel.com
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2017-08-18 Rodrigo Vividrm/i915/cnl: Apply large line width optimization
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...patch/msgid/20170815231651.975-4-rodrigo.vivi@intel.com
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2017-08-18 Rodrigo Vividrm/i915/cnl: WaDisableEnhancedSBEVertexCaching
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...patch/msgid/20170815231651.975-3-rodrigo.vivi@intel.com
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2017-08-18 Rodrigo Vividrm/i915/cnl: Add WaDisableReplayBufferBankArbitrationOptimi...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...patch/msgid/20170815231651.975-2-rodrigo.vivi@intel.com
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2017-08-18 Rodrigo Vividrm/i915/cnl: Introduce initial Cannonlake Workarounds.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...patch/msgid/20170815231651.975-1-rodrigo.vivi@intel.com
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2017-08-16 Rodrigo Vividrm/i915/cnl: Fix LSPCON support.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170816030403.11368-1-rodrigo.vivi@intel.com
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2017-08-16 Rodrigo Vividrm/i915/cnl: Reuse skl_wm_get_hw_state on Cannonlake.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170809205248.11917-6-rodrigo.vivi@intel.com
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2017-08-16 Rodrigo Vividrm/i915/cnl: Fix LSPCON support.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170816030403.11368-1-rodrigo.vivi@intel.com
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2017-08-15 Rodrigo Vividrm/i915/cnl: Setup PAT Index.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...patch/msgid/20170815232539.3562-1-rodrigo.vivi@intel.com
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2017-08-14 Rodrigo Vividrm/i915/cnl: Add slice and subslice information to...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170809200702.11236-1-rodrigo.vivi@intel.com
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2017-08-11 Rodrigo Vividrm/i915: Introduce intel_hpd_pin function.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170811182650.14327-2-rodrigo.vivi@intel.com
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2017-08-11 Rodrigo Vividrm/i915: Simplify hpd pin to port
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170811182650.14327-1-rodrigo.vivi@intel.com
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2017-08-11 Rodrigo Vividrm/i915/cnl: Dump the right pll registers when dumping...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170810224525.18278-1-rodrigo.vivi@intel.com
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2017-08-11 Rodrigo Vividrm/i915/cnl: Add allowed DP rates for Cannonlake.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170810224008.15571-1-rodrigo.vivi@intel.com
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2017-08-10 Rodrigo Vividrm/i915/cnl: Add slice and subslice information to...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170809200702.11236-1-rodrigo.vivi@intel.com
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2017-08-10 Rodrigo Vividrm/i915/cnl: Enable SAGV for Cannonlake.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170809205248.11917-2-rodrigo.vivi@intel.com
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2017-08-10 Rodrigo Vividrm/i915: Avoid null dereference if mst_port is unset.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170810145043.24047-1-rodrigo.vivi@intel.com
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2017-08-08 Rodrigo Vividrm/i915/cnl: Removing missing DDI_E bits from CNL.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170808193237.17410-1-rodrigo.vivi@intel.com
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2017-08-03 Rodrigo Vividrm/i915: Fix PCH names for KBP and CNP.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...patch/msgid/20170731185220.758-1-rodrigo.vivi@intel.com
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2017-07-11 Rodrigo Vividrm/i915/cnl: Add missing type case.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...msgid/20170710205852.28352-1-rodrigo.vivi@intel.com
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2017-07-10 Rodrigo Vividrm/i915/cnl: Add max allowed Cannonlake DC.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1499373908-26761-1-git-send-email-rodrigo.vivi@intel.com
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2017-07-07 Rodrigo Vividrm/i915/cnl: Get DDI clock based on PLLs.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1499374321-31152-1-git-send-email-rodrigo.vivi@intel.com
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2017-07-07 Rodrigo Vividrm/i915/cnl: Inherit RPS stuff from previous platforms.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1499373673-25066-1-git-send-email-rodrigo.vivi@intel.com
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2017-07-07 Rodrigo Vividrm/i915/cnl: Gen10 render context size.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1499375184-5725-1-git-send-email-rodrigo.vivi@intel.com
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2017-07-07 Rodrigo Vividrm/i915/cnl: Don't trust VBT's alternate pin for port...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1499375295-6454-1-git-send-email-rodrigo.vivi@intel.com
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2017-07-06 Rodrigo Vividrm/i915/cnl: Cannonlake color init.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1499374873-2454-1-git-send-email-rodrigo.vivi@intel.com
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2017-07-06 Rodrigo Vividrm/i915/cnl: Add force wake for gen10+.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1499302831-17773-1-git-send-email-rodrigo.vivi@intel.com
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2017-07-03 Rodrigo Vividrm/i915/cfl: Fix Workarounds.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-06-29 Rodrigo Vividrm/i915/cfl: Fix Workarounds.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-06-26 Rodrigo Vividrm/i915/cnl: Fix RMW on ddi vswing sequence.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1497897572-22520-1-git-send-email-rodrigo.vivi@intel.com
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2017-06-19 Rodrigo Vividrm/i915/cnl: Fix RMW on ddi vswing sequence.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1497897572-22520-1-git-send-email-rodrigo.vivi@intel.com
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2017-06-16 Rodrigo Vividrm/i915/cfl: Introduce Coffee Lake workarounds.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1497653398-15722-1-git-send-email-rodrigo.vivi@intel.com
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2017-06-15 Rodrigo ViviRevert "drm/i915/skl: New ddb allocation algorithm"
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1497376350-3400-1-git-send-email-rodrigo.vivi@intel.com
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2017-06-12 Rodrigo Vividrm/i915/cfl: Basic DDI plumbing for Coffee Lake.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1497045770-21302-1-git-send-email-rodrigo.vivi@intel.com
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2017-06-12 Rodrigo Vividrm/i915/cnl: LSPCON support is gen9+
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1497047175-27250-17-git-send-email-rodrigo.vivi@intel.com
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2017-06-12 Rodrigo Vividrm/i915/cnl: Enable fifo underrun for Cannonlake.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1497047175-27250-16-git-send-email-rodrigo.vivi@intel.com
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2017-06-12 Rodrigo Vividrm/i915/cnl: Fix Cannonlake scaler mode programing.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1497047175-27250-15-git-send-email-rodrigo.vivi@intel.com
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2017-06-12 Rodrigo Vividrm/i915: Use HAS_CSR instead of gen number on DMC...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1497047175-27250-14-git-send-email-rodrigo.vivi@intel.com
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2017-06-12 Rodrigo Vividrm/i915/cnl: Implement voltage swing sequence.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1497047175-27250-11-git-send-email-rodrigo.vivi@intel.com
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2017-06-12 Rodrigo Vividrm/i915/cnl: Add DDI Buffer translation tables for...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1497047175-27250-10-git-send-email-rodrigo.vivi@intel.com
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2017-06-12 Rodrigo Vividrm/i915/cnl: Add registers related to voltage swing...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1497047175-27250-9-git-send-email-rodrigo.vivi@intel.com
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2017-06-12 Rodrigo Vividrm/i915: Add MMIO helper for 6 ports with different...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1497047175-27250-8-git-send-email-rodrigo.vivi@intel.com
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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2017-06-12 Rodrigo Vividrm/i915/cnl: Initialize PLLs
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1497047175-27250-7-git-send-email-rodrigo.vivi@intel.com
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2017-06-12 Rodrigo Vividrm/i915/cnl: DDI - PLL mapping
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1497047175-27250-5-git-send-email-rodrigo.vivi@intel.com
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2017-06-12 Rodrigo Vividrm/i915/cnl: Allow dynamic cdclk changes on CNL
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1497047175-27250-4-git-send-email-rodrigo.vivi@intel.com
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2017-06-09 Rodrigo Vividrm/i915/cfl: Coffee Lake reuses Kabylake DMC.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1497038550-30910-1-git-send-email-rodrigo.vivi@intel.com
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2017-06-08 Rodrigo Vividrm/i915/cfl: Introduce Display workarounds for Coffee...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1496937000-8450-3-git-send-email-rodrigo.vivi@intel.com
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2017-06-08 Rodrigo Vividrm/i915/cfl: Coffee Lake uses CNP PCH.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1496937000-8450-2-git-send-email-rodrigo.vivi@intel.com
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2017-06-08 Rodrigo Vividrm/i915/cfl: Introduce Coffee Lake platform definition.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1496937000-8450-1-git-send-email-rodrigo.vivi@intel.com
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2017-06-07 Rodrigo Vividrm/i915: Unify GT* and GT3 definitions
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1496765166-7068-1-git-send-email-rodrigo.vivi@intel.com
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2017-06-07 Rodrigo Vividrm/i915: Remove unnecessary PORT3 definition.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1496700722-13755-1-git-send-email-rodrigo.vivi@intel.com
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2017-06-07 Rodrigo Vividrm/i915/cnl: Also need power well sanitize.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1496781040-20888-11-git-send-email-rodrigo.vivi@intel.com
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2017-06-07 Rodrigo Vividrm/i915/cnl: Cannonlake has same MOCS table than Skylake.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1496781040-20888-8-git-send-email-rodrigo.vivi@intel.com
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2017-06-07 Rodrigo Vividrm/i915/cnl: Configure EU slice power gating.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1496781040-20888-7-git-send-email-rodrigo.vivi@intel.com
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2017-06-07 Rodrigo Vividrm/i915/cnl: Add Cannonlake PCI IDs for Y-skus.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1496781040-20888-4-git-send-email-rodrigo.vivi@intel.com
 commit | commitdiff | tree
2017-06-07 Rodrigo Vividrm/i915/cnl: Add Cannonlake PCI IDs for U-skus.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1496781040-20888-3-git-send-email-rodrigo.vivi@intel.com
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2017-06-07 Rodrigo Vividrm/i915/cnl: Cannonlake uses CNP PCH.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1496781040-20888-2-git-send-email-rodrigo.vivi@intel.com
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2017-06-07 Rodrigo Vividrm/i915/cnl: Introduce Cannonlake platform defition.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1496781040-20888-1-git-send-email-rodrigo.vivi@intel.com
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2017-06-02 Rodrigo Vividrm/i915/cnp: Panel Power sequence changes for CNP...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1496434004-29812-6-git-send-email-rodrigo.vivi@intel.com
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2017-06-02 Rodrigo Vividrm/i915/cnp: add CNP gmbus support
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
...1496434004-29812-5-git-send-email-rodrigo.vivi@intel.com
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