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2017-08-31 | Rodrigo Vivi | drm/i915: Stop using long platform names on clock gating... Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...msgid/20170829052026.15038-1-rodrigo.vivi@intel.com |
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2017-08-23 | Rodrigo Vivi | drm/i915/cnl: WaForceContextSaveRestoreNonCoherent Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...msgid/20170823203504.10012-1-rodrigo.vivi@intel.com |
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2017-08-22 | Rodrigo Vivi | drm/i915/cfl: Coffee Lake works on Kaby Lake PCH. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...patch/msgid/20170821235056.9015-1-rodrigo.vivi@intel.com |
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2017-08-18 | Rodrigo Vivi | drm/i915/cnl: Apply large line width optimization Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...patch/msgid/20170815231651.975-4-rodrigo.vivi@intel.com |
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2017-08-18 | Rodrigo Vivi | drm/i915/cnl: WaDisableEnhancedSBEVertexCaching Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...patch/msgid/20170815231651.975-3-rodrigo.vivi@intel.com |
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2017-08-18 | Rodrigo Vivi | drm/i915/cnl: Add WaDisableReplayBufferBankArbitrationOptimi... Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...patch/msgid/20170815231651.975-2-rodrigo.vivi@intel.com |
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2017-08-18 | Rodrigo Vivi | drm/i915/cnl: Introduce initial Cannonlake Workarounds. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...patch/msgid/20170815231651.975-1-rodrigo.vivi@intel.com |
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2017-08-16 | Rodrigo Vivi | drm/i915/cnl: Reuse skl_wm_get_hw_state on Cannonlake. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...msgid/20170809205248.11917-6-rodrigo.vivi@intel.com |
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2017-08-16 | Rodrigo Vivi | drm/i915/cnl: Fix LSPCON support. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...msgid/20170816030403.11368-1-rodrigo.vivi@intel.com |
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2017-08-15 | Rodrigo Vivi | drm/i915/cnl: Setup PAT Index. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...patch/msgid/20170815232539.3562-1-rodrigo.vivi@intel.com |
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2017-08-11 | Rodrigo Vivi | drm/i915: Introduce intel_hpd_pin function. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...msgid/20170811182650.14327-2-rodrigo.vivi@intel.com |
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2017-08-11 | Rodrigo Vivi | drm/i915: Simplify hpd pin to port Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...msgid/20170811182650.14327-1-rodrigo.vivi@intel.com |
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2017-08-11 | Rodrigo Vivi | drm/i915/cnl: Dump the right pll registers when dumping... Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...msgid/20170810224525.18278-1-rodrigo.vivi@intel.com |
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2017-08-11 | Rodrigo Vivi | drm/i915/cnl: Add allowed DP rates for Cannonlake. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...msgid/20170810224008.15571-1-rodrigo.vivi@intel.com |
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2017-08-10 | Rodrigo Vivi | drm/i915/cnl: Add slice and subslice information to... Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...msgid/20170809200702.11236-1-rodrigo.vivi@intel.com |
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2017-08-10 | Rodrigo Vivi | drm/i915/cnl: Enable SAGV for Cannonlake. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...msgid/20170809205248.11917-2-rodrigo.vivi@intel.com |
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2017-08-10 | Rodrigo Vivi | drm/i915: Avoid null dereference if mst_port is unset. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...msgid/20170810145043.24047-1-rodrigo.vivi@intel.com |
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2017-08-08 | Rodrigo Vivi | drm/i915/cnl: Removing missing DDI_E bits from CNL. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...msgid/20170808193237.17410-1-rodrigo.vivi@intel.com |
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2017-08-03 | Rodrigo Vivi | drm/i915: Fix PCH names for KBP and CNP. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...patch/msgid/20170731185220.758-1-rodrigo.vivi@intel.com |
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2017-07-11 | Rodrigo Vivi | drm/i915/cnl: Add missing type case. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...msgid/20170710205852.28352-1-rodrigo.vivi@intel.com |
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2017-07-10 | Rodrigo Vivi | drm/i915/cnl: Add max allowed Cannonlake DC. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1499373908-26761-1-git-send-email-rodrigo.vivi@intel.com |
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2017-07-07 | Rodrigo Vivi | drm/i915/cnl: Get DDI clock based on PLLs. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1499374321-31152-1-git-send-email-rodrigo.vivi@intel.com |
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2017-07-07 | Rodrigo Vivi | drm/i915/cnl: Inherit RPS stuff from previous platforms. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1499373673-25066-1-git-send-email-rodrigo.vivi@intel.com |
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2017-07-07 | Rodrigo Vivi | drm/i915/cnl: Gen10 render context size. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1499375184-5725-1-git-send-email-rodrigo.vivi@intel.com |
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2017-07-07 | Rodrigo Vivi | drm/i915/cnl: Don't trust VBT's alternate pin for port... Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1499375295-6454-1-git-send-email-rodrigo.vivi@intel.com |
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2017-07-06 | Rodrigo Vivi | drm/i915/cnl: Cannonlake color init. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1499374873-2454-1-git-send-email-rodrigo.vivi@intel.com |
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2017-07-06 | Rodrigo Vivi | drm/i915/cnl: Add force wake for gen10+. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1499302831-17773-1-git-send-email-rodrigo.vivi@intel.com |
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2017-07-03 | Rodrigo Vivi | drm/i915/cfl: Fix Workarounds. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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2017-06-29 | Rodrigo Vivi | drm/i915/cfl: Fix Workarounds. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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2017-06-26 | Rodrigo Vivi | drm/i915/cnl: Fix RMW on ddi vswing sequence. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1497897572-22520-1-git-send-email-rodrigo.vivi@intel.com |
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2017-06-19 | Rodrigo Vivi | drm/i915/cnl: Fix RMW on ddi vswing sequence. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1497897572-22520-1-git-send-email-rodrigo.vivi@intel.com |
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2017-06-16 | Rodrigo Vivi | drm/i915/cfl: Introduce Coffee Lake workarounds. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1497653398-15722-1-git-send-email-rodrigo.vivi@intel.com |
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2017-06-15 | Rodrigo Vivi | Revert "drm/i915/skl: New ddb allocation algorithm" Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1497376350-3400-1-git-send-email-rodrigo.vivi@intel.com |
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2017-06-12 | Rodrigo Vivi | drm/i915/cfl: Basic DDI plumbing for Coffee Lake. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1497045770-21302-1-git-send-email-rodrigo.vivi@intel.com |
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2017-06-12 | Rodrigo Vivi | drm/i915/cnl: LSPCON support is gen9+ Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1497047175-27250-17-git-send-email-rodrigo.vivi@intel.com |
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2017-06-12 | Rodrigo Vivi | drm/i915/cnl: Enable fifo underrun for Cannonlake. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1497047175-27250-16-git-send-email-rodrigo.vivi@intel.com |
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2017-06-12 | Rodrigo Vivi | drm/i915/cnl: Fix Cannonlake scaler mode programing. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1497047175-27250-15-git-send-email-rodrigo.vivi@intel.com |
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2017-06-12 | Rodrigo Vivi | drm/i915: Use HAS_CSR instead of gen number on DMC... Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1497047175-27250-14-git-send-email-rodrigo.vivi@intel.com |
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2017-06-12 | Rodrigo Vivi | drm/i915/cnl: Implement voltage swing sequence. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1497047175-27250-11-git-send-email-rodrigo.vivi@intel.com |
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2017-06-12 | Rodrigo Vivi | drm/i915/cnl: Add DDI Buffer translation tables for... Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1497047175-27250-10-git-send-email-rodrigo.vivi@intel.com |
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2017-06-12 | Rodrigo Vivi | drm/i915/cnl: Add registers related to voltage swing... Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1497047175-27250-9-git-send-email-rodrigo.vivi@intel.com |
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2017-06-12 | Rodrigo Vivi | drm/i915: Add MMIO helper for 6 ports with different... Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1497047175-27250-8-git-send-email-rodrigo.vivi@intel.com Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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2017-06-12 | Rodrigo Vivi | drm/i915/cnl: Initialize PLLs Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1497047175-27250-7-git-send-email-rodrigo.vivi@intel.com |
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2017-06-12 | Rodrigo Vivi | drm/i915/cnl: DDI - PLL mapping Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1497047175-27250-5-git-send-email-rodrigo.vivi@intel.com |
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2017-06-12 | Rodrigo Vivi | drm/i915/cnl: Allow dynamic cdclk changes on CNL Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1497047175-27250-4-git-send-email-rodrigo.vivi@intel.com |
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2017-06-09 | Rodrigo Vivi | drm/i915/cfl: Coffee Lake reuses Kabylake DMC. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1497038550-30910-1-git-send-email-rodrigo.vivi@intel.com |
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2017-06-08 | Rodrigo Vivi | drm/i915/cfl: Introduce Display workarounds for Coffee... Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1496937000-8450-3-git-send-email-rodrigo.vivi@intel.com |
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2017-06-08 | Rodrigo Vivi | drm/i915/cfl: Coffee Lake uses CNP PCH. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1496937000-8450-2-git-send-email-rodrigo.vivi@intel.com |
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2017-06-08 | Rodrigo Vivi | drm/i915/cfl: Introduce Coffee Lake platform definition. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1496937000-8450-1-git-send-email-rodrigo.vivi@intel.com |
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2017-06-07 | Rodrigo Vivi | drm/i915: Unify GT* and GT3 definitions Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1496765166-7068-1-git-send-email-rodrigo.vivi@intel.com |
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2017-06-07 | Rodrigo Vivi | drm/i915: Remove unnecessary PORT3 definition. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1496700722-13755-1-git-send-email-rodrigo.vivi@intel.com |
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2017-06-07 | Rodrigo Vivi | drm/i915/cnl: Also need power well sanitize. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1496781040-20888-11-git-send-email-rodrigo.vivi@intel.com |
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2017-06-07 | Rodrigo Vivi | drm/i915/cnl: Cannonlake has same MOCS table than Skylake. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1496781040-20888-8-git-send-email-rodrigo.vivi@intel.com |
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2017-06-07 | Rodrigo Vivi | drm/i915/cnl: Configure EU slice power gating. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1496781040-20888-7-git-send-email-rodrigo.vivi@intel.com |
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2017-06-07 | Rodrigo Vivi | drm/i915/cnl: Add Cannonlake PCI IDs for Y-skus. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1496781040-20888-4-git-send-email-rodrigo.vivi@intel.com |
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2017-06-07 | Rodrigo Vivi | drm/i915/cnl: Add Cannonlake PCI IDs for U-skus. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1496781040-20888-3-git-send-email-rodrigo.vivi@intel.com |
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2017-06-07 | Rodrigo Vivi | drm/i915/cnl: Cannonlake uses CNP PCH. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1496781040-20888-2-git-send-email-rodrigo.vivi@intel.com |
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2017-06-07 | Rodrigo Vivi | drm/i915/cnl: Introduce Cannonlake platform defition. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1496781040-20888-1-git-send-email-rodrigo.vivi@intel.com |
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2017-06-02 | Rodrigo Vivi | drm/i915/cnp: Panel Power sequence changes for CNP... Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1496434004-29812-6-git-send-email-rodrigo.vivi@intel.com |
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2017-06-02 | Rodrigo Vivi | drm/i915/cnp: add CNP gmbus support Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1496434004-29812-5-git-send-email-rodrigo.vivi@intel.com |
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2017-06-02 | Rodrigo Vivi | drm/i915/cnp: Backlight support for CNP. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1496434004-29812-4-git-send-email-rodrigo.vivi@intel.com |
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2017-06-02 | Rodrigo Vivi | drm/i915/cnp: Get/set proper Raw clock frequency on... Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1496434004-29812-3-git-send-email-rodrigo.vivi@intel.com |
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2017-06-02 | Rodrigo Vivi | drm/i915/cnp: Introduce Cannonpoint PCH. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1496434004-29812-1-git-send-email-rodrigo.vivi@intel.com |
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2017-02-20 | Rodrigo Vivi | drm/i915: DMC 1.03 for Geminilake Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1487295515-15396-1-git-send-email-rodrigo.vivi@intel.com |
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2017-01-24 | Rodrigo Vivi | drm/i915: Introduce IS_GEN9_BC for Skylake and Kabylake. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1485196357-30599-2-git-send-email-rodrigo.vivi@intel.com |
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2017-01-24 | Rodrigo Vivi | drm/i915/kbl: Apply WaIncreaseDefaultTLBEntries on... Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1485196357-30599-1-git-send-email-rodrigo.vivi@intel.com |
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2017-01-10 | Rodrigo Vivi | drm/i915/glk: Add missing bits to allow runtime pm... Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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2017-01-03 | Rodrigo Vivi | drm/i915: Update SKL SRV GT4 pci ids reference. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1483471672-10450-1-git-send-email-rodrigo.vivi@intel.com |
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2016-12-20 | Rodrigo Vivi | drm/i915: Remove useless VLV_FEATURE Macro. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1482184508-18346-1-git-send-email-rodrigo.vivi@intel.com |
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2016-12-19 | Rodrigo Vivi | drm/i915: Simplify gem stolen initialization. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1482174347-24911-1-git-send-email-rodrigo.vivi@intel.com |
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2016-12-19 | Rodrigo Vivi | drm/i915: Rename get stolen functions for LP platforms... Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1482096988-400-2-git-send-email-rodrigo.vivi@intel.com |
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2016-12-19 | Rodrigo Vivi | drm/i915: Expand is_lp backwards to gen8_lp and gen7_lp. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1482096988-400-1-git-send-email-rodrigo.vivi@intel.com |
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2016-12-02 | Rodrigo Vivi | drm/i915: Only poll DW3_A when init DDI PHY for ports... Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1479410256-25735-1-git-send-email-rodrigo.vivi@intel.com |
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2016-12-01 | Rodrigo Vivi | drm/i915: Create a common GEN9_LP_FEATURE. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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2016-10-20 | Rodrigo Vivi | drm/i915: KBL - Recommended buffer translation programming... Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1476806256-13318-1-git-send-email-rodrigo.vivi@intel.com |
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2016-10-20 | Rodrigo Vivi | drm/i915: Move down skl/kbl ddi iboost and n_edp_entires... Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1475258757-29540-1-git-send-email-rodrigo.vivi@intel.com |
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2016-09-14 | Rodrigo Vivi | Revert "drm/i915/psr: Make idle_frames sensible again" Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1473295351-8766-1-git-send-email-rodrigo.vivi@intel.com |
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2016-09-13 | Rodrigo Vivi | Revert "drm/i915/psr: Make idle_frames sensible again" Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1473295351-8766-1-git-send-email-rodrigo.vivi@intel.com |
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2016-08-08 | Rodrigo Vivi | drm: Avoid printing negative values for unsigned variables. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1470243226-2750-1-git-send-email-rodrigo.vivi@intel.com |
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2016-08-05 | Rodrigo Vivi | drm/i915: Use drm official vblank_no_hw_counter callback. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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2016-08-05 | Rodrigo Vivi | drm/i915: Fix copy_to_user usage for pipe_crc Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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2016-07-25 | Rodrigo Vivi | drm/i915/guc: Revert "drm/i915/guc: enable GuC loading... Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1468884477-30086-1-git-send-email-rodrigo.vivi@intel.com |
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2016-07-19 | Rodrigo Vivi | drm/i915/guc: Revert "drm/i915/guc: enable GuC loading... Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1468884477-30086-1-git-send-email-rodrigo.vivi@intel.com |
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2016-07-18 | Rodrigo Vivi | drm/i915/kbl: Introduce the first official DMC for... Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1461707991-15336-1-git-send-email-rodrigo.vivi@intel.com |
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2016-07-15 | Rodrigo Vivi | drm/i915: Introduce Kabypoint PCH for Kabylake H/DT. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1467418032-15167-1-git-send-email-rodrigo.vivi@intel.com Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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2016-07-07 | Rodrigo Vivi | drm/i915: Introduce Kabypoint PCH for Kabylake H/DT. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1467418032-15167-1-git-send-email-rodrigo.vivi@intel.com Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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2016-06-29 | Rodrigo Vivi | drm/i915: Removing PCI IDs that are no longer listed... Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1466718636-19675-2-git-send-email-rodrigo.vivi@intel.com |
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2016-06-29 | Rodrigo Vivi | drm/i915: Add more Kabylake PCI IDs. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1466718636-19675-1-git-send-email-rodrigo.vivi@intel.com |
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2016-06-28 | Rodrigo Vivi | drm/i915: Removing PCI IDs that are no longer listed... Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1466718636-19675-2-git-send-email-rodrigo.vivi@intel.com |
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2016-06-28 | Rodrigo Vivi | drm/i915: Add more Kabylake PCI IDs. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1466718636-19675-1-git-send-email-rodrigo.vivi@intel.com |
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2016-05-05 | Rodrigo Vivi | drm/i915/kbl: Introduce the first official DMC for... Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1461707991-15336-1-git-send-email-rodrigo.vivi@intel.com |
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2016-03-30 | Rodrigo Vivi | drm/i915/kbl: Remove preliminary_hw_support protection... Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1459349881-951-1-git-send-email-rodrigo.vivi@intel.com |
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2016-02-17 | Rodrigo Vivi | drm/i915: Enable PSR by default on Haswell and Broadwell. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1455278893-1307-2-git-send-email-rodrigo.vivi@intel.com Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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2016-02-17 | Rodrigo Vivi | drm/i915: Enable PSR by default on Valleyview and Cherryview. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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2016-02-17 | Rodrigo Vivi | drm/i915: Change i915.enable_psr parameter to use per... Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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2016-02-01 | Rodrigo Vivi | drm/i915: Instrument PSR parameter for debuging with... Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1454356928-19779-1-git-send-email-rodrigo.vivi@intel.com |
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2016-02-01 | Rodrigo Vivi | drm/i915: Add PSR main link standby support back Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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2016-02-01 | Rodrigo Vivi | drm/i915: PSR simplify port and link standby checks. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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2016-01-29 | Rodrigo Vivi | drm/i915: Sink CRC: tune down error message at stop... Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1454107499-29678-1-git-send-email-rodrigo.vivi@intel.com |
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2016-01-08 | Rodrigo Vivi | drm/i915/kbl: Adding missing IS_KABYLAKE checks. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1452214179-22361-1-git-send-email-rodrigo.vivi@intel.com |
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