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2021-12-20	Kito Cheng	target/riscv: zfh: half-precision load and store Signed-off-by: Kito Cheng <kito.cheng@sifive.com>	commit \| commitdiff \| tree
2021-07-07	Kito Cheng	linux-user/elfload: Implement ELF_HWCAP for RISC-V Signed-off-by: Kito Cheng <kito.cheng@sifive.com>	commit \| commitdiff \| tree
2021-06-07	Kito Cheng	target/riscv: rvb: support and turn on B-extension... Signed-off-by: Kito Cheng <kito.cheng@sifive.com>	commit \| commitdiff \| tree
2021-06-07	Kito Cheng	target/riscv: rvb: add/shift with prefix zero-extend Signed-off-by: Kito Cheng <kito.cheng@sifive.com>	commit \| commitdiff \| tree
2021-06-07	Kito Cheng	target/riscv: rvb: address calculation Signed-off-by: Kito Cheng <kito.cheng@sifive.com>	commit \| commitdiff \| tree
2021-06-07	Kito Cheng	target/riscv: rvb: rotate (left/right) Signed-off-by: Kito Cheng <kito.cheng@sifive.com>	commit \| commitdiff \| tree
2021-06-07	Kito Cheng	target/riscv: rvb: shift ones Signed-off-by: Kito Cheng <kito.cheng@sifive.com>	commit \| commitdiff \| tree
2021-06-07	Kito Cheng	target/riscv: rvb: sign-extend instructions Signed-off-by: Kito Cheng <kito.cheng@sifive.com>	commit \| commitdiff \| tree
2021-06-07	Kito Cheng	target/riscv: rvb: min/max instructions Signed-off-by: Kito Cheng <kito.cheng@sifive.com>	commit \| commitdiff \| tree
2021-06-07	Kito Cheng	target/riscv: rvb: pack two words into one register Signed-off-by: Kito Cheng <kito.cheng@sifive.com>	commit \| commitdiff \| tree
2021-06-07	Kito Cheng	target/riscv: rvb: logic-with-negate Signed-off-by: Kito Cheng <kito.cheng@sifive.com>	commit \| commitdiff \| tree
2021-06-07	Kito Cheng	target/riscv: rvb: count leading/trailing zeros Signed-off-by: Kito Cheng <kito.cheng@sifive.com>	commit \| commitdiff \| tree
2021-06-07	Kito Cheng	target/riscv: reformat @sh format encoding for B-extension Signed-off-by: Kito Cheng <kito.cheng@sifive.com>	commit \| commitdiff \| tree
2021-05-15	Kito Cheng	linux-user: Add strace support for printing arguments... Signed-off-by: Kito Cheng <kito.cheng@sifive.com>	commit \| commitdiff \| tree
2021-01-18	Kito Cheng	riscv: Add semihosting support for user mode Signed-off-by: Kito Cheng <kito.cheng@sifive.com>	commit \| commitdiff \| tree
2020-08-28	Kito Cheng	softfloat: Implement the full set of comparisons for... Signed-off-by: Kito Cheng <kito.cheng@sifive.com>	commit \| commitdiff \| tree
2019-03-26	Kito Cheng	target/riscv: Fix wrong expanding for c.fswsp Signed-off-by: Kito Cheng <kito.cheng@gmail.com>	commit \| commitdiff \| tree
2019-03-25	Kito Cheng	hardfloat: fix float32/64 fused multiply-add Signed-off-by: Kito Cheng <kito.cheng@gmail.com>	commit \| commitdiff \| tree
2019-03-19	Kito Cheng	RISC-V: linux-user support for RVE ABI Co-authored-by: Kito Cheng <kito.cheng@gmail.com>	commit \| commitdiff \| tree

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