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| 2017-10-17 | Chris Wilson | drm/i915: Fix eviction when the GGTT is idle but full Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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| 2017-10-17 | Rodrigo Vivi | Merge tag 'gvt-fixes-2017-10-16' of https://github... Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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| 2017-10-11 | Jani Nikula | drm/i915/bios: parse DDI ports also for CHV for HDMI... Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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| 2017-10-09 | Ville Syrjälä | drm/i915: Read timings from the correct transcoder... Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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| 2017-10-09 | Chris Wilson | drm/i915: Order two completing nop_submit_request Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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| 2017-10-09 | Chris Wilson | drm/i915: Silence compiler warning for hsw_power_well_enable() Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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| 2017-10-09 | Maarten Lankhorst | drm/i915: Use crtc_state_is_legacy_gamma in intel_color_check Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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| 2017-10-09 | Manasi Navare | drm/i915/edp: Increase the T12 delay quirk to 1300ms Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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| 2017-10-09 | Manasi Navare | drm/i915/edp: Get the Panel Power Off timestamp after... Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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| 2017-10-04 | Imre Deak | drm/i915/glk: Fix DMC/DC state idleness calculation Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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| 2017-10-04 | Imre Deak | drm/i915/cnl: Reprogram DMC firmware after S3/S4 resume Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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| 2017-10-03 | Imre Deak | drm/i915: Fix DDI PHY init if it was already on Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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| 2017-09-26 | Jani Nikula | drm/i915/bios: ignore HDMI on port A Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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| 2017-09-26 | Colin Ian King | drm/i915: remove redundant variable hw_check Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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| 2017-09-26 | Jani Nikula | drm/i915: always update ELD connector type after get... Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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| 2017-09-18 | Chris Wilson | drm/i915: Remove unused 'in_vbl' from i915_get_crtc_scanoutpos() Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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| 2017-09-18 | Lee, Shawn C | drm/i915/cnp: set min brightness from VBT Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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| 2017-09-18 | Uma Shankar | Revert "drm/i915/bxt: Disable device ready before shutdown... Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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| 2017-09-18 | Lee, Shawn C | drm/i915/bxt: set min brightness from VBT Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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| 2017-09-18 | Christophe JAILLET | drm/i915: Fix an error handling in 'intel_framebuffer_init()' Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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| 2017-09-18 | Changbin Du | drm/i915/gvt: Fix incorrect PCI BARs reporting Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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| 2017-09-06 | Rodrigo Vivi | Merge tag 'gvt-fixes-2017-09-06' of https://github... Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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| 2017-09-06 | Chris Wilson | drm/i915: Re-enable GTT following a device reset Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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| 2017-09-06 | Ville Syrjälä | drm/i915: Annotate user relocs with __user Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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| 2017-09-05 | Chris Wilson | drm/i915: Silence sparse by using gfp_t Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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| 2017-09-05 | Ville Syrjälä | drm/i915: Add __rcu to radix tree slot pointer Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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| 2017-09-05 | Zhi Wang | drm/i915: Fix the missing PPAT cache attributes on CNL Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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| 2017-09-01 | Ville Syrjälä | drm/i915: Fix enum pipe vs. enum transcoder for the... Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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| 2017-09-01 | Ville Syrjälä | drm/i915: Make i2c lock ops static Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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| 2017-09-01 | Ville Syrjälä | drm/i915: Make i9xx_load_ycbcr_conversion_matrix()... Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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| 2017-09-01 | Manasi Navare | drm/i915/edp: Increase T12 panel delay to 900 ms to... Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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| 2017-08-30 | Chris Wilson | drm/i915: Ignore duplicate VMA stored within the per... Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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| 2017-08-30 | Ville Syrjälä | drm/i915: Skip fence alignemnt check for the CCS plane Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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| 2017-08-30 | Ville Syrjälä | drm/i915: Treat fb->offsets[] as a raw byte offset... Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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| 2017-08-30 | Chris Wilson | drm/i915: Always wake the device to flush the GTT Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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| 2017-08-30 | Chris Wilson | drm/i915: Recreate vmapping even when the object is... Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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| 2017-08-30 | Chris Wilson | drm/i915: Quietly cancel FBC activation if CRTC is... Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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| 2017-08-16 | Rodrigo Vivi | drm/i915/cnl: Reuse skl_wm_get_hw_state on Cannonlake. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...msgid/20170809205248.11917-6-rodrigo.vivi@intel.com |
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| 2017-08-16 | Paulo Zanoni | drm/i915/gen10: implement gen 10 watermarks calculations Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...msgid/20170811233825.32083-1-rodrigo.vivi@intel.com |
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| 2017-08-16 | Rodrigo Vivi | drm/i915/cnl: Fix LSPCON support. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...msgid/20170816030403.11368-1-rodrigo.vivi@intel.com |
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| 2017-08-15 | Rodrigo Vivi | drm/i915/cnl: Setup PAT Index. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...patch/msgid/20170815232539.3562-1-rodrigo.vivi@intel.com |
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| 2017-08-15 | Jim Bride | drm/i915/edp: Allow alternate fixed mode for eDP if... Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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| 2017-08-11 | Rodrigo Vivi | drm/i915: Introduce intel_hpd_pin function. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...msgid/20170811182650.14327-2-rodrigo.vivi@intel.com |
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| 2017-08-11 | Rodrigo Vivi | drm/i915: Simplify hpd pin to port Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...msgid/20170811182650.14327-1-rodrigo.vivi@intel.com |
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| 2017-08-11 | Rodrigo Vivi | drm/i915/cnl: Dump the right pll registers when dumping... Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...msgid/20170810224525.18278-1-rodrigo.vivi@intel.com |
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| 2017-08-11 | Rodrigo Vivi | drm/i915/cnl: Add allowed DP rates for Cannonlake. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...msgid/20170810224008.15571-1-rodrigo.vivi@intel.com |
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| 2017-08-11 | Matthias Kaehlcke | drm/i915: Return correct EDP voltage swing table for... Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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| 2017-08-10 | Rodrigo Vivi | drm/i915/cnl: Add slice and subslice information to... Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...msgid/20170809200702.11236-1-rodrigo.vivi@intel.com |
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| 2017-08-10 | Paulo Zanoni | drm/i915/gen10: fix WM latency printing Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...msgid/20170809205248.11917-4-rodrigo.vivi@intel.com |
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| 2017-08-10 | Paulo Zanoni | drm/i915/gen10: fix the gen 10 SAGV block time Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...msgid/20170809205248.11917-3-rodrigo.vivi@intel.com |
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| 2017-08-10 | Rodrigo Vivi | drm/i915/cnl: Enable SAGV for Cannonlake. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...msgid/20170809205248.11917-2-rodrigo.vivi@intel.com |
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| 2017-08-10 | Paulo Zanoni | drm/i915/gen10+: use the SKL code for reading WM latencies Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...msgid/20170809205248.11917-1-rodrigo.vivi@intel.com |
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| 2017-08-10 | Rodrigo Vivi | drm/i915: Avoid null dereference if mst_port is unset. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...msgid/20170810145043.24047-1-rodrigo.vivi@intel.com |
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| 2017-08-09 | Jim Bride | drm/i915/psr: Preserve SRD_CTL bit 29 on PSR init Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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| 2017-08-08 | Rodrigo Vivi | drm/i915/cnl: Removing missing DDI_E bits from CNL. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...msgid/20170808193237.17410-1-rodrigo.vivi@intel.com |
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| 2017-08-03 | Praveen Paneri | drm/i915: enable WaDisableDopClkGating for skl Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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| 2017-08-03 | Rodrigo Vivi | drm/i915: Fix PCH names for KBP and CNP. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...patch/msgid/20170731185220.758-1-rodrigo.vivi@intel.com |
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| 2017-07-11 | Rodrigo Vivi | drm/i915/cnl: Add missing type case. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...msgid/20170710205852.28352-1-rodrigo.vivi@intel.com |
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| 2017-07-10 | Rodrigo Vivi | drm/i915/cnl: Add max allowed Cannonlake DC. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1499373908-26761-1-git-send-email-rodrigo.vivi@intel.com |
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| 2017-07-07 | Rodrigo Vivi | drm/i915/cnl: Get DDI clock based on PLLs. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1499374321-31152-1-git-send-email-rodrigo.vivi@intel.com |
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| 2017-07-07 | Rodrigo Vivi | drm/i915/cnl: Inherit RPS stuff from previous platforms. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1499373673-25066-1-git-send-email-rodrigo.vivi@intel.com |
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| 2017-07-07 | Rodrigo Vivi | drm/i915/cnl: Gen10 render context size. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1499375184-5725-1-git-send-email-rodrigo.vivi@intel.com |
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| 2017-07-07 | Rodrigo Vivi | drm/i915/cnl: Don't trust VBT's alternate pin for port... Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1499375295-6454-1-git-send-email-rodrigo.vivi@intel.com |
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| 2017-07-06 | Rodrigo Vivi | drm/i915/cnl: Cannonlake color init. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1499374873-2454-1-git-send-email-rodrigo.vivi@intel.com |
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| 2017-07-06 | Rodrigo Vivi | drm/i915/cnl: Add force wake for gen10+. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1499302831-17773-1-git-send-email-rodrigo.vivi@intel.com |
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| 2017-07-06 | Paulo Zanoni | x86/gpu: CNL uses the same GMS values as SKL Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1499302845-17856-1-git-send-email-rodrigo.vivi@intel.com |
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| 2017-06-30 | Navare, Manasi D | drm/i915/cnl: Fix the CURSOR_COEFF_MASK used in DDI... Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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| 2017-06-29 | Rodrigo Vivi | drm/i915/cfl: Fix Workarounds. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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| 2017-06-19 | Rodrigo Vivi | drm/i915/cnl: Fix RMW on ddi vswing sequence. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1497897572-22520-1-git-send-email-rodrigo.vivi@intel.com |
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| 2017-06-16 | Rodrigo Vivi | drm/i915/cfl: Introduce Coffee Lake workarounds. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1497653398-15722-1-git-send-email-rodrigo.vivi@intel.com |
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| 2017-06-15 | Rodrigo Vivi | Revert "drm/i915/skl: New ddb allocation algorithm" Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1497376350-3400-1-git-send-email-rodrigo.vivi@intel.com |
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| 2017-06-12 | Rodrigo Vivi | drm/i915/cfl: Basic DDI plumbing for Coffee Lake. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1497045770-21302-1-git-send-email-rodrigo.vivi@intel.com |
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| 2017-06-12 | Kahola, Mika | drm/i915/cnl: Enable wrpll computation for CNL Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1497047175-27250-18-git-send-email-rodrigo.vivi@intel.com |
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| 2017-06-12 | Rodrigo Vivi | drm/i915/cnl: LSPCON support is gen9+ Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1497047175-27250-17-git-send-email-rodrigo.vivi@intel.com |
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| 2017-06-12 | Rodrigo Vivi | drm/i915/cnl: Enable fifo underrun for Cannonlake. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1497047175-27250-16-git-send-email-rodrigo.vivi@intel.com |
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| 2017-06-12 | Rodrigo Vivi | drm/i915/cnl: Fix Cannonlake scaler mode programing. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1497047175-27250-15-git-send-email-rodrigo.vivi@intel.com |
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| 2017-06-12 | Rodrigo Vivi | drm/i915: Use HAS_CSR instead of gen number on DMC... Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1497047175-27250-14-git-send-email-rodrigo.vivi@intel.com |
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| 2017-06-12 | Anusha Srivatsa | drm/i915/DMC/CNL: Load DMC on CNL Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1497047175-27250-13-git-send-email-rodrigo.vivi@intel.com |
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| 2017-06-12 | Clint Taylor | drm/i915/cnl: Enable loadgen_select bit for vswing... Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1497047175-27250-12-git-send-email-rodrigo.vivi@intel.com |
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| 2017-06-12 | Rodrigo Vivi | drm/i915/cnl: Implement voltage swing sequence. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1497047175-27250-11-git-send-email-rodrigo.vivi@intel.com |
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| 2017-06-12 | Rodrigo Vivi | drm/i915/cnl: Add DDI Buffer translation tables for... Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1497047175-27250-10-git-send-email-rodrigo.vivi@intel.com |
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| 2017-06-12 | Rodrigo Vivi | drm/i915/cnl: Add registers related to voltage swing... Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1497047175-27250-9-git-send-email-rodrigo.vivi@intel.com |
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| 2017-06-12 | Rodrigo Vivi | drm/i915: Add MMIO helper for 6 ports with different... Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1497047175-27250-8-git-send-email-rodrigo.vivi@intel.com Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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| 2017-06-12 | Rodrigo Vivi | drm/i915/cnl: Initialize PLLs Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1497047175-27250-7-git-send-email-rodrigo.vivi@intel.com |
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| 2017-06-12 | Kahola, Mika | drm/i915: Configure DPLL's for Cannonlake Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1497047175-27250-6-git-send-email-rodrigo.vivi@intel.com |
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| 2017-06-12 | Rodrigo Vivi | drm/i915/cnl: DDI - PLL mapping Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1497047175-27250-5-git-send-email-rodrigo.vivi@intel.com |
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| 2017-06-12 | Rodrigo Vivi | drm/i915/cnl: Allow dynamic cdclk changes on CNL Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1497047175-27250-4-git-send-email-rodrigo.vivi@intel.com |
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| 2017-06-12 | Ville Syrjälä | drm/i915/cnl: Implement CNL display init/unit sequence Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1497047175-27250-3-git-send-email-rodrigo.vivi@intel.com |
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| 2017-06-12 | Ville Syrjälä | drm/i915/cnl: Implement .set_cdclk() for CNL Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1497047175-27250-2-git-send-email-rodrigo.vivi@intel.com |
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| 2017-06-12 | Ville Syrjälä | drm/i915/cnl: Implement .get_display_clock_speed()... Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1497047175-27250-1-git-send-email-rodrigo.vivi@intel.com |
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| 2017-06-09 | Rodrigo Vivi | drm/i915/cfl: Coffee Lake reuses Kabylake DMC. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1497038550-30910-1-git-send-email-rodrigo.vivi@intel.com |
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| 2017-06-09 | Anusha Srivatsa | drm/i915/huc: Load HuC on Coffee Lake Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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| 2017-06-09 | Anusha Srivatsa | drm/i915/guc: Load GuC on Coffee Lake Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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| 2017-06-09 | Anusha Srivatsa | drm/i915/cfl: Add Coffee Lake PCI IDs for U Sku. Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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| 2017-06-09 | Anusha Srivatsa | drm/i915/cfl: Add Coffee Lake PCI IDs for H Sku. Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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| 2017-06-09 | Anusha Srivatsa | drm/i915/cfl: Add Coffee Lake PCI IDs for S Skus. Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
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| 2017-06-08 | Rodrigo Vivi | drm/i915/cfl: Introduce Display workarounds for Coffee... Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1496937000-8450-3-git-send-email-rodrigo.vivi@intel.com |
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| 2017-06-08 | Rodrigo Vivi | drm/i915/cfl: Coffee Lake uses CNP PCH. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1496937000-8450-2-git-send-email-rodrigo.vivi@intel.com |
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| 2017-06-08 | Rodrigo Vivi | drm/i915/cfl: Introduce Coffee Lake platform definition. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1496937000-8450-1-git-send-email-rodrigo.vivi@intel.com |
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| 2017-06-07 | Rodrigo Vivi | drm/i915: Unify GT* and GT3 definitions Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> ...1496765166-7068-1-git-send-email-rodrigo.vivi@intel.com |
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