projects / mirror_qemu.git / search
| 2023-07-10 | Bin Meng | roms/opensbi: Upgrade from v1.2 to v1.3 Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-07-10 | Weiwei Li | target/riscv: update cur_pmbase/pmmask based on mode... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-07-10 | Weiwei Li | target/riscv: Add additional xlen for address when... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-07-10 | Daniel Henrique... | target/riscv/cpu.c: fix veyron-v1 CPU properties Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-07-10 | Weiwei Li | target/riscv: Remove redundant assignment to SXL Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-07-10 | Weiwei Li | target/riscv: Support MSTATUS.MPV/GVA only when RVH... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-07-10 | Weiwei Li | target/riscv: Make MPV only work when MPP != PRV_M Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-07-10 | Christoph Müllner | disas/riscv: Add support for XThead* instructions Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-07-10 | Christoph Müllner | disas/riscv: Add support for XVentanaCondOps Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-07-10 | Christoph Müllner | disas/riscv: Provide infrastructure for vendor extensions Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-07-10 | Christoph Müllner | disas/riscv: Encapsulate opcode_data into decode Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-07-10 | Christoph Müllner | disas/riscv: Make rv_op_illegal a shared enum value Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-07-10 | Christoph Müllner | disas/riscv: Move types/constants to new header file Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-07-10 | Christoph Müllner | target/riscv: Factor out extension tests to cpu_cfg.h Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-07-10 | LIU Zhiwei | target/riscv: Use xl instead of mxl for disassemble Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-06-14 | Tommy Wu | hw/intc: If mmsiaddrcfgh.L == 1, smsiaddrcfg and smsiaddrcfg... Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-06-13 | Himanshu Chauhan | target/riscv: Smepmp: Return error when access permission... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-06-13 | Xiao Wang | target/riscv/vector_helper.c: Remove the check for... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-06-13 | Xiao Wang | target/riscv/vector_helper.c: clean up reference of... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-06-13 | Weiwei Li | target/riscv: Fix initialized value for cur_pmmask Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-06-13 | Ivan Klokov | util/log: Add vector registers to log Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-06-13 | Sunil V L | docs/system: riscv: Add pflash usage details Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-06-13 | Sunil V L | riscv/virt: Support using pflash via -blockdev option Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-06-13 | Sunil V L | hw/riscv: virt: Assume M-mode FW in pflash0 only when... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-06-13 | Weiwei Li | target/riscv: Remove pc_succ_insn from DisasContext Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-06-13 | Weiwei Li | target/riscv: Enable PC-relative translation Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-06-13 | Weiwei Li | target/riscv: Use true diff for gen_pc_plus_diff Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-06-13 | Weiwei Li | target/riscv: Change gen_set_pc_imm to gen_update_pc Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-06-13 | Weiwei Li | target/riscv: Change gen_goto_tb to work on displacements Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-06-13 | Weiwei Li | target/riscv: Introduce cur_insn_len into DisasContext Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-06-13 | Weiwei Li | target/riscv: Fix target address to update badaddr Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-06-13 | Weiwei Li | disas/riscv.c: Remove redundant parentheses Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-06-13 | Weiwei Li | disas/riscv.c: Fix lines with over 80 characters Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-06-13 | Weiwei Li | disas/riscv.c: Remove unused decomp_rv32/64 value for... Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-06-13 | Weiwei Li | disas/riscv.c: Support disas for Z*inx extensions Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-06-13 | Weiwei Li | disas/riscv.c: Support disas for Zcm* extensions Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-06-13 | Weiwei Li | target/riscv: Pass RISCVCPUConfig as target_info to... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-06-13 | Weiwei Li | target/riscv: Split RISCVCPUConfig declarations from... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-06-13 | Weiwei Li | disas: Change type of disassemble_info.target_info... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-06-13 | Mayuresh Chitale | target/riscv: smstateen knobs Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-06-13 | Mayuresh Chitale | target/riscv: Reuse tb->flags.FS Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-06-13 | Mayuresh Chitale | target/riscv: smstateen check for fcsr Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-06-13 | Weiwei Li | target/riscv: Update cur_pmmask/base when xl changes Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-06-13 | Weiwei Li | target/riscv: Fix pointer mask transformation for vector... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-06-13 | Yin Wang | hw/riscv: qemu crash when NUMA nodes exceed available... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-06-13 | Philippe Mathieu... | hw/riscv/opentitan: Correct OpenTitanState parent type... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-06-13 | Philippe Mathieu... | hw/riscv/opentitan: Explicit machine type definition Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-06-13 | Philippe Mathieu... | hw/riscv/opentitan: Add TYPE_OPENTITAN_MACHINE definition Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-06-13 | Philippe Mathieu... | hw/riscv/opentitan: Declare QOM types using DEFINE_TYPES... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-06-13 | Philippe Mathieu... | hw/riscv/opentitan: Rename machine_[class]_init() functions Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-06-13 | Weiwei Li | target/riscv: Deny access if access is partially inside... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-06-13 | Weiwei Li | target/riscv: Separate pmp_update_rule() in pmpcfg_csr_write Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-06-13 | Weiwei Li | target/riscv: Flush TLB only when pmpcfg/pmpaddr really... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-06-13 | Weiwei Li | target/riscv: Flush TLB when pmpaddr is updated Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-06-13 | Weiwei Li | target/riscv: Update the next rule addr in pmpaddr_csr_write() Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-06-13 | Weiwei Li | target/riscv: Flush TLB when MMWP or MML bits are changed Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-06-13 | Weiwei Li | target/riscv: Remove unused paramters in pmp_hart_has_privs_... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-06-13 | Weiwei Li | target/riscv: Make RLB/MML/MMWP bits writable only... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-06-13 | Weiwei Li | target/riscv: Change the return type of pmp_hart_has_privs... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-06-13 | Weiwei Li | target/riscv: Make the short cut really work in pmp_hart_has... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-06-13 | Weiwei Li | target/riscv: Move pmp_get_tlb_size apart from get_physical_... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-06-13 | Weiwei Li | target/riscv: Update pmp_get_tlb_size() Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-06-13 | Daniel Henrique... | target/riscv: rework write_misa() Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-06-13 | Daniel Henrique... | target/riscv/cpu.c: remove cfg setup from riscv_cpu_init() Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-06-13 | Daniel Henrique... | target/riscv/cpu.c: validate extensions before riscv_timer_i... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-06-13 | Daniel Henrique... | target/riscv/cpu.c: add riscv_cpu_validate_misa_mxl() Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-06-13 | Daniel Henrique... | target/riscv/cpu.c: add priv_spec validate/disable_exts... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-06-13 | Weiwei Li | target/riscv: Update check for Zca/Zcf/Zcd Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-06-13 | Weiwei Li | target/riscv: Mask the implicitly enabled extensions... Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-06-13 | Daniel Henrique... | target/riscv: add PRIV_VERSION_LATEST Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-06-13 | Daniel Henrique... | target/riscv/cpu.c: remove set_priv_version() Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-06-13 | Daniel Henrique... | target/riscv/cpu.c: remove set_vext_version() Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-06-13 | Daniel Henrique... | target/riscv/cpu.c: add riscv_cpu_validate_v() Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-06-13 | Weiwei Li | target/riscv: Move zc* out of the experimental properties Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-06-13 | Daniel Henrique... | target/riscv/vector_helper.c: skip set tail when vta... Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-05-05 | Rahul Pathak | target/riscv: add Ventana's Veyron V1 CPU Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-05-05 | Alexandre Ghiti | riscv: Make sure an exception is raised if a pte is... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-05-05 | Irina Ryapolova | target/riscv: Fix Guest Physical Address Translation Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-05-05 | Bin Meng | target/riscv: Restore the predicate() NULL check behavior Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-05-05 | Daniel Henrique... | target/riscv: add TYPE_RISCV_DYNAMIC_CPU Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-05-05 | Daniel Henrique... | target/riscv: add query-cpy-definitions support Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-05-05 | Daniel Henrique... | target/riscv: add CPU QOM header Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-05-05 | Ivan Klokov | hw/intc/riscv_aplic: Zero init APLIC internal state Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-05-05 | Richard Henderson | target/riscv: Reorg sum check in get_physical_address Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-05-05 | Richard Henderson | target/riscv: Reorg access check in get_physical_address Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-05-05 | Richard Henderson | target/riscv: Merge checks for reserved pte flags Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-05-05 | Richard Henderson | target/riscv: Don't modify SUM with is_debug Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-05-05 | Richard Henderson | target/riscv: Suppress pte update with is_debug Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-05-05 | Richard Henderson | target/riscv: Move leaf pte processing out of level... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-05-05 | Richard Henderson | target/riscv: Hoist pbmte and hade out of the level... Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-05-05 | Richard Henderson | target/riscv: Hoist second stage mode change to callers Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-05-05 | Richard Henderson | target/riscv: Check SUM in the correct register Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-05-05 | Richard Henderson | target/riscv: Set MMU_2STAGE_BIT in riscv_cpu_mmu_index Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-05-05 | Richard Henderson | target/riscv: Move hstatus.spvp check to check_access_hlsv Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-05-05 | Richard Henderson | target/riscv: Introduce mmuidx_2stage Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-05-05 | Richard Henderson | target/riscv: Introduce mmuidx_priv Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-05-05 | Richard Henderson | target/riscv: Introduce mmuidx_sum Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-05-05 | Richard Henderson | target/riscv: Rename MMU_HYP_ACCESS_BIT to MMU_2STAGE_BIT Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-05-05 | Richard Henderson | target/riscv: Handle HLV, HSV via helpers Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| 2023-05-05 | Richard Henderson | target/riscv: Use cpu_ld*_code_mmu for HLVX Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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