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target/arm: Update ISAR fields for ARMv8.8
2022-04-22 Richard Hendersontarget/arm: Update ISAR fields for ARMv8.8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-22 Peter Maydellhw/arm/virt: Support TCG GICv4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-22 Peter Maydellhw/arm/virt: Abstract out calculation of redistributor...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-22 Peter Maydellhw/arm/virt: Use VIRT_GIC_VERSION_* enum values in...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-22 Peter Maydellhw/intc/arm_gicv3: Allow 'revision' property to be...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-22 Peter Maydellhw/intc/arm_gicv3: Update ID and feature registers...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-22 Peter Maydellhw/intc/arm_gicv3_redist: Implement gicv3_redist_inv_vlpi()
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-22 Peter Maydellhw/intc/arm_gicv3_redist: Implement gicv3_redist_vinvall()
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-22 Peter Maydellhw/intc/arm_gicv3_redist: Implement gicv3_redist_mov_vlpi()
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-22 Peter Maydellhw/intc/arm_gicv3_redist: Use set_pending_table_bit...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-22 Peter Maydellhw/intc/arm_gicv3_redist: Implement gicv3_redist_vlpi_pending()
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-22 Peter Maydellhw/intc/arm_gicv3_redist: Implement gicv3_redist_process_vlpi()
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-22 Peter Maydellhw/intc/arm_gicv3_redist: Factor out "update bit in...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-22 Peter Maydellhw/intc/arm_gicv3_redist: Recalculate hppvlpi on VPENDBASER...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-22 Peter Maydellhw/intc/arm_gicv3_redist: Factor out "update hpplpi...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-22 Peter Maydellhw/intc/arm_gicv3_redist: Factor out "update hpplpi...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-22 Peter Maydellhw/intc/arm_gicv3_cpuif: Don't recalculate maintenance...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-22 Peter Maydellhw/intc/arm_gicv3_cpuif: Support vLPIs
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-22 Peter Maydellhw/intc/arm_gicv3_cpuif: Split "update vIRQ/vFIQ" from...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-22 Peter Maydellhw/intc/arm_gicv3: Implement new GICv4 redistributor...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-22 Peter Maydellhw/intc/arm_gicv3: Implement GICv4's new redistributor...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-22 Peter Maydellhw/intc/arm_gicv3_its: Implement VINVALL
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-22 Peter Maydellhw/intc/arm_gicv3_its: Implement VMOVI
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-22 Peter Maydellhw/intc/arm_gicv3_its: Implement INV for virtual interrupts
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-22 Peter Maydellhw/intc/arm_gicv3_its: Implement INV command properly
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-22 Peter Maydellhw/intc/arm_gicv3_its: Implement VSYNC
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-22 Peter Maydellhw/intc/arm_gicv3_its: Implement VMOVP
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-22 Peter Maydellhw/intc/arm_gicv3: Keep pointers to every connected ITS
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-22 Peter Maydellhw/intc/arm_gicv3_its: Handle virtual interrupts in...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-22 Peter Maydellhw/intc/arm_gicv3_its: Split out process_its_cmd()...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-22 Peter Maydellhw/intc/arm_gicv3_its: Factor out CTE lookup sequence
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-22 Peter Maydellhw/intc/arm_gicv3_its: Factor out "find ITE given devid...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-22 Peter Maydellhw/intc/arm_gicv3_its: Distinguish success and error...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-22 Peter Maydellhw/intc/arm_gicv3_its: Implement VMAPP
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-22 Peter Maydellhw/intc/arm_gicv3_its: Implement VMAPI and VMAPTI
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-22 Peter Maydellhw/intc/arm_gicv3_its: Implement GITS_BASER2 for GICv4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-22 Peter Maydellhw/intc/arm_gicv3_its: Factor out "is intid a valid...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-22 Peter Maydelltarget/arm/cpu.c: ignore VIRQ and VFIQ if no EL2
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-22 Peter Maydellhw/intc/arm_gicv3: Report correct PIDR0 values for...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-22 Peter Maydellhw/intc/arm_gicv3: Insist that redist region capacity...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-22 Peter Maydellhw/intc/arm_gicv3: Sanity-check num-cpu property
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-22 Peter Maydellhw/intc/arm_gicv3_its: Add missing blank line
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-21 Hao Wuhw/arm: Use bit fields for NPCM7XX PWRON STRAPs
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-21 Hao Wuhw/misc: Add PWRON STRAP bit fields in GCR module
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-21 Heinrich Schuchardthw/arm/virt: impact of gic-version on max CPUs
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-21 Zongyuan Lihw/core/irq: remove unused 'qemu_irq_split' function
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-21 Zongyuan Lihw/arm/stellaris: replace 'qemu_split_irq' with 'TYPE_SPLIT_IRQ'
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-21 Zongyuan Lihw/arm/realview: replace 'qemu_split_irq' with 'TYPE_SPLIT_IRQ'
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-21 Peter Maydellhw/arm/exynos4210: Drop Exynos4210Irq struct
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-21 Peter Maydellhw/arm/exynos4210: Put combiners into state struct
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-21 Peter Maydellhw/arm/exynos4210: Fold combiner splits into exynos4210_init...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-21 Peter Maydellhw/arm/exynos4210: Don't connect multiple lines to...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-21 Peter Maydellhw/arm/exynos4210: Connect MCT_G0 and MCT_G1 to both...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-21 Peter Maydellhw/arm/exynos4210: Fill in irq_table[] for internal...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-21 Peter Maydellhw/arm/exynos4210: Use TYPE_SPLIT_IRQ in exynos4210_init_boa...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-21 Peter Maydellhw/arm/exynos4210: Delete unused macro definitions
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-21 Peter Maydellhw/arm/exynos4210: Move exynos4210_combiner_get_gpioin...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-21 Peter Maydellhw/arm/exynos4210: Drop ext_gic_irq[] from Exynos4210Irq...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-21 Peter Maydellhw/arm/exynos4210: Put external GIC into state struct
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-21 Peter Maydellhw/arm/exynos4210: Move exynos4210_init_board_irqs...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-21 Peter Maydellhw/arm/exynos4210: Fix code style nit in combiner_grp_to_gic...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-21 Peter Maydellhw/arm/exynos4210: Coalesce board_irqs and irq_table
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-21 Peter Maydellhw/arm/exynos4210: Drop int_gic_irq[] from Exynos4210Irq...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-21 Peter Maydellhw/arm/exynos4210: Put a9mpcore device into state struct
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-21 Peter Maydellhw/intc/exynos4210_gic: Remove unused TYPE_EXYNOS4210_IRQ_GATE
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-21 Peter Maydellhw/arm/exynos4210: Use TYPE_OR_IRQ instead of custom...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-21 Edgar E. Iglesiashw/arm: versal: Connect the CRL
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-21 Edgar E. Iglesiashw/misc: Add a model of the Xilinx Versal CRL
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-21 Edgar E. Iglesiashw/arm: versal: Add the Cortex-R5Fs
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-21 Edgar E. Iglesiashw/arm: versal: Create an APU CPU Cluster
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-21 Edgar E. Iglesiashw/arm/xlnx-zynqmp: Connect 4 TTC timers
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-21 Edgar E. Iglesiastimer: cadence_ttc: Break out header file to allow...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-21 Peter Maydellhw/arm/virt: Check for attempt to use TrustZone with...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-19 Peter MaydellUpdate version for v7.0.0 release
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-12 Peter MaydellUpdate version for v7.0.0-rc4 release
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-08 Wentao Liangvirtio-iommu: use-after-free fix
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-08 Peter MaydellMerge tag 'fixes-20220408-pull-request' of git://git...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-06 Peter MaydellUpdate version for v7.0.0-rc3 release
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-06 Dr. David Alan Gilbertacpi: fix acpi_index migration
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-05 Peter MaydellMerge tag 'for-upstream' of https://gitlab.com/bonzini...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-05 Peter MaydellMerge tag 'pull-qapi-2022-04-05' of git://repo.or.cz...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-05 Peter MaydellMerge tag 'pull-target-arm-20220405' of https://git...
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-05 Pavel Pisadocs/system/devices/can.rst: correct links to CTU CAN...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-05 Tong Hoxlnx-bbram: hw/nvram: Fix uninitialized Error *
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-04 Peter MaydellMerge tag 'pull-ppc-20220404' of https://github.com...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-02 Peter MaydellMerge tag 'pull-request-2022-04-01' of https://gitlab...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-01 Peter MaydellMerge tag 'pull-target-arm-20220401' of https://git...
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-01 Peter MaydellMerge tag 'pull-riscv-to-apply-20220401' of github...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-01 Peter Maydelltarget/arm: Don't use DISAS_NORETURN in STXP !HAVE_CMPXCHG12...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-01 Frederic KonradMAINTAINERS: change Fred Konrad's email address
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-01 Idan Horowitztarget/arm: Determine final stage 2 output PA space...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-01 Idan Horowitztarget/arm: Take VSTCR.SW, VTCR.NSW into account in...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-01 Idan Horowitztarget/arm: Check VSTCR.SW when assigning the stage...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-01 Idan Horowitztarget/arm: Fix MTE access checks for disabled SEL2
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-04-01 Peter MaydellMerge tag 'trivial-branch-for-7.0-pull-request' of...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-03-31 Peter MaydellMerge tag 'pull-tcg-20220331' of https://gitlab.com...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-03-31 Peter MaydellMerge tag 'pull-qapi-2022-03-31' of git://repo.or.cz...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-03-29 Peter MaydellUpdate version for v7.0.0-rc2 release
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-03-29 Peter MaydellMerge tag 'for-upstream' of https://gitlab.com/bonzini...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2022-03-29 Peter MaydellMerge tag 'pull-block-2022-03-29' of https://gitlab...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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