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2021-10-21	Frank Chang	target/riscv: Pass the same value to oprsz and maxsz... Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-10-06	Frank Chang	target/riscv: Set mstatus_hs.[SD\|FS] bits if Clean... Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-09-21	Frank Chang	target/riscv: Backup/restore mstatus.SD bit when virtual... Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-09-20	Frank Chang	hw/dma: sifive_pdma: don't set Control.error if 0 bytes... Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-09-20	Frank Chang	hw/dma: sifive_pdma: claim bit must be set before DMA... Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-09-20	Frank Chang	hw/dma: sifive_pdma: reset Next* registers when Control... Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-06-07	Frank Chang	target/riscv: rvb: add b-ext version cpu option Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-06-07	Frank Chang	target/riscv: rvb: generalized or-combine Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-06-07	Frank Chang	target/riscv: rvb: generalized reverse Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-06-07	Frank Chang	target/riscv: rvb: single-bit instructions Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-06-07	Frank Chang	target/riscv: add gen_shifti() and gen_shiftiw() helper... Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-06-07	Frank Chang	target/riscv: rvb: count bits set Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-05-11	Frank Chang	fpu/softfloat: set invalid excp flag for RISC-V muladd... Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-05-11	Frank Chang	target/riscv: fix vrgather macro index variable type bug Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2021-03-23	Frank Chang	target/riscv: fix vs() to return proper error code Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2020-08-28	Frank Chang	softfloat: Add fp16 and uint8/int8 conversion functions Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2020-07-14	Frank Chang	target/riscv: fix vill bit index in vtype register Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2020-07-14	Frank Chang	target/riscv: fix return value of do_opivx_widen() Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2020-07-14	Frank Chang	target/riscv: correct the gvec IR called in gen_vec_rsub16_i64() Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree
2020-07-14	Frank Chang	target/riscv: fix rsub gvec tcg_assert_listed_vecop... Signed-off-by: Frank Chang <frank.chang@sifive.com>	commit \| commitdiff \| tree

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