projects / mirror_qemu.git / search
| 2020-03-17 | Bin Meng | gitlab-ci.yml: Add jobs to build OpenSBI firmware binaries Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-03-17 | Bin Meng | riscv: sifive_u: Update BIOS_FILENAME for 32-bit Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-03-17 | Bin Meng | roms: opensbi: Add 32-bit firmware image for sifive_u... Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-03-17 | Bin Meng | roms: opensbi: Upgrade from v0.5 to v0.6 Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-03-17 | Alistair Francis | target/riscv: Correctly implement TSR trap Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-03-05 | Palmer Dabbelt | RISC-V: Add a missing "," in riscv_excp_names Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Anup Patel | hw/riscv: Provide rdtime callback for TCG in CLINT... Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Anup Patel | target/riscv: Emulate TIME CSRs for privileged mode Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Bin Meng | riscv: virt: Allow PCI address 0 Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Allow enabling the Hypervisor extension Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Add the MSTATUS_MPV_ISSET helper macro Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Add support for the 32-bit MSTATUSH CSR Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Set htval and mtval2 on execptions Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Raise the new execptions when 2nd stage... Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Implement second stage MMU Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Allow specifying MMU stage Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Respect MPRV and SPRV for floating point ops Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Mark both sstatus and msstatus_hs as... Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Disable guest FP support based on virtual... Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Only set TB flags with FP status if enabled Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Remove the hret instruction Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Add hfence instructions Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Add Hypervisor trap return support Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Add hypvervisor trap support Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Generate illegal instruction on WFI when V=1 Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/ricsv: Flush the TLB on virtulisation mode changes Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Add support for virtual interrupt setting Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Extend the SIP CSR to support virtulisation Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Extend the MIE CSR to support virtulisation Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Set VS bits in mideleg for Hyp extension Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Add virtual register swapping function Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Add Hypervisor machine CSRs accesses Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Add Hypervisor virtual CSRs accesses Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Add Hypervisor CSR access functions Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Dump Hypervisor registers if enabled Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Print priv and virt in disas log Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Fix CSR perm checking for HS mode Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Add the force HS exception mode Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Add the virtulisation mode Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Rename the H irqs to VS irqs Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Add support for the new execption numbers Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Add the Hypervisor CSRs to CPUState Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Add the Hypervisor extension Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-27 | Alistair Francis | target/riscv: Convert MIP CSR to target_ulong Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-10 | Anup Patel | MAINTAINERS: Add maintainer entry for Goldfish RTC Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-10 | Anup Patel | riscv: virt: Use Goldfish RTC device Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-10 | Anup Patel | hw: rtc: Add Goldfish RTC device Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-10 | Keith Packard | riscv: Separate FPU register size from core register... Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-02-10 | Anup Patel | riscv/virt: Add syscon reboot and poweroff DT nodes Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-01-16 | ShihPo Hung | target/riscv: update mstatus.SD when FS is set dirty Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-01-16 | ShihPo Hung | target/riscv: fsd/fsw doesn't dirty FP state Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-01-16 | ShihPo Hung | target/riscv: Fix tb->flags FS status Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-01-16 | Yiting Wang | riscv: Set xPIE to 1 after xRET Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2020-01-16 | Pan Nengyuan | riscv/sifive_u: fix a memory leak in soc_realize() Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2019-11-25 | Zhuang, Siwei (Data6... | hw/riscv: Add optional symbol callback ptr to riscv_load_ker... Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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| 2019-11-25 | Palmer Dabbelt | RISC-V: virt: This is a "sifive,test1" test finisher Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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