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drm/i915: Rewrite bxt_hpd_handler() to look like everyone else
2015-09-02 Ville Syrjälädrm/i915: Rewrite bxt_hpd_handler() to look like everyone...
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2015-09-02 Ville Syrjälädrm/i915: Reinitialize HPD after runtime D3
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2015-09-02 Ville Syrjälädrm/i915: Add port A HPD support for SPT
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2015-09-02 Ville Syrjälädrm/i915: Add port A HPD support for BDW
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2015-09-02 Ville Syrjälädrm/i915: LPT:LP needs port A HPD enabled in both north...
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2015-09-02 Ville Syrjälädrm/i915: Add port A HPD support for IVB/HSW
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2015-09-02 Ville Syrjälädrm/i915: Add port A HPD support for ILK/SNB
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2015-09-02 Ville Syrjälädrm/i915: Introduce spt_irq_handler()
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2015-09-02 Ville Syrjälädrm/i915: Move {pin, long}_mask initialization to caller...
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2015-09-02 Ville Syrjälädrm/i915: Rename BXT PORTA HPD defines
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2015-09-02 Ville Syrjälädrm/i915: Add HAS_PCH_LPT_LP() macro
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2015-09-02 Ville Syrjälädrm/i915: Factor out ilk_update_display_irq()
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2015-09-02 Ville Syrjälädrm/i915: Extract intel_hpd_enabled_irqs()
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2015-09-02 Ville Syrjälädrm/i915: Clean up various HPD defines
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2015-09-01 Ville Syrjälädrm/i915: Factor out intel_crtc_has_encoders()
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2015-09-01 Ville Syrjälädrm/i915: Fix clock readout when pipes are enabled...
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2015-09-01 Ville Syrjälädrm/i915: Add CHV PHY LDO power sanity checks
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2015-09-01 Ville Syrjälädrm/i915: Add some CHV DPIO lane power state asserts
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2015-09-01 Ville Syrjälädrm/i915: Clean up CHV lane soft reset programming
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2015-09-01 Ville Syrjälädrm/i915: Don't use link_bw for PLL setup
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2015-08-31 Ville Syrjälädrm/i915: Check DP link status on long hpd too
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2015-08-26 Ville Syrjälädrm/i915: Force CL2 off in CHV x1 PHY
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2015-08-26 Ville Syrjälädrm/i915: Enable DPIO SUS clock gating on CHV
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2015-08-26 Ville Syrjälädrm/i915: Force common lane on for the PPS kick on CHV
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2015-08-26 Ville Syrjälädrm/i915: Trick CL2 into life on CHV when using pipe...
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2015-08-26 Ville Syrjälädrm/i915: Implement PHY lane power gating for CHV
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2015-08-26 Ville Syrjälädrm/i915: Move DPLL ref/cri/VGA mode frobbing to the...
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2015-08-26 Ville Syrjälädrm/i915: Make some string arrays const
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2015-08-26 Ville Syrjälädrm/i915: Use ARRAY_SIZE() instead of hand rolling it
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2015-08-26 Ville Syrjälädrm/i915: Fix some gcc warnings
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2015-08-26 Ville Syrjälädrm/i915: Add vlv_dport_to_phy()
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2015-08-26 Ville Syrjälädrm/i915: Move VLV/CHV prepare_pll later
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2015-08-26 Ville Syrjälädrm/i915: Add locking around chv_phy_control_init()
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2015-08-26 Ville Syrjälädrm/i915: Move DPIO port init earlier
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2015-08-26 Ville Syrjälädrm/i915: Add encoder->post_pll_disable() hooks and...
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2015-08-26 Ville Syrjälädrm/i915: Always program unique transition scale for CHV
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2015-08-26 Ville Syrjälädrm/i915: Always program m2 fractional value on CHV
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2015-08-26 Ville Syrjälädrm/i915: Put back lane_count into intel_dp and add...
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2015-08-14 Ville Syrjälädrm/i915: Kill intel_dp->{link_bw, rate_select}
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2015-08-14 Ville Syrjälädrm/i915: Don't use link_bw to select between TP1 and TP3
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2015-08-14 Ville Syrjälädrm/i915: Move intel_dp->lane_count into pipe_config
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2015-08-14 Ville Syrjälädrm/i915: Avoid confusion between DP and TRANS_DP_CTL...
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2015-08-14 Ville Syrjälädrm/i915: Don't pass clock to DDI PLL select functions
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2015-08-14 Ville Syrjälädrm/i915: Don't use link_bw for PLL setup
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2015-08-14 Ville Syrjälädrm/i915: Clean up DP/HDMI limited color range handling
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2015-08-14 Ville Syrjälädrm/i915: clflush on pin_to_display after pwrite to...
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2015-07-13 Ville Syrjälädrm/i915: Adjust BXT HDMI port clock limits
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2015-07-13 Ville Syrjälädrm/i915: Refactor VLV display power well init/deinit
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2015-07-13 Ville Syrjälädrm/i915: Simplify CHV pipe A power well code
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2015-07-13 Ville Syrjälädrm/i915: Apply OCD to VLV/CHV DPLL defines
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2015-07-13 Ville Syrjälädrm/i915: Keep GMCH DPLL VGA mode always disabled
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2015-07-09 Ville SyrjäläRevert "drm/i915: Allocate context objects from stolen"
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2015-07-06 Ville Syrjälädrm/i915: Disable LVDS port after the pipe on PCH
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2015-07-06 Ville Syrjälädrm/i915: Drop a spurious intel_pre_plane_update()...
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2015-07-06 Ville SyrjäläRevert "drm/i915: Disable 12bpc hdmi for now"
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2015-07-06 Ville Syrjälädrm/i915: Account for CHV/BXT DPLL clock limitations
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2015-07-06 Ville Syrjälädrm/i915: Bump HDMI min port clock to 25 MHz
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2015-07-06 Ville Syrjälädrm/i915: Fix HDMI 12bpc and pixel repeat clock readout...
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2015-06-29 Ville Syrjälädrm/i915: Zero unused WM1 watermarks on VLV/CHV
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2015-06-29 Ville Syrjälädrm/i915: Add debugfs knobs for VLVCHV memory latency...
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2015-06-29 Ville Syrjälädrm/i915: Don't do PM5/DDR DVFS with multiple pipes
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2015-06-29 Ville Syrjälädrm/i915: Try to make sure cxsr is disabled around...
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2015-06-29 Ville Syrjälädrm/i915: Use the memory latency based WM computation...
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2015-06-29 Ville Syrjälädrm/i915: Compute display FIFO split dynamically for CHV
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2015-06-29 Ville Syrjälädrm/i915: CHV DDR DVFS support and another watermark...
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2015-06-29 Ville Syrjälädrm/i915: Read wm values from hardware at init on CHV
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2015-06-29 Ville Syrjälädrm/i915: Split atomic wm update to pre and post variants
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2015-06-29 Ville Syrjälädrm/i915: POSTING_READ() in intel_set_memory_cxsr()
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2015-06-25 Ville Syrjälädrm/i915: Add debug messages for pipe enable/disable
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2015-06-25 Ville Syrjälädrm/i915: Store frontbuffer_bits in the plane
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2015-06-22 Ville Syrjälädrm/i915: Factor out p2 divider selection for pre-ilk...
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2015-06-15 Ville Syrjälädrm/i915: Drop the 64k linear scanout alignment on...
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2015-06-15 Ville Syrjälädrm/i915: Align DSPSURF to 128k on VLV/CHV
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2015-06-15 Ville Syrjälädrm/i915: Actually respect DSPSURF alignment restrictions
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2015-06-15 Ville Syrjälädrm/i915: Bump CHV PFI credits to 63 when cdclk>=czclk
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2015-06-15 Ville Syrjälädrm/i915: Double the port clock when using double clocked...
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2015-06-15 Ville Syrjälädrm/i915: Fix hdmi clock readout with pixel repeat
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2015-06-15 Ville Syrjälädrm/i915: Check infoframe state more diligently.
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2015-06-15 Ville Syrjälädrm/i915: Disable all infoframes when turning off the...
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2015-06-15 Ville Syrjälädrm/i915: Fix 12bpc HDMI enable for IBX
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2015-06-15 Ville Syrjälädrm/i915: Fix HDMI 12bpc TRANSCONF bpc value
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2015-06-15 Ville Syrjälädrm/i915: Enable default_phase in GCP when possible
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2015-06-15 Ville Syrjälädrm/i915: Send GCP infoframes for deep color HDMI sinks
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2015-06-15 Ville Syrjälädrm/i915: Don't skip request retirement if the active...
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2015-06-15 Ville Syrjälädrm/i915: Implement WaEnableHDMI8bpcBefore12bpc:snb...
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2015-06-12 Ville Syrjälädrm/i915: BDW clock change support
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2015-06-12 Ville Syrjälädrm/i915: Add IS_BDW_ULX
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2015-06-12 Ville Syrjälädrm/i915: Don't enable IPS when pixel rate exceeds 95%
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2015-06-12 Ville Syrjälädrm/i915: Store max cdclk value in dev_priv
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2015-06-12 Ville Syrjälädrm/i915: Use cached cdclk value
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2015-06-12 Ville Syrjälädrm/i915: Cache current cdclk frequency in dev_priv
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2015-06-04 Ville Syrjälädrm/i915: Move WaBarrierPerformanceFixDisable:skl to...
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2015-06-03 Ville Syrjälädrm/i915: Apply WaDisableAsyncFlipPerfMode via LRIs...
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2015-06-03 Ville Syrjälädrm/i915: Set INSTPM_FORCE_ORDERING via LRI on gen8...
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2015-06-03 Ville Syrjälädrm/i915: Move WaBarrierPerformanceFixDisable:skl to...
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2015-06-01 Ville Syrjälädrm/i915: Don't skip request retirement if the active...
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2015-05-29 Ville Syrjälädrm/i915: Warn when cdclk for the platforms is not...
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2015-05-29 Ville Syrjälädrm/i915: Add cdclk extraction for g33, g965gm and g4x
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2015-05-29 Ville Syrjälädrm/i915: Fix 852GM/GMV cdclk
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2015-05-29 Ville Syrjälädrm/i915: Fix i855 get_display_clock_speed
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