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target/loongarch/cpu: Fix cpucfg default value
2022-07-19 Xiaojuan Yangtarget/loongarch/cpu: Fix cpucfg default value
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
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2022-07-19 Xiaojuan Yangtarget/loongarch/op_helper: Fix coverity cond_at_most...
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
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2022-07-19 Xiaojuan Yangtarget/loongarch/tlb_helper: Fix coverity integer overflow...
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
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2022-07-19 Xiaojuan Yangtarget/loongarch/cpu: Fix coverity errors about excp_names
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
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2022-07-19 Xiaojuan Yanghw/intc/loongarch_pch_pic: Fix bugs for update_irq...
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
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2022-07-19 Xiaojuan Yangtarget/loongarch: Fix loongarch_cpu_class_by_name
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
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2022-07-05 Xiaojuan Yanghw/intc/loongarch_ipi: Fix mail send and any send function
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
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2022-07-05 Xiaojuan Yanghw/intc/loongarch_ipi: Fix ipi device access of 64bits
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
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2022-07-04 Xiaojuan Yangtarget/loongarch: Add lock when writing timer clear reg
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
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2022-07-04 Xiaojuan Yangtarget/loongarch: Fix the meaning of ECFG reg's VS...
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
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2022-07-04 Xiaojuan Yanghw/rtc/ls7a_rtc: Fix 'calculate' spelling errors
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
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2022-07-04 Xiaojuan Yanghw/rtc/ls7a_rtc: Use tm struct pointer as arguments...
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
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2022-07-04 Xiaojuan Yanghw/rtc/ls7a_rtc: Fix rtc enable and disable function
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
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2022-07-04 Xiaojuan Yanghw/rtc/ls7a_rtc: Add reset function
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
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2022-07-04 Xiaojuan Yanghw/rtc/ls7a_rtc: Remove unimplemented device in realized...
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
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2022-07-04 Xiaojuan Yanghw/rtc/ls7a_rtc: Fix timer call back function
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
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2022-07-04 Xiaojuan Yanghw/rtc/ls7a_rtc: Fix uninitialied bugs and toymatch...
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
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2022-06-06 Xiaojuan Yangtests/tcg/loongarch64: Add hello/memory test in loongarch64...
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
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2022-06-06 Xiaojuan Yangtarget/loongarch: Add gdb support.
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
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2022-06-06 Xiaojuan Yanghw/loongarch: Add LoongArch virt power manager support.
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
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2022-06-06 Xiaojuan Yanghw/loongarch: Add LoongArch load elf function.
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
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2022-06-06 Xiaojuan Yanghw/loongarch: Add LoongArch ls7a rtc device support
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
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2022-06-06 Xiaojuan Yanghw/loongarch: Add some devices support for 3A5000.
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
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2022-06-06 Xiaojuan YangEnable common virtio pci support for LoongArch
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
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2022-06-06 Xiaojuan Yanghw/loongarch: Add irq hierarchy for the system
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
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2022-06-06 Xiaojuan Yanghw/intc: Add LoongArch extioi interrupt controller...
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
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2022-06-06 Xiaojuan Yanghw/intc: Add LoongArch ls7a msi interrupt controller...
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
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2022-06-06 Xiaojuan Yanghw/intc: Add LoongArch ls7a interrupt controller support...
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
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2022-06-06 Xiaojuan Yanghw/loongarch: Add LoongArch ipi interrupt support(IPI)
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
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2022-06-06 Xiaojuan Yanghw/loongarch: Add support loongson3 virt machine type.
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
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2022-06-06 Xiaojuan Yangtarget/loongarch: Add timer related instructions support.
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
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2022-06-06 Xiaojuan Yangtarget/loongarch: Add other core instructions support
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
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2022-06-06 Xiaojuan Yangtarget/loongarch: Add TLB instruction support
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
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2022-06-06 Xiaojuan Yangtarget/loongarch: Add LoongArch IOCSR instruction
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
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2022-06-06 Xiaojuan Yangtarget/loongarch: Add LoongArch CSR instruction
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
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2022-06-06 Xiaojuan Yangtarget/loongarch: Add constant timer support
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
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2022-06-06 Xiaojuan Yangtarget/loongarch: Add LoongArch interrupt and exception...
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
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2022-06-06 Xiaojuan Yangtarget/loongarch: Add MMU support for LoongArch CPU.
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
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2022-06-06 Xiaojuan Yangtarget/loongarch: Implement qmp_query_cpu_definitions()
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
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2022-06-06 Xiaojuan Yangtarget/loongarch: Add basic vmstate description of...
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
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2022-06-06 Xiaojuan Yangtarget/loongarch: Add CSRs definition
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
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2022-06-06 Xiaojuan Yangtarget/loongarch: Add system emulation introduction
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
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