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2023-03-02 | Bin Meng | hw/riscv: Move the dtb load bits outside of create_fdt() Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> |
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2023-03-02 | Bin Meng | hw/riscv: Skip re-generating DT nodes for a given DTB Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> |
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2023-03-02 | Weiwei Li | target/riscv: Add support for Zicond extension Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> |
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2023-03-02 | Christoph Müllner | RISC-V: XTheadMemPair: Remove register restrictions... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> |
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2023-03-02 | Shaobo Song | target/riscv: Fix checking of whether instruciton at... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> |
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2023-03-02 | Palmer Dabbelt | Merge patch series "target/riscv: Various fixes to... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> |
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2023-03-02 | Bin Meng | target/riscv: Group all predicate() routines together Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> |
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2023-03-02 | Bin Meng | target/riscv: Drop priv level check in mseccfg predicate() Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> |
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2023-03-02 | Bin Meng | target/riscv: Allow debugger to access sstc CSRs Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> |
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2023-03-02 | Bin Meng | target/riscv: Allow debugger to access {h, s}stateen... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> |
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2023-03-02 | Bin Meng | target/riscv: Allow debugger to access seed CSR Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> |
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2023-03-02 | Bin Meng | target/riscv: Allow debugger to access user timer and... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> |
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2023-03-02 | Bin Meng | target/riscv: gdbstub: Drop the vector CSRs in riscv... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> |
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2023-03-02 | Bin Meng | target/riscv: gdbstub: Turn on debugger mode before... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> |
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2023-03-02 | Bin Meng | target/riscv: Avoid reporting odd-numbered pmpcfgX... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> |
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2023-03-02 | Bin Meng | target/riscv: Simplify getting RISCVCPU pointer from env Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> |
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2023-03-02 | Bin Meng | target/riscv: Simplify {read, write}_pmpcfg() a little bit Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> |
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2023-03-02 | Bin Meng | target/riscv: Use 'bool' type for read_only Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> |
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2023-03-02 | Bin Meng | target/riscv: Coding style fixes in csr.c Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> |
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2023-03-02 | Bin Meng | target/riscv: gdbstub: Do not generate CSR XML if Zicsr... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> |
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2023-03-02 | Bin Meng | target/riscv: gdbstub: Minor change for better readability Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> |
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2023-03-02 | Bin Meng | target/riscv: Use g_assert() for the predicate() NULL... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> |
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2023-03-02 | Bin Meng | target/riscv: Add some comments to clarify the priority... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> |
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2023-03-02 | Bin Meng | target/riscv: gdbstub: Check priv spec version before... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> |
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2023-03-01 | Palmer Dabbelt | Merge patch series "target/riscv: Some updates to float... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> |
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2023-03-01 | Palmer Dabbelt | Merge patch series "make write_misa a no-op and FEATURE_... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> |
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2023-03-01 | Weiwei Li | target/riscv: Expose properties for Zv* extensions Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> |
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2023-03-01 | Weiwei Li | target/riscv: Simplify check for EEW = 64 in trans_rvv... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> |
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2023-03-01 | Weiwei Li | target/riscv: Fix check for vector load/store instructions... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> |
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2023-03-01 | Weiwei Li | target/riscv: Add support for Zvfh/zvfhmin extensions Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> |
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2023-03-01 | Weiwei Li | target/riscv: Remove redundunt check for zve32f and... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> |
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2023-03-01 | Weiwei Li | target/riscv: Replace check for F/D to Zve32f/Zve64d... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> |
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2023-03-01 | Weiwei Li | target/riscv: Simplify check for Zve32f and Zve64f Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> |
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2023-03-01 | Weiwei Li | target/riscv: Indent fixes in cpu.c Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> |
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2023-03-01 | Weiwei Li | target/riscv: Add property check for Zvfh{min} extensions Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> |
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2023-03-01 | Weiwei Li | target/riscv: Fix relationship between V, Zve*, F and D Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> |
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2023-03-01 | Weiwei Li | target/riscv: Add cfg properties for Zv* extensions Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> |
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2023-03-01 | Weiwei Li | target/riscv: Simplify the check for Zfhmin and Zhinxmin Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> |
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2023-03-01 | Weiwei Li | target/riscv: Fix the relationship between Zhinxmin... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> |
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2023-03-01 | Weiwei Li | target/riscv: Fix the relationship between Zfhmin and Zfh Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> |
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2023-03-01 | Daniel Henrique... | target/riscv/cpu: remove CPUArchState::features and... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> |
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2023-03-01 | Daniel Henrique... | target/riscv: remove RISCV_FEATURE_MMU Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> |
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2023-03-01 | Daniel Henrique... | hw/riscv/virt.c: do not use RISCV_FEATURE_MMU in create_fdt_... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> |
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2023-03-01 | Daniel Henrique... | target/riscv: remove RISCV_FEATURE_PMP Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> |
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2023-03-01 | Daniel Henrique... | target/riscv: remove RISCV_FEATURE_EPMP Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> |
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2023-03-01 | Daniel Henrique... | target/riscv/cpu.c: error out if EPMP is enabled without PMP Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> |
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2023-03-01 | Daniel Henrique... | target/riscv: remove RISCV_FEATURE_DEBUG Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> |
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2023-03-01 | Daniel Henrique... | target/riscv: allow MISA writes as experimental Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> |
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2023-03-01 | Daniel Henrique... | target/riscv: do not mask unsupported QEMU extensions... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> |
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2023-03-01 | Daniel Henrique... | target/riscv: introduce riscv_cpu_cfg() Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> |
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2023-02-23 | LIU Zhiwei | target/riscv: Fix vslide1up.vf and vslide1down.vf Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> |
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2023-02-23 | Daniel Henrique... | target/riscv: avoid env_archcpu() in cpu_get_tb_cpu_state() Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> |
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2023-02-23 | Himanshu Chauhan | target/riscv: Smepmp: Skip applying default rules when... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> |
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2023-02-23 | Alistair Francis | MAINTAINERS: Add some RISC-V reviewers Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> |
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2023-02-23 | Frank Chang | target/riscv: Remove privileged spec version restriction... Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> |
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2023-02-16 | Daniel Henrique... | hw/riscv/boot.c: make riscv_load_initrd() static Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> |
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2023-02-16 | Daniel Henrique... | hw/riscv/boot.c: consolidate all kernel init in riscv_load_k... Cc: Palmer Dabbelt <palmer@dabbelt.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> |
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2023-02-16 | Daniel Henrique... | hw/riscv: handle 32 bit CPUs kernel_entry in riscv_load_kernel() Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> |
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2020-03-17 | Rajnesh Kanwal | target/riscv: Fix VS mode interrupts forwarding. Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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2020-03-17 | Bin Meng | gitlab-ci.yml: Add jobs to build OpenSBI firmware binaries Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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2020-03-17 | Bin Meng | riscv: sifive_u: Update BIOS_FILENAME for 32-bit Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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2020-03-17 | Bin Meng | roms: opensbi: Add 32-bit firmware image for sifive_u... Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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2020-03-17 | Bin Meng | roms: opensbi: Upgrade from v0.5 to v0.6 Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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2020-03-17 | Alistair Francis | target/riscv: Correctly implement TSR trap Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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2020-03-05 | Palmer Dabbelt | RISC-V: Add a missing "," in riscv_excp_names Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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2020-02-27 | Anup Patel | hw/riscv: Provide rdtime callback for TCG in CLINT... Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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2020-02-27 | Anup Patel | target/riscv: Emulate TIME CSRs for privileged mode Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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2020-02-27 | Bin Meng | riscv: virt: Allow PCI address 0 Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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2020-02-27 | Alistair Francis | target/riscv: Allow enabling the Hypervisor extension Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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2020-02-27 | Alistair Francis | target/riscv: Add the MSTATUS_MPV_ISSET helper macro Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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2020-02-27 | Alistair Francis | target/riscv: Add support for the 32-bit MSTATUSH CSR Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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2020-02-27 | Alistair Francis | target/riscv: Set htval and mtval2 on execptions Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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2020-02-27 | Alistair Francis | target/riscv: Raise the new execptions when 2nd stage... Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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2020-02-27 | Alistair Francis | target/riscv: Implement second stage MMU Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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2020-02-27 | Alistair Francis | target/riscv: Allow specifying MMU stage Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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2020-02-27 | Alistair Francis | target/riscv: Respect MPRV and SPRV for floating point ops Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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2020-02-27 | Alistair Francis | target/riscv: Mark both sstatus and msstatus_hs as... Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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2020-02-27 | Alistair Francis | target/riscv: Disable guest FP support based on virtual... Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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2020-02-27 | Alistair Francis | target/riscv: Only set TB flags with FP status if enabled Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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2020-02-27 | Alistair Francis | target/riscv: Remove the hret instruction Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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2020-02-27 | Alistair Francis | target/riscv: Add hfence instructions Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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2020-02-27 | Alistair Francis | target/riscv: Add Hypervisor trap return support Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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2020-02-27 | Alistair Francis | target/riscv: Add hypvervisor trap support Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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2020-02-27 | Alistair Francis | target/riscv: Generate illegal instruction on WFI when V=1 Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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2020-02-27 | Alistair Francis | target/ricsv: Flush the TLB on virtulisation mode changes Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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2020-02-27 | Alistair Francis | target/riscv: Add support for virtual interrupt setting Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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2020-02-27 | Alistair Francis | target/riscv: Extend the SIP CSR to support virtulisation Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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2020-02-27 | Alistair Francis | target/riscv: Extend the MIE CSR to support virtulisation Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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2020-02-27 | Alistair Francis | target/riscv: Set VS bits in mideleg for Hyp extension Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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2020-02-27 | Alistair Francis | target/riscv: Add virtual register swapping function Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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2020-02-27 | Alistair Francis | target/riscv: Add Hypervisor machine CSRs accesses Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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2020-02-27 | Alistair Francis | target/riscv: Add Hypervisor virtual CSRs accesses Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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2020-02-27 | Alistair Francis | target/riscv: Add Hypervisor CSR access functions Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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2020-02-27 | Alistair Francis | target/riscv: Dump Hypervisor registers if enabled Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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2020-02-27 | Alistair Francis | target/riscv: Print priv and virt in disas log Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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2020-02-27 | Alistair Francis | target/riscv: Fix CSR perm checking for HS mode Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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2020-02-27 | Alistair Francis | target/riscv: Add the force HS exception mode Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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2020-02-27 | Alistair Francis | target/riscv: Add the virtulisation mode Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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2020-02-27 | Alistair Francis | target/riscv: Rename the H irqs to VS irqs Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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2020-02-27 | Alistair Francis | target/riscv: Add support for the new execption numbers Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
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