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7d13299d 1/*
e965fc38 2 * emulator main execution loop
5fafdf24 3 *
66321a11 4 * Copyright (c) 2003-2005 Fabrice Bellard
7d13299d 5 *
3ef693a0
FB
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
7d13299d 10 *
3ef693a0
FB
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
7d13299d 15 *
3ef693a0 16 * You should have received a copy of the GNU Lesser General Public
8167ee88 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
7d13299d 18 */
e4533c7a 19#include "config.h"
cea5f9a2 20#include "cpu.h"
6db8b538 21#include "trace.h"
76cad711 22#include "disas/disas.h"
7cb69cae 23#include "tcg.h"
1de7afc9 24#include "qemu/atomic.h"
9c17d615 25#include "sysemu/qtest.h"
c2aa5f81 26#include "qemu/timer.h"
9d82b5a7 27#include "exec/address-spaces.h"
79e2b9ae 28#include "qemu/rcu.h"
e1b89321 29#include "exec/tb-hash.h"
6220e900
PD
30#if defined(TARGET_I386) && !defined(CONFIG_USER_ONLY)
31#include "hw/i386/apic.h"
32#endif
c2aa5f81
ST
33
34/* -icount align implementation. */
35
36typedef struct SyncClocks {
37 int64_t diff_clk;
38 int64_t last_cpu_icount;
7f7bc144 39 int64_t realtime_clock;
c2aa5f81
ST
40} SyncClocks;
41
42#if !defined(CONFIG_USER_ONLY)
43/* Allow the guest to have a max 3ms advance.
44 * The difference between the 2 clocks could therefore
45 * oscillate around 0.
46 */
47#define VM_CLOCK_ADVANCE 3000000
7f7bc144
ST
48#define THRESHOLD_REDUCE 1.5
49#define MAX_DELAY_PRINT_RATE 2000000000LL
50#define MAX_NB_PRINTS 100
c2aa5f81
ST
51
52static void align_clocks(SyncClocks *sc, const CPUState *cpu)
53{
54 int64_t cpu_icount;
55
56 if (!icount_align_option) {
57 return;
58 }
59
60 cpu_icount = cpu->icount_extra + cpu->icount_decr.u16.low;
61 sc->diff_clk += cpu_icount_to_ns(sc->last_cpu_icount - cpu_icount);
62 sc->last_cpu_icount = cpu_icount;
63
64 if (sc->diff_clk > VM_CLOCK_ADVANCE) {
65#ifndef _WIN32
66 struct timespec sleep_delay, rem_delay;
67 sleep_delay.tv_sec = sc->diff_clk / 1000000000LL;
68 sleep_delay.tv_nsec = sc->diff_clk % 1000000000LL;
69 if (nanosleep(&sleep_delay, &rem_delay) < 0) {
a498d0ef 70 sc->diff_clk = rem_delay.tv_sec * 1000000000LL + rem_delay.tv_nsec;
c2aa5f81
ST
71 } else {
72 sc->diff_clk = 0;
73 }
74#else
75 Sleep(sc->diff_clk / SCALE_MS);
76 sc->diff_clk = 0;
77#endif
78 }
79}
80
7f7bc144
ST
81static void print_delay(const SyncClocks *sc)
82{
83 static float threshold_delay;
84 static int64_t last_realtime_clock;
85 static int nb_prints;
86
87 if (icount_align_option &&
88 sc->realtime_clock - last_realtime_clock >= MAX_DELAY_PRINT_RATE &&
89 nb_prints < MAX_NB_PRINTS) {
90 if ((-sc->diff_clk / (float)1000000000LL > threshold_delay) ||
91 (-sc->diff_clk / (float)1000000000LL <
92 (threshold_delay - THRESHOLD_REDUCE))) {
93 threshold_delay = (-sc->diff_clk / 1000000000LL) + 1;
94 printf("Warning: The guest is now late by %.1f to %.1f seconds\n",
95 threshold_delay - 1,
96 threshold_delay);
97 nb_prints++;
98 last_realtime_clock = sc->realtime_clock;
99 }
100 }
101}
102
c2aa5f81
ST
103static void init_delay_params(SyncClocks *sc,
104 const CPUState *cpu)
105{
106 if (!icount_align_option) {
107 return;
108 }
2e91cc62
PB
109 sc->realtime_clock = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL_RT);
110 sc->diff_clk = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - sc->realtime_clock;
c2aa5f81 111 sc->last_cpu_icount = cpu->icount_extra + cpu->icount_decr.u16.low;
27498bef
ST
112 if (sc->diff_clk < max_delay) {
113 max_delay = sc->diff_clk;
114 }
115 if (sc->diff_clk > max_advance) {
116 max_advance = sc->diff_clk;
117 }
7f7bc144
ST
118
119 /* Print every 2s max if the guest is late. We limit the number
120 of printed messages to NB_PRINT_MAX(currently 100) */
121 print_delay(sc);
c2aa5f81
ST
122}
123#else
124static void align_clocks(SyncClocks *sc, const CPUState *cpu)
125{
126}
127
128static void init_delay_params(SyncClocks *sc, const CPUState *cpu)
129{
130}
131#endif /* CONFIG USER ONLY */
7d13299d 132
77211379
PM
133/* Execute a TB, and fix up the CPU state afterwards if necessary */
134static inline tcg_target_ulong cpu_tb_exec(CPUState *cpu, uint8_t *tb_ptr)
135{
136 CPUArchState *env = cpu->env_ptr;
03afa5f8
RH
137 uintptr_t next_tb;
138
139#if defined(DEBUG_DISAS)
140 if (qemu_loglevel_mask(CPU_LOG_TB_CPU)) {
141#if defined(TARGET_I386)
142 log_cpu_state(cpu, CPU_DUMP_CCOP);
143#elif defined(TARGET_M68K)
144 /* ??? Should not modify env state for dumping. */
145 cpu_m68k_flush_flags(env, env->cc_op);
146 env->cc_op = CC_OP_FLAGS;
147 env->sr = (env->sr & 0xffe0) | env->cc_dest | (env->cc_x << 4);
148 log_cpu_state(cpu, 0);
149#else
150 log_cpu_state(cpu, 0);
151#endif
152 }
153#endif /* DEBUG_DISAS */
154
414b15c9 155 cpu->can_do_io = !use_icount;
03afa5f8 156 next_tb = tcg_qemu_tb_exec(env, tb_ptr);
626cf8f4 157 cpu->can_do_io = 1;
6db8b538
AB
158 trace_exec_tb_exit((void *) (next_tb & ~TB_EXIT_MASK),
159 next_tb & TB_EXIT_MASK);
160
77211379
PM
161 if ((next_tb & TB_EXIT_MASK) > TB_EXIT_IDX1) {
162 /* We didn't start executing this TB (eg because the instruction
163 * counter hit zero); we must restore the guest PC to the address
164 * of the start of the TB.
165 */
bdf7ae5b 166 CPUClass *cc = CPU_GET_CLASS(cpu);
77211379 167 TranslationBlock *tb = (TranslationBlock *)(next_tb & ~TB_EXIT_MASK);
bdf7ae5b
AF
168 if (cc->synchronize_from_tb) {
169 cc->synchronize_from_tb(cpu, tb);
170 } else {
171 assert(cc->set_pc);
172 cc->set_pc(cpu, tb->pc);
173 }
77211379 174 }
378df4b2
PM
175 if ((next_tb & TB_EXIT_MASK) == TB_EXIT_REQUESTED) {
176 /* We were asked to stop executing TBs (probably a pending
177 * interrupt. We've now stopped, so clear the flag.
178 */
179 cpu->tcg_exit_req = 0;
180 }
77211379
PM
181 return next_tb;
182}
183
2e70f6ef
PB
184/* Execute the code without caching the generated code. An interpreter
185 could be used if available. */
ea3e9847 186static void cpu_exec_nocache(CPUState *cpu, int max_cycles,
cea5f9a2 187 TranslationBlock *orig_tb)
2e70f6ef 188{
2e70f6ef
PB
189 TranslationBlock *tb;
190
191 /* Should never happen.
192 We only end up here when an existing TB is too long. */
193 if (max_cycles > CF_COUNT_MASK)
194 max_cycles = CF_COUNT_MASK;
195
02d57ea1 196 tb = tb_gen_code(cpu, orig_tb->pc, orig_tb->cs_base, orig_tb->flags,
d8a499f1 197 max_cycles | CF_NOCACHE);
02d57ea1 198 tb->orig_tb = tcg_ctx.tb_ctx.tb_invalidated_flag ? NULL : orig_tb;
d77953b9 199 cpu->current_tb = tb;
2e70f6ef 200 /* execute the generated code */
6db8b538 201 trace_exec_tb_nocache(tb, tb->pc);
77211379 202 cpu_tb_exec(cpu, tb->tc_ptr);
d77953b9 203 cpu->current_tb = NULL;
2e70f6ef
PB
204 tb_phys_invalidate(tb, -1);
205 tb_free(tb);
206}
207
9fd1a948
PB
208static TranslationBlock *tb_find_physical(CPUState *cpu,
209 target_ulong pc,
210 target_ulong cs_base,
211 uint64_t flags)
8a40a180 212{
ea3e9847 213 CPUArchState *env = (CPUArchState *)cpu->env_ptr;
8a40a180 214 TranslationBlock *tb, **ptb1;
8a40a180 215 unsigned int h;
337fc758 216 tb_page_addr_t phys_pc, phys_page1;
41c1b1c9 217 target_ulong virt_page2;
3b46e624 218
5e5f07e0 219 tcg_ctx.tb_ctx.tb_invalidated_flag = 0;
3b46e624 220
8a40a180 221 /* find translated block using physical mappings */
41c1b1c9 222 phys_pc = get_page_addr_code(env, pc);
8a40a180 223 phys_page1 = phys_pc & TARGET_PAGE_MASK;
8a40a180 224 h = tb_phys_hash_func(phys_pc);
5e5f07e0 225 ptb1 = &tcg_ctx.tb_ctx.tb_phys_hash[h];
8a40a180
FB
226 for(;;) {
227 tb = *ptb1;
9fd1a948
PB
228 if (!tb) {
229 return NULL;
230 }
5fafdf24 231 if (tb->pc == pc &&
8a40a180 232 tb->page_addr[0] == phys_page1 &&
5fafdf24 233 tb->cs_base == cs_base &&
8a40a180
FB
234 tb->flags == flags) {
235 /* check next page if needed */
236 if (tb->page_addr[1] != -1) {
337fc758
BS
237 tb_page_addr_t phys_page2;
238
5fafdf24 239 virt_page2 = (pc & TARGET_PAGE_MASK) +
8a40a180 240 TARGET_PAGE_SIZE;
41c1b1c9 241 phys_page2 = get_page_addr_code(env, virt_page2);
9fd1a948
PB
242 if (tb->page_addr[1] == phys_page2) {
243 break;
244 }
8a40a180 245 } else {
9fd1a948 246 break;
8a40a180
FB
247 }
248 }
249 ptb1 = &tb->phys_hash_next;
250 }
3b46e624 251
9fd1a948
PB
252 /* Move the TB to the head of the list */
253 *ptb1 = tb->phys_hash_next;
254 tb->phys_hash_next = tcg_ctx.tb_ctx.tb_phys_hash[h];
255 tcg_ctx.tb_ctx.tb_phys_hash[h] = tb;
256 return tb;
257}
258
259static TranslationBlock *tb_find_slow(CPUState *cpu,
260 target_ulong pc,
261 target_ulong cs_base,
262 uint64_t flags)
263{
264 TranslationBlock *tb;
265
266 tb = tb_find_physical(cpu, pc, cs_base, flags);
267 if (tb) {
268 goto found;
269 }
270
271#ifdef CONFIG_USER_ONLY
272 /* mmap_lock is needed by tb_gen_code, and mmap_lock must be
273 * taken outside tb_lock. Since we're momentarily dropping
274 * tb_lock, there's a chance that our desired tb has been
275 * translated.
276 */
277 tb_unlock();
278 mmap_lock();
279 tb_lock();
280 tb = tb_find_physical(cpu, pc, cs_base, flags);
281 if (tb) {
282 mmap_unlock();
283 goto found;
2c90fe2b 284 }
9fd1a948
PB
285#endif
286
287 /* if no translated code available, then translate it now */
288 tb = tb_gen_code(cpu, pc, cs_base, flags, 0);
289
290#ifdef CONFIG_USER_ONLY
291 mmap_unlock();
292#endif
293
294found:
8a40a180 295 /* we add the TB in the virtual pc hash table */
8cd70437 296 cpu->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb;
8a40a180
FB
297 return tb;
298}
299
ea3e9847 300static inline TranslationBlock *tb_find_fast(CPUState *cpu)
8a40a180 301{
ea3e9847 302 CPUArchState *env = (CPUArchState *)cpu->env_ptr;
8a40a180
FB
303 TranslationBlock *tb;
304 target_ulong cs_base, pc;
6b917547 305 int flags;
8a40a180
FB
306
307 /* we record a subset of the CPU state. It will
308 always be the same before a given translated block
309 is executed. */
6b917547 310 cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags);
8cd70437 311 tb = cpu->tb_jmp_cache[tb_jmp_cache_hash_func(pc)];
551bd27f
TS
312 if (unlikely(!tb || tb->pc != pc || tb->cs_base != cs_base ||
313 tb->flags != flags)) {
ea3e9847 314 tb = tb_find_slow(cpu, pc, cs_base, flags);
8a40a180
FB
315 }
316 return tb;
317}
318
ea3e9847 319static void cpu_handle_debug_exception(CPUState *cpu)
1009d2ed 320{
86025ee4 321 CPUClass *cc = CPU_GET_CLASS(cpu);
1009d2ed
JK
322 CPUWatchpoint *wp;
323
ff4700b0
AF
324 if (!cpu->watchpoint_hit) {
325 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
1009d2ed
JK
326 wp->flags &= ~BP_WATCHPOINT_HIT;
327 }
328 }
86025ee4
PM
329
330 cc->debug_excp_handler(cpu);
1009d2ed
JK
331}
332
7d13299d
FB
333/* main execution loop */
334
ea3e9847 335int cpu_exec(CPUState *cpu)
7d13299d 336{
97a8ea5a 337 CPUClass *cc = CPU_GET_CLASS(cpu);
693fa551
AF
338#ifdef TARGET_I386
339 X86CPU *x86_cpu = X86_CPU(cpu);
ea3e9847 340 CPUArchState *env = &x86_cpu->env;
97a8ea5a 341#endif
8a40a180 342 int ret, interrupt_request;
8a40a180 343 TranslationBlock *tb;
c27004ec 344 uint8_t *tc_ptr;
3e9bd63a 345 uintptr_t next_tb;
c2aa5f81
ST
346 SyncClocks sc;
347
259186a7 348 if (cpu->halted) {
6220e900
PD
349#if defined(TARGET_I386) && !defined(CONFIG_USER_ONLY)
350 if (cpu->interrupt_request & CPU_INTERRUPT_POLL) {
351 apic_poll_irq(x86_cpu->apic_state);
352 cpu_reset_interrupt(cpu, CPU_INTERRUPT_POLL);
353 }
354#endif
3993c6bd 355 if (!cpu_has_work(cpu)) {
eda48c34
PB
356 return EXCP_HALTED;
357 }
358
259186a7 359 cpu->halted = 0;
eda48c34 360 }
5a1e3cfc 361
4917cf44 362 current_cpu = cpu;
9373e632 363 atomic_mb_set(&tcg_current_cpu, cpu);
79e2b9ae
PB
364 rcu_read_lock();
365
aed807c8 366 if (unlikely(atomic_mb_read(&exit_request))) {
fcd7d003 367 cpu->exit_request = 1;
1a28cac3
MT
368 }
369
cffe7b32 370 cc->cpu_exec_enter(cpu);
9d27abd9 371
c2aa5f81
ST
372 /* Calculate difference between guest clock and host clock.
373 * This delay includes the delay of the last cycle, so
374 * what we have to do is sleep until it is 0. As for the
375 * advance/delay we gain here, we try to fix it next time.
376 */
377 init_delay_params(&sc, cpu);
378
7d13299d 379 /* prepare setjmp context for exception handling */
3fb2ded1 380 for(;;) {
6f03bef0 381 if (sigsetjmp(cpu->jmp_env, 0) == 0) {
3fb2ded1 382 /* if an exception is pending, we execute it here */
27103424
AF
383 if (cpu->exception_index >= 0) {
384 if (cpu->exception_index >= EXCP_INTERRUPT) {
3fb2ded1 385 /* exit request from the cpu execution loop */
27103424 386 ret = cpu->exception_index;
1009d2ed 387 if (ret == EXCP_DEBUG) {
ea3e9847 388 cpu_handle_debug_exception(cpu);
1009d2ed 389 }
e511b4d7 390 cpu->exception_index = -1;
3fb2ded1 391 break;
72d239ed
AJ
392 } else {
393#if defined(CONFIG_USER_ONLY)
3fb2ded1 394 /* if user mode only, we simulate a fake exception
9f083493 395 which will be handled outside the cpu execution
3fb2ded1 396 loop */
83479e77 397#if defined(TARGET_I386)
97a8ea5a 398 cc->do_interrupt(cpu);
83479e77 399#endif
27103424 400 ret = cpu->exception_index;
e511b4d7 401 cpu->exception_index = -1;
3fb2ded1 402 break;
72d239ed 403#else
97a8ea5a 404 cc->do_interrupt(cpu);
27103424 405 cpu->exception_index = -1;
83479e77 406#endif
3fb2ded1 407 }
5fafdf24 408 }
9df217a3 409
b5fc09ae 410 next_tb = 0; /* force lookup of first TB */
3fb2ded1 411 for(;;) {
259186a7 412 interrupt_request = cpu->interrupt_request;
e1638bd8 413 if (unlikely(interrupt_request)) {
ed2803da 414 if (unlikely(cpu->singlestep_enabled & SSTEP_NOIRQ)) {
e1638bd8 415 /* Mask out external interrupts for this step. */
3125f763 416 interrupt_request &= ~CPU_INTERRUPT_SSTEP_MASK;
e1638bd8 417 }
6658ffb8 418 if (interrupt_request & CPU_INTERRUPT_DEBUG) {
259186a7 419 cpu->interrupt_request &= ~CPU_INTERRUPT_DEBUG;
27103424 420 cpu->exception_index = EXCP_DEBUG;
5638d180 421 cpu_loop_exit(cpu);
6658ffb8 422 }
a90b7318 423 if (interrupt_request & CPU_INTERRUPT_HALT) {
259186a7
AF
424 cpu->interrupt_request &= ~CPU_INTERRUPT_HALT;
425 cpu->halted = 1;
27103424 426 cpu->exception_index = EXCP_HLT;
5638d180 427 cpu_loop_exit(cpu);
a90b7318 428 }
4a92a558
PB
429#if defined(TARGET_I386)
430 if (interrupt_request & CPU_INTERRUPT_INIT) {
431 cpu_svm_check_intercept_param(env, SVM_EXIT_INIT, 0);
432 do_cpu_init(x86_cpu);
433 cpu->exception_index = EXCP_HALTED;
434 cpu_loop_exit(cpu);
435 }
436#else
437 if (interrupt_request & CPU_INTERRUPT_RESET) {
438 cpu_reset(cpu);
439 }
68a79315 440#endif
9585db68
RH
441 /* The target hook has 3 exit conditions:
442 False when the interrupt isn't processed,
443 True when it is, and we should restart on a new TB,
444 and via longjmp via cpu_loop_exit. */
445 if (cc->cpu_exec_interrupt(cpu, interrupt_request)) {
446 next_tb = 0;
447 }
448 /* Don't use the cached interrupt_request value,
449 do_interrupt may have updated the EXITTB flag. */
259186a7
AF
450 if (cpu->interrupt_request & CPU_INTERRUPT_EXITTB) {
451 cpu->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
bf3e8bf1
FB
452 /* ensure that no TB jump will be modified as
453 the program flow was changed */
b5fc09ae 454 next_tb = 0;
bf3e8bf1 455 }
be214e6c 456 }
fcd7d003
AF
457 if (unlikely(cpu->exit_request)) {
458 cpu->exit_request = 0;
27103424 459 cpu->exception_index = EXCP_INTERRUPT;
5638d180 460 cpu_loop_exit(cpu);
3fb2ded1 461 }
677ef623 462 tb_lock();
ea3e9847 463 tb = tb_find_fast(cpu);
d5975363
PB
464 /* Note: we do it here to avoid a gcc bug on Mac OS X when
465 doing it in tb_find_slow */
5e5f07e0 466 if (tcg_ctx.tb_ctx.tb_invalidated_flag) {
d5975363
PB
467 /* as some TB could have been invalidated because
468 of memory exceptions while generating the code, we
469 must recompute the hash index here */
470 next_tb = 0;
5e5f07e0 471 tcg_ctx.tb_ctx.tb_invalidated_flag = 0;
d5975363 472 }
c30d1aea
PM
473 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
474 qemu_log("Trace %p [" TARGET_FMT_lx "] %s\n",
475 tb->tc_ptr, tb->pc, lookup_symbol(tb->pc));
476 }
8a40a180
FB
477 /* see if we can patch the calling TB. When the TB
478 spans two pages, we cannot safely do a direct
479 jump. */
040f2fb2 480 if (next_tb != 0 && tb->page_addr[1] == -1) {
0980011b
PM
481 tb_add_jump((TranslationBlock *)(next_tb & ~TB_EXIT_MASK),
482 next_tb & TB_EXIT_MASK, tb);
3fb2ded1 483 }
677ef623 484 tb_unlock();
fcd7d003 485 if (likely(!cpu->exit_request)) {
6db8b538 486 trace_exec_tb(tb, tb->pc);
2e70f6ef 487 tc_ptr = tb->tc_ptr;
e965fc38 488 /* execute the generated code */
b0a46fa7 489 cpu->current_tb = tb;
77211379 490 next_tb = cpu_tb_exec(cpu, tc_ptr);
b0a46fa7 491 cpu->current_tb = NULL;
378df4b2
PM
492 switch (next_tb & TB_EXIT_MASK) {
493 case TB_EXIT_REQUESTED:
494 /* Something asked us to stop executing
495 * chained TBs; just continue round the main
496 * loop. Whatever requested the exit will also
497 * have set something else (eg exit_request or
498 * interrupt_request) which we will handle
ab096a75
PB
499 * next time around the loop. But we need to
500 * ensure the tcg_exit_req read in generated code
501 * comes before the next read of cpu->exit_request
502 * or cpu->interrupt_request.
378df4b2 503 */
ab096a75 504 smp_rmb();
378df4b2
PM
505 next_tb = 0;
506 break;
507 case TB_EXIT_ICOUNT_EXPIRED:
508 {
bf20dc07 509 /* Instruction counter expired. */
52851b7e 510 int insns_left = cpu->icount_decr.u32;
efee7340 511 if (cpu->icount_extra && insns_left >= 0) {
2e70f6ef 512 /* Refill decrementer and continue execution. */
efee7340 513 cpu->icount_extra += insns_left;
52851b7e 514 insns_left = MIN(0xffff, cpu->icount_extra);
efee7340 515 cpu->icount_extra -= insns_left;
28ecfd7a 516 cpu->icount_decr.u16.low = insns_left;
2e70f6ef
PB
517 } else {
518 if (insns_left > 0) {
519 /* Execute remaining instructions. */
52851b7e 520 tb = (TranslationBlock *)(next_tb & ~TB_EXIT_MASK);
ea3e9847 521 cpu_exec_nocache(cpu, insns_left, tb);
c2aa5f81 522 align_clocks(&sc, cpu);
2e70f6ef 523 }
27103424 524 cpu->exception_index = EXCP_INTERRUPT;
2e70f6ef 525 next_tb = 0;
5638d180 526 cpu_loop_exit(cpu);
2e70f6ef 527 }
378df4b2
PM
528 break;
529 }
530 default:
531 break;
2e70f6ef
PB
532 }
533 }
c2aa5f81
ST
534 /* Try to align the host and virtual clocks
535 if the guest is in advance */
536 align_clocks(&sc, cpu);
4cbf74b6
FB
537 /* reset soft MMU for next block (it can currently
538 only be set by a memory fault) */
50a518e3 539 } /* for(;;) */
0d101938
JK
540 } else {
541 /* Reload env after longjmp - the compiler may have smashed all
542 * local variables as longjmp is marked 'noreturn'. */
4917cf44 543 cpu = current_cpu;
6c78f29a 544 cc = CPU_GET_CLASS(cpu);
626cf8f4 545 cpu->can_do_io = 1;
693fa551
AF
546#ifdef TARGET_I386
547 x86_cpu = X86_CPU(cpu);
ea3e9847 548 env = &x86_cpu->env;
6c78f29a 549#endif
677ef623 550 tb_lock_reset();
7d13299d 551 }
3fb2ded1
FB
552 } /* for(;;) */
553
cffe7b32 554 cc->cpu_exec_exit(cpu);
79e2b9ae 555 rcu_read_unlock();
1057eaa7 556
4917cf44
AF
557 /* fail safe : never use current_cpu outside cpu_exec() */
558 current_cpu = NULL;
9373e632
PB
559
560 /* Does not need atomic_mb_set because a spurious wakeup is okay. */
561 atomic_set(&tcg_current_cpu, NULL);
7d13299d
FB
562 return ret;
563}