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CommitLineData
d9f24bf5
PB
1/*
2 * Target-specific parts of the CPU object
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20#include "qemu/osdep.h"
d9f24bf5
PB
21#include "qapi/error.h"
22
23#include "exec/target_page.h"
24#include "hw/qdev-core.h"
25#include "hw/qdev-properties.h"
26#include "qemu/error-report.h"
dfa47531 27#include "qemu/qemu-print.h"
d9f24bf5
PB
28#include "migration/vmstate.h"
29#ifdef CONFIG_USER_ONLY
30#include "qemu.h"
31#else
8b80bd28 32#include "hw/core/sysemu-cpu-ops.h"
d9f24bf5
PB
33#include "exec/address-spaces.h"
34#endif
412ae126 35#include "sysemu/cpus.h"
d9f24bf5 36#include "sysemu/tcg.h"
5b5968c4 37#include "exec/replay-core.h"
377bf6f3 38#include "exec/cpu-common.h"
3b04508c 39#include "exec/exec-all.h"
548c9609 40#include "exec/tb-flush.h"
3b9bd3f4 41#include "exec/translate-all.h"
d9f24bf5 42#include "exec/log.h"
30565f10 43#include "hw/core/accel-cpu.h"
ad1a706f 44#include "trace/trace-root.h"
3b04508c 45#include "qemu/accel.h"
d9f24bf5
PB
46
47uintptr_t qemu_host_page_size;
48intptr_t qemu_host_page_mask;
49
50#ifndef CONFIG_USER_ONLY
51static int cpu_common_post_load(void *opaque, int version_id)
52{
53 CPUState *cpu = opaque;
54
55 /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
56 version_id is increased. */
57 cpu->interrupt_request &= ~0x01;
58 tlb_flush(cpu);
59
60 /* loadvm has just updated the content of RAM, bypassing the
61 * usual mechanisms that ensure we flush TBs for writes to
62 * memory we've translated code from. So we must flush all TBs,
63 * which will now be stale.
64 */
65 tb_flush(cpu);
66
67 return 0;
68}
69
70static int cpu_common_pre_load(void *opaque)
71{
72 CPUState *cpu = opaque;
73
74 cpu->exception_index = -1;
75
76 return 0;
77}
78
79static bool cpu_common_exception_index_needed(void *opaque)
80{
81 CPUState *cpu = opaque;
82
83 return tcg_enabled() && cpu->exception_index != -1;
84}
85
86static const VMStateDescription vmstate_cpu_common_exception_index = {
87 .name = "cpu_common/exception_index",
88 .version_id = 1,
89 .minimum_version_id = 1,
90 .needed = cpu_common_exception_index_needed,
ee1381ce 91 .fields = (const VMStateField[]) {
d9f24bf5
PB
92 VMSTATE_INT32(exception_index, CPUState),
93 VMSTATE_END_OF_LIST()
94 }
95};
96
97static bool cpu_common_crash_occurred_needed(void *opaque)
98{
99 CPUState *cpu = opaque;
100
101 return cpu->crash_occurred;
102}
103
104static const VMStateDescription vmstate_cpu_common_crash_occurred = {
105 .name = "cpu_common/crash_occurred",
106 .version_id = 1,
107 .minimum_version_id = 1,
108 .needed = cpu_common_crash_occurred_needed,
ee1381ce 109 .fields = (const VMStateField[]) {
d9f24bf5
PB
110 VMSTATE_BOOL(crash_occurred, CPUState),
111 VMSTATE_END_OF_LIST()
112 }
113};
114
115const VMStateDescription vmstate_cpu_common = {
116 .name = "cpu_common",
117 .version_id = 1,
118 .minimum_version_id = 1,
119 .pre_load = cpu_common_pre_load,
120 .post_load = cpu_common_post_load,
ee1381ce 121 .fields = (const VMStateField[]) {
d9f24bf5
PB
122 VMSTATE_UINT32(halted, CPUState),
123 VMSTATE_UINT32(interrupt_request, CPUState),
124 VMSTATE_END_OF_LIST()
125 },
ee1381ce 126 .subsections = (const VMStateDescription * const []) {
d9f24bf5
PB
127 &vmstate_cpu_common_exception_index,
128 &vmstate_cpu_common_crash_occurred,
129 NULL
130 }
131};
132#endif
133
79a99091 134bool cpu_exec_realizefn(CPUState *cpu, Error **errp)
d9f24bf5 135{
6fbdff87
AB
136 /* cache the cpu class for the hotpath */
137 cpu->cc = CPU_GET_CLASS(cpu);
d9f24bf5 138
bd684b2f 139 if (!accel_cpu_common_realize(cpu, errp)) {
79a99091 140 return false;
9ea057dc 141 }
4e4fa6c1 142
4e4fa6c1
RH
143 /* Wait until cpu initialization complete before exposing cpu. */
144 cpu_list_add(cpu);
145
7df5e3d6 146#ifdef CONFIG_USER_ONLY
4336073b
PMD
147 assert(qdev_get_vmsd(DEVICE(cpu)) == NULL ||
148 qdev_get_vmsd(DEVICE(cpu))->unmigratable);
7df5e3d6
CF
149#else
150 if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
151 vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu);
152 }
6fbdff87
AB
153 if (cpu->cc->sysemu_ops->legacy_vmsd != NULL) {
154 vmstate_register(NULL, cpu->cpu_index, cpu->cc->sysemu_ops->legacy_vmsd, cpu);
7df5e3d6
CF
155 }
156#endif /* CONFIG_USER_ONLY */
79a99091
PMD
157
158 return true;
7df5e3d6
CF
159}
160
161void cpu_exec_unrealizefn(CPUState *cpu)
162{
feece4d0 163#ifndef CONFIG_USER_ONLY
7df5e3d6 164 CPUClass *cc = CPU_GET_CLASS(cpu);
d9f24bf5 165
feece4d0
PMD
166 if (cc->sysemu_ops->legacy_vmsd != NULL) {
167 vmstate_unregister(NULL, cc->sysemu_ops->legacy_vmsd, cpu);
d9f24bf5
PB
168 }
169 if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
170 vmstate_unregister(NULL, &vmstate_cpu_common, cpu);
171 }
d9f24bf5 172#endif
4731f89b 173
7df5e3d6 174 cpu_list_remove(cpu);
4731f89b
EC
175 /*
176 * Now that the vCPU has been removed from the RCU list, we can call
1aa1d830 177 * accel_cpu_common_unrealize, which may free fields using call_rcu.
4731f89b 178 */
1aa1d830 179 accel_cpu_common_unrealize(cpu);
d9f24bf5
PB
180}
181
6e8dcacd
RH
182/*
183 * This can't go in hw/core/cpu.c because that file is compiled only
184 * once for both user-mode and system builds.
185 */
995b87de 186static Property cpu_common_props[] = {
6e8dcacd
RH
187#ifdef CONFIG_USER_ONLY
188 /*
189 * Create a property for the user-only object, so users can
190 * adjust prctl(PR_SET_UNALIGN) from the command-line.
191 * Has no effect if the target does not support the feature.
192 */
193 DEFINE_PROP_BOOL("prctl-unalign-sigbus", CPUState,
194 prctl_unalign_sigbus, false),
195#else
995b87de 196 /*
54b99122 197 * Create a memory property for system CPU object, so users can
6e8dcacd 198 * wire up its memory. The default if no link is set up is to use
995b87de
RH
199 * the system address space.
200 */
201 DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION,
202 MemoryRegion *),
203#endif
995b87de
RH
204 DEFINE_PROP_END_OF_LIST(),
205};
206
0f9237f4 207#ifndef CONFIG_USER_ONLY
0c3c25fc
PM
208static bool cpu_get_start_powered_off(Object *obj, Error **errp)
209{
210 CPUState *cpu = CPU(obj);
211 return cpu->start_powered_off;
212}
213
214static void cpu_set_start_powered_off(Object *obj, bool value, Error **errp)
215{
216 CPUState *cpu = CPU(obj);
217 cpu->start_powered_off = value;
218}
0f9237f4 219#endif
0c3c25fc 220
995b87de
RH
221void cpu_class_init_props(DeviceClass *dc)
222{
0f9237f4 223#ifndef CONFIG_USER_ONLY
0c3c25fc
PM
224 ObjectClass *oc = OBJECT_CLASS(dc);
225
0c3c25fc
PM
226 /*
227 * We can't use DEFINE_PROP_BOOL in the Property array for this
228 * property, because we want this to be settable after realize.
229 */
230 object_class_property_add_bool(oc, "start-powered-off",
231 cpu_get_start_powered_off,
232 cpu_set_start_powered_off);
0f9237f4
PMD
233#endif
234
235 device_class_set_props(dc, cpu_common_props);
995b87de
RH
236}
237
d9f24bf5
PB
238void cpu_exec_initfn(CPUState *cpu)
239{
240 cpu->as = NULL;
241 cpu->num_ases = 0;
242
243#ifndef CONFIG_USER_ONLY
244 cpu->thread_id = qemu_get_thread_id();
245 cpu->memory = get_system_memory();
246 object_ref(OBJECT(cpu->memory));
247#endif
248}
249
445946f4
GS
250char *cpu_model_from_type(const char *typename)
251{
252 const char *suffix = "-" CPU_RESOLVING_TYPE;
253
254 if (!object_class_by_name(typename)) {
255 return NULL;
256 }
257
258 if (g_str_has_suffix(typename, suffix)) {
259 return g_strndup(typename, strlen(typename) - strlen(suffix));
260 }
261
262 return g_strdup(typename);
263}
264
d9f24bf5
PB
265const char *parse_cpu_option(const char *cpu_option)
266{
267 ObjectClass *oc;
268 CPUClass *cc;
269 gchar **model_pieces;
270 const char *cpu_type;
271
272 model_pieces = g_strsplit(cpu_option, ",", 2);
273 if (!model_pieces[0]) {
274 error_report("-cpu option cannot be empty");
275 exit(1);
276 }
277
278 oc = cpu_class_by_name(CPU_RESOLVING_TYPE, model_pieces[0]);
279 if (oc == NULL) {
280 error_report("unable to find CPU model '%s'", model_pieces[0]);
281 g_strfreev(model_pieces);
282 exit(EXIT_FAILURE);
283 }
284
285 cpu_type = object_class_get_name(oc);
286 cc = CPU_CLASS(oc);
287 cc->parse_features(cpu_type, model_pieces[1], &error_fatal);
288 g_strfreev(model_pieces);
289 return cpu_type;
290}
291
dfa47531
GS
292#ifndef cpu_list
293static void cpu_list_entry(gpointer data, gpointer user_data)
294{
295 CPUClass *cc = CPU_CLASS(OBJECT_CLASS(data));
296 const char *typename = object_class_get_name(OBJECT_CLASS(data));
297 g_autofree char *model = cpu_model_from_type(typename);
298
299 if (cc->deprecation_note) {
300 qemu_printf(" %s (deprecated)\n", model);
301 } else {
302 qemu_printf(" %s\n", model);
303 }
304}
305
306static void cpu_list(void)
307{
308 GSList *list;
309
310 list = object_class_get_list_sorted(TYPE_CPU, false);
311 qemu_printf("Available CPUs:\n");
312 g_slist_foreach(list, cpu_list_entry, NULL);
313 g_slist_free(list);
314}
315#endif
316
c138c3b8 317void list_cpus(void)
377bf6f3 318{
377bf6f3 319 cpu_list();
377bf6f3
PMD
320}
321
d9f24bf5
PB
322/* enable or disable single step mode. EXCP_DEBUG is returned by the
323 CPU loop after each instruction */
324void cpu_single_step(CPUState *cpu, int enabled)
325{
326 if (cpu->singlestep_enabled != enabled) {
327 cpu->singlestep_enabled = enabled;
412ae126
MY
328
329#if !defined(CONFIG_USER_ONLY)
330 const AccelOpsClass *ops = cpus_get_accel();
331 if (ops->update_guest_debug) {
332 ops->update_guest_debug(cpu);
d9f24bf5 333 }
412ae126
MY
334#endif
335
ad1a706f 336 trace_breakpoint_singlestep(cpu->cpu_index, enabled);
d9f24bf5
PB
337 }
338}
339
340void cpu_abort(CPUState *cpu, const char *fmt, ...)
341{
342 va_list ap;
343 va_list ap2;
344
345 va_start(ap, fmt);
346 va_copy(ap2, ap);
347 fprintf(stderr, "qemu: fatal: ");
348 vfprintf(stderr, fmt, ap);
349 fprintf(stderr, "\n");
350 cpu_dump_state(cpu, stderr, CPU_DUMP_FPU | CPU_DUMP_CCOP);
351 if (qemu_log_separate()) {
c60f599b 352 FILE *logfile = qemu_log_trylock();
78b54858
RH
353 if (logfile) {
354 fprintf(logfile, "qemu: fatal: ");
355 vfprintf(logfile, fmt, ap2);
356 fprintf(logfile, "\n");
357 cpu_dump_state(cpu, logfile, CPU_DUMP_FPU | CPU_DUMP_CCOP);
78b54858
RH
358 qemu_log_unlock(logfile);
359 }
d9f24bf5
PB
360 }
361 va_end(ap2);
362 va_end(ap);
363 replay_finish();
364#if defined(CONFIG_USER_ONLY)
365 {
366 struct sigaction act;
367 sigfillset(&act.sa_mask);
368 act.sa_handler = SIG_DFL;
369 act.sa_flags = 0;
370 sigaction(SIGABRT, &act, NULL);
371 }
372#endif
373 abort();
374}
375
376/* physical memory access (slow version, mainly for debug) */
377#if defined(CONFIG_USER_ONLY)
73842ef0
PMD
378int cpu_memory_rw_debug(CPUState *cpu, vaddr addr,
379 void *ptr, size_t len, bool is_write)
d9f24bf5
PB
380{
381 int flags;
73842ef0 382 vaddr l, page;
d9f24bf5
PB
383 void * p;
384 uint8_t *buf = ptr;
87ab2704
IL
385 ssize_t written;
386 int ret = -1;
387 int fd = -1;
d9f24bf5
PB
388
389 while (len > 0) {
390 page = addr & TARGET_PAGE_MASK;
391 l = (page + TARGET_PAGE_SIZE) - addr;
392 if (l > len)
393 l = len;
394 flags = page_get_flags(page);
87ab2704
IL
395 if (!(flags & PAGE_VALID)) {
396 goto out_close;
397 }
d9f24bf5 398 if (is_write) {
87ab2704
IL
399 if (flags & PAGE_WRITE) {
400 /* XXX: this code should not depend on lock_user */
401 p = lock_user(VERIFY_WRITE, addr, l, 0);
402 if (!p) {
403 goto out_close;
404 }
405 memcpy(p, buf, l);
406 unlock_user(p, addr, l);
407 } else {
408 /* Bypass the host page protection using ptrace. */
409 if (fd == -1) {
410 fd = open("/proc/self/mem", O_WRONLY);
411 if (fd == -1) {
412 goto out;
413 }
414 }
415 /*
416 * If there is a TranslationBlock and we weren't bypassing the
417 * host page protection, the memcpy() above would SEGV,
418 * ultimately leading to page_unprotect(). So invalidate the
419 * translations manually. Both invalidation and pwrite() must
420 * be under mmap_lock() in order to prevent the creation of
421 * another TranslationBlock in between.
422 */
423 mmap_lock();
424 tb_invalidate_phys_range(addr, addr + l - 1);
425 written = pwrite(fd, buf, l,
426 (off_t)(uintptr_t)g2h_untagged(addr));
427 mmap_unlock();
428 if (written != l) {
429 goto out_close;
430 }
431 }
432 } else if (flags & PAGE_READ) {
d9f24bf5 433 /* XXX: this code should not depend on lock_user */
87ab2704
IL
434 p = lock_user(VERIFY_READ, addr, l, 1);
435 if (!p) {
436 goto out_close;
437 }
d9f24bf5
PB
438 memcpy(buf, p, l);
439 unlock_user(p, addr, 0);
87ab2704
IL
440 } else {
441 /* Bypass the host page protection using ptrace. */
442 if (fd == -1) {
443 fd = open("/proc/self/mem", O_RDONLY);
444 if (fd == -1) {
445 goto out;
446 }
447 }
448 if (pread(fd, buf, l,
449 (off_t)(uintptr_t)g2h_untagged(addr)) != l) {
450 goto out_close;
451 }
d9f24bf5
PB
452 }
453 len -= l;
454 buf += l;
455 addr += l;
456 }
87ab2704
IL
457 ret = 0;
458out_close:
459 if (fd != -1) {
460 close(fd);
461 }
462out:
463 return ret;
d9f24bf5
PB
464}
465#endif
466
467bool target_words_bigendian(void)
468{
ded625e7 469 return TARGET_BIG_ENDIAN;
d9f24bf5
PB
470}
471
1077f50b
TH
472const char *target_name(void)
473{
474 return TARGET_NAME;
475}
476
d9f24bf5
PB
477void page_size_init(void)
478{
479 /* NOTE: we can always suppose that qemu_host_page_size >=
480 TARGET_PAGE_SIZE */
481 if (qemu_host_page_size == 0) {
8e3b0cbb 482 qemu_host_page_size = qemu_real_host_page_size();
d9f24bf5
PB
483 }
484 if (qemu_host_page_size < TARGET_PAGE_SIZE) {
485 qemu_host_page_size = TARGET_PAGE_SIZE;
486 }
487 qemu_host_page_mask = -(intptr_t)qemu_host_page_size;
488}