[mirror_qemu.git] / cpu.c

/*
 * Target-specific parts of the CPU object
 *
 *  Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include "qemu/osdep.h"
#include "qapi/error.h"

#include "exec/target_page.h"
#include "hw/qdev-core.h"
#include "hw/qdev-properties.h"
#include "qemu/error-report.h"
#include "migration/vmstate.h"
#ifdef CONFIG_USER_ONLY
#include "qemu.h"
#else
#include "hw/core/sysemu-cpu-ops.h"
#include "exec/address-spaces.h"
#endif
#include "sysemu/cpus.h"
#include "sysemu/tcg.h"
#include "exec/replay-core.h"
#include "exec/cpu-common.h"
#include "exec/exec-all.h"
#include "exec/tb-flush.h"
#include "exec/translate-all.h"
#include "exec/log.h"
#include "hw/core/accel-cpu.h"
#include "trace/trace-root.h"
#include "qemu/accel.h"
#include "qemu/plugin.h"

uintptr_t qemu_host_page_size;
intptr_t qemu_host_page_mask;

#ifndef CONFIG_USER_ONLY
static int cpu_common_post_load(void *opaque, int version_id)
{
    CPUState *cpu = opaque;

    /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
       version_id is increased. */
    cpu->interrupt_request &= ~0x01;
    tlb_flush(cpu);

    /* loadvm has just updated the content of RAM, bypassing the
     * usual mechanisms that ensure we flush TBs for writes to
     * memory we've translated code from. So we must flush all TBs,
     * which will now be stale.
     */
    tb_flush(cpu);

    return 0;
}

static int cpu_common_pre_load(void *opaque)
{
    CPUState *cpu = opaque;

    cpu->exception_index = -1;

    return 0;
}

static bool cpu_common_exception_index_needed(void *opaque)
{
    CPUState *cpu = opaque;

    return tcg_enabled() && cpu->exception_index != -1;
}

static const VMStateDescription vmstate_cpu_common_exception_index = {
    .name = "cpu_common/exception_index",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = cpu_common_exception_index_needed,
    .fields = (VMStateField[]) {
        VMSTATE_INT32(exception_index, CPUState),
        VMSTATE_END_OF_LIST()
    }
};

static bool cpu_common_crash_occurred_needed(void *opaque)
{
    CPUState *cpu = opaque;

    return cpu->crash_occurred;
}

static const VMStateDescription vmstate_cpu_common_crash_occurred = {
    .name = "cpu_common/crash_occurred",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = cpu_common_crash_occurred_needed,
    .fields = (VMStateField[]) {
        VMSTATE_BOOL(crash_occurred, CPUState),
        VMSTATE_END_OF_LIST()
    }
};

const VMStateDescription vmstate_cpu_common = {
    .name = "cpu_common",
    .version_id = 1,
    .minimum_version_id = 1,
    .pre_load = cpu_common_pre_load,
    .post_load = cpu_common_post_load,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(halted, CPUState),
        VMSTATE_UINT32(interrupt_request, CPUState),
        VMSTATE_END_OF_LIST()
    },
    .subsections = (const VMStateDescription*[]) {
        &vmstate_cpu_common_exception_index,
        &vmstate_cpu_common_crash_occurred,
        NULL
    }
};
#endif

void cpu_exec_realizefn(CPUState *cpu, Error **errp)
{
    /* cache the cpu class for the hotpath */
    cpu->cc = CPU_GET_CLASS(cpu);

    if (!accel_cpu_realizefn(cpu, errp)) {
        return;
    }

    /* NB: errp parameter is unused currently */
    if (tcg_enabled()) {
        tcg_exec_realizefn(cpu, errp);
    }

    /* Wait until cpu initialization complete before exposing cpu. */
    cpu_list_add(cpu);

    /* Plugin initialization must wait until cpu_index assigned. */
    if (tcg_enabled()) {
        qemu_plugin_vcpu_init_hook(cpu);
    }

#ifdef CONFIG_USER_ONLY
    assert(qdev_get_vmsd(DEVICE(cpu)) == NULL ||
           qdev_get_vmsd(DEVICE(cpu))->unmigratable);
#else
    if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
        vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu);
    }
    if (cpu->cc->sysemu_ops->legacy_vmsd != NULL) {
        vmstate_register(NULL, cpu->cpu_index, cpu->cc->sysemu_ops->legacy_vmsd, cpu);
    }
#endif /* CONFIG_USER_ONLY */
}

void cpu_exec_unrealizefn(CPUState *cpu)
{
#ifndef CONFIG_USER_ONLY
    CPUClass *cc = CPU_GET_CLASS(cpu);

    if (cc->sysemu_ops->legacy_vmsd != NULL) {
        vmstate_unregister(NULL, cc->sysemu_ops->legacy_vmsd, cpu);
    }
    if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
        vmstate_unregister(NULL, &vmstate_cpu_common, cpu);
    }
#endif

    /* Call the plugin hook before clearing cpu->cpu_index in cpu_list_remove */
    if (tcg_enabled()) {
        qemu_plugin_vcpu_exit_hook(cpu);
    }

    cpu_list_remove(cpu);
    /*
     * Now that the vCPU has been removed from the RCU list, we can call
     * tcg_exec_unrealizefn, which may free fields using call_rcu.
     */
    if (tcg_enabled()) {
        tcg_exec_unrealizefn(cpu);
    }
}

/*
 * This can't go in hw/core/cpu.c because that file is compiled only
 * once for both user-mode and system builds.
 */
static Property cpu_common_props[] = {
#ifdef CONFIG_USER_ONLY
    /*
     * Create a property for the user-only object, so users can
     * adjust prctl(PR_SET_UNALIGN) from the command-line.
     * Has no effect if the target does not support the feature.
     */
    DEFINE_PROP_BOOL("prctl-unalign-sigbus", CPUState,
                     prctl_unalign_sigbus, false),
#else
    /*
     * Create a memory property for softmmu CPU object, so users can
     * wire up its memory.  The default if no link is set up is to use
     * the system address space.
     */
    DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION,
                     MemoryRegion *),
#endif
    DEFINE_PROP_END_OF_LIST(),
};

static bool cpu_get_start_powered_off(Object *obj, Error **errp)
{
    CPUState *cpu = CPU(obj);
    return cpu->start_powered_off;
}

static void cpu_set_start_powered_off(Object *obj, bool value, Error **errp)
{
    CPUState *cpu = CPU(obj);
    cpu->start_powered_off = value;
}

void cpu_class_init_props(DeviceClass *dc)
{
    ObjectClass *oc = OBJECT_CLASS(dc);

    device_class_set_props(dc, cpu_common_props);
    /*
     * We can't use DEFINE_PROP_BOOL in the Property array for this
     * property, because we want this to be settable after realize.
     */
    object_class_property_add_bool(oc, "start-powered-off",
                                   cpu_get_start_powered_off,
                                   cpu_set_start_powered_off);
}

void cpu_exec_initfn(CPUState *cpu)
{
    cpu->as = NULL;
    cpu->num_ases = 0;

#ifndef CONFIG_USER_ONLY
    cpu->thread_id = qemu_get_thread_id();
    cpu->memory = get_system_memory();
    object_ref(OBJECT(cpu->memory));
#endif
}

const char *parse_cpu_option(const char *cpu_option)
{
    ObjectClass *oc;
    CPUClass *cc;
    gchar **model_pieces;
    const char *cpu_type;

    model_pieces = g_strsplit(cpu_option, ",", 2);
    if (!model_pieces[0]) {
        error_report("-cpu option cannot be empty");
        exit(1);
    }

    oc = cpu_class_by_name(CPU_RESOLVING_TYPE, model_pieces[0]);
    if (oc == NULL) {
        error_report("unable to find CPU model '%s'", model_pieces[0]);
        g_strfreev(model_pieces);
        exit(EXIT_FAILURE);
    }

    cpu_type = object_class_get_name(oc);
    cc = CPU_CLASS(oc);
    cc->parse_features(cpu_type, model_pieces[1], &error_fatal);
    g_strfreev(model_pieces);
    return cpu_type;
}

void list_cpus(void)
{
    /* XXX: implement xxx_cpu_list for targets that still miss it */
#if defined(cpu_list)
    cpu_list();
#endif
}

#if defined(CONFIG_USER_ONLY)
void tb_invalidate_phys_addr(hwaddr addr)
{
    mmap_lock();
    tb_invalidate_phys_page(addr);
    mmap_unlock();
}
#else
void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs)
{
    ram_addr_t ram_addr;
    MemoryRegion *mr;
    hwaddr l = 1;

    if (!tcg_enabled()) {
        return;
    }

    RCU_READ_LOCK_GUARD();
    mr = address_space_translate(as, addr, &addr, &l, false, attrs);
    if (!(memory_region_is_ram(mr)
          || memory_region_is_romd(mr))) {
        return;
    }
    ram_addr = memory_region_get_ram_addr(mr) + addr;
    tb_invalidate_phys_page(ram_addr);
}
#endif

/* enable or disable single step mode. EXCP_DEBUG is returned by the
   CPU loop after each instruction */
void cpu_single_step(CPUState *cpu, int enabled)
{
    if (cpu->singlestep_enabled != enabled) {
        cpu->singlestep_enabled = enabled;

#if !defined(CONFIG_USER_ONLY)
        const AccelOpsClass *ops = cpus_get_accel();
        if (ops->update_guest_debug) {
            ops->update_guest_debug(cpu);
        }
#endif

        trace_breakpoint_singlestep(cpu->cpu_index, enabled);
    }
}

void cpu_abort(CPUState *cpu, const char *fmt, ...)
{
    va_list ap;
    va_list ap2;

    va_start(ap, fmt);
    va_copy(ap2, ap);
    fprintf(stderr, "qemu: fatal: ");
    vfprintf(stderr, fmt, ap);
    fprintf(stderr, "\n");
    cpu_dump_state(cpu, stderr, CPU_DUMP_FPU | CPU_DUMP_CCOP);
    if (qemu_log_separate()) {
        FILE *logfile = qemu_log_trylock();
        if (logfile) {
            fprintf(logfile, "qemu: fatal: ");
            vfprintf(logfile, fmt, ap2);
            fprintf(logfile, "\n");
            cpu_dump_state(cpu, logfile, CPU_DUMP_FPU | CPU_DUMP_CCOP);
            qemu_log_unlock(logfile);
        }
    }
    va_end(ap2);
    va_end(ap);
    replay_finish();
#if defined(CONFIG_USER_ONLY)
    {
        struct sigaction act;
        sigfillset(&act.sa_mask);
        act.sa_handler = SIG_DFL;
        act.sa_flags = 0;
        sigaction(SIGABRT, &act, NULL);
    }
#endif
    abort();
}

/* physical memory access (slow version, mainly for debug) */
#if defined(CONFIG_USER_ONLY)
int cpu_memory_rw_debug(CPUState *cpu, vaddr addr,
                        void *ptr, size_t len, bool is_write)
{
    int flags;
    vaddr l, page;
    void * p;
    uint8_t *buf = ptr;

    while (len > 0) {
        page = addr & TARGET_PAGE_MASK;
        l = (page + TARGET_PAGE_SIZE) - addr;
        if (l > len)
            l = len;
        flags = page_get_flags(page);
        if (!(flags & PAGE_VALID))
            return -1;
        if (is_write) {
            if (!(flags & PAGE_WRITE))
                return -1;
            /* XXX: this code should not depend on lock_user */
            if (!(p = lock_user(VERIFY_WRITE, addr, l, 0)))
                return -1;
            memcpy(p, buf, l);
            unlock_user(p, addr, l);
        } else {
            if (!(flags & PAGE_READ))
                return -1;
            /* XXX: this code should not depend on lock_user */
            if (!(p = lock_user(VERIFY_READ, addr, l, 1)))
                return -1;
            memcpy(buf, p, l);
            unlock_user(p, addr, 0);
        }
        len -= l;
        buf += l;
        addr += l;
    }
    return 0;
}
#endif

bool target_words_bigendian(void)
{
#if TARGET_BIG_ENDIAN
    return true;
#else
    return false;
#endif
}

const char *target_name(void)
{
    return TARGET_NAME;
}

void page_size_init(void)
{
    /* NOTE: we can always suppose that qemu_host_page_size >=
       TARGET_PAGE_SIZE */
    if (qemu_host_page_size == 0) {
        qemu_host_page_size = qemu_real_host_page_size();
    }
    if (qemu_host_page_size < TARGET_PAGE_SIZE) {
        qemu_host_page_size = TARGET_PAGE_SIZE;
    }
    qemu_host_page_mask = -(intptr_t)qemu_host_page_size;
}
Commit	Line	Data
d9f24bf5 PB	1	/*
	2	* Target-specific parts of the CPU object
	3	*
	4	* Copyright (c) 2003 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
	20	#include "qemu/osdep.h"
d9f24bf5 PB	21	#include "qapi/error.h"
	22
	23	#include "exec/target_page.h"
	24	#include "hw/qdev-core.h"
	25	#include "hw/qdev-properties.h"
	26	#include "qemu/error-report.h"
	27	#include "migration/vmstate.h"
	28	#ifdef CONFIG_USER_ONLY
	29	#include "qemu.h"
	30	#else
8b80bd28	31	#include "hw/core/sysemu-cpu-ops.h"
d9f24bf5 PB	32	#include "exec/address-spaces.h"
d9f24bf5 PB	33	#endif
412ae126	34	#include "sysemu/cpus.h"
d9f24bf5	35	#include "sysemu/tcg.h"
5b5968c4	36	#include "exec/replay-core.h"
377bf6f3	37	#include "exec/cpu-common.h"
3b04508c	38	#include "exec/exec-all.h"
548c9609	39	#include "exec/tb-flush.h"
3b9bd3f4	40	#include "exec/translate-all.h"
d9f24bf5	41	#include "exec/log.h"
30565f10	42	#include "hw/core/accel-cpu.h"
ad1a706f	43	#include "trace/trace-root.h"
3b04508c	44	#include "qemu/accel.h"
720ace24	45	#include "qemu/plugin.h"
d9f24bf5 PB	46
	47	uintptr_t qemu_host_page_size;
	48	intptr_t qemu_host_page_mask;
	49
	50	#ifndef CONFIG_USER_ONLY
	51	static int cpu_common_post_load(void *opaque, int version_id)
	52	{
	53	CPUState *cpu = opaque;
	54
	55	/* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
	56	version_id is increased. */
	57	cpu->interrupt_request &= ~0x01;
	58	tlb_flush(cpu);
	59
	60	/* loadvm has just updated the content of RAM, bypassing the
	61	* usual mechanisms that ensure we flush TBs for writes to
	62	* memory we've translated code from. So we must flush all TBs,
	63	* which will now be stale.
	64	*/
	65	tb_flush(cpu);
	66
	67	return 0;
	68	}
	69
	70	static int cpu_common_pre_load(void *opaque)
	71	{
	72	CPUState *cpu = opaque;
	73
	74	cpu->exception_index = -1;
	75
	76	return 0;
	77	}
	78
	79	static bool cpu_common_exception_index_needed(void *opaque)
	80	{
	81	CPUState *cpu = opaque;
	82
	83	return tcg_enabled() && cpu->exception_index != -1;
	84	}
	85
	86	static const VMStateDescription vmstate_cpu_common_exception_index = {
	87	.name = "cpu_common/exception_index",
	88	.version_id = 1,
	89	.minimum_version_id = 1,
	90	.needed = cpu_common_exception_index_needed,
	91	.fields = (VMStateField[]) {
	92	VMSTATE_INT32(exception_index, CPUState),
	93	VMSTATE_END_OF_LIST()
	94	}
	95	};
	96
	97	static bool cpu_common_crash_occurred_needed(void *opaque)
	98	{
	99	CPUState *cpu = opaque;
	100
	101	return cpu->crash_occurred;
	102	}
	103
	104	static const VMStateDescription vmstate_cpu_common_crash_occurred = {
	105	.name = "cpu_common/crash_occurred",
	106	.version_id = 1,
	107	.minimum_version_id = 1,
	108	.needed = cpu_common_crash_occurred_needed,
	109	.fields = (VMStateField[]) {
110	VMSTATE_BOOL(crash_occurred, CPUState),
111	VMSTATE_END_OF_LIST()
112	}
113	};
114
115	const VMStateDescription vmstate_cpu_common = {
116	.name = "cpu_common",
117	.version_id = 1,
118	.minimum_version_id = 1,
119	.pre_load = cpu_common_pre_load,
120	.post_load = cpu_common_post_load,
121	.fields = (VMStateField[]) {
122	VMSTATE_UINT32(halted, CPUState),
123	VMSTATE_UINT32(interrupt_request, CPUState),
124	VMSTATE_END_OF_LIST()
125	},
126	.subsections = (const VMStateDescription*[]) {
127	&vmstate_cpu_common_exception_index,
128	&vmstate_cpu_common_crash_occurred,
129	NULL
130	}
131	};
132	#endif
133
7df5e3d6	134	void cpu_exec_realizefn(CPUState cpu, Error *errp)
d9f24bf5	135	{
6fbdff87 AB	136	/* cache the cpu class for the hotpath */
6fbdff87 AB	137	cpu->cc = CPU_GET_CLASS(cpu);
d9f24bf5	138
9ea057dc CF	139	if (!accel_cpu_realizefn(cpu, errp)) {
	140	return;
	141	}
4e4fa6c1	142
7df5e3d6 CF	143	/* NB: errp parameter is unused currently */
	144	if (tcg_enabled()) {
	145	tcg_exec_realizefn(cpu, errp);
	146	}
7df5e3d6	147
4e4fa6c1 RH	148	/* Wait until cpu initialization complete before exposing cpu. */
	149	cpu_list_add(cpu);
	150
	151	/* Plugin initialization must wait until cpu_index assigned. */
	152	if (tcg_enabled()) {
	153	qemu_plugin_vcpu_init_hook(cpu);
	154	}
	155
7df5e3d6	156	#ifdef CONFIG_USER_ONLY
4336073b PMD	157	assert(qdev_get_vmsd(DEVICE(cpu)) == NULL \|\|
4336073b PMD	158	qdev_get_vmsd(DEVICE(cpu))->unmigratable);
7df5e3d6 CF	159	#else
	160	if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
	161	vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu);
	162	}
6fbdff87 AB	163	if (cpu->cc->sysemu_ops->legacy_vmsd != NULL) {
6fbdff87 AB	164	vmstate_register(NULL, cpu->cpu_index, cpu->cc->sysemu_ops->legacy_vmsd, cpu);
7df5e3d6 CF	165	}
	166	#endif /* CONFIG_USER_ONLY */
	167	}
	168
	169	void cpu_exec_unrealizefn(CPUState *cpu)
	170	{
feece4d0	171	#ifndef CONFIG_USER_ONLY
7df5e3d6	172	CPUClass *cc = CPU_GET_CLASS(cpu);
d9f24bf5	173
feece4d0 PMD	174	if (cc->sysemu_ops->legacy_vmsd != NULL) {
feece4d0 PMD	175	vmstate_unregister(NULL, cc->sysemu_ops->legacy_vmsd, cpu);
d9f24bf5 PB	176	}
	177	if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
	178	vmstate_unregister(NULL, &vmstate_cpu_common, cpu);
	179	}
d9f24bf5	180	#endif
4731f89b EC	181
4731f89b EC	182	/* Call the plugin hook before clearing cpu->cpu_index in cpu_list_remove */
7df5e3d6	183	if (tcg_enabled()) {
4731f89b	184	qemu_plugin_vcpu_exit_hook(cpu);
7df5e3d6	185	}
7df5e3d6 CF	186
7df5e3d6 CF	187	cpu_list_remove(cpu);
4731f89b EC	188	/*
	189	* Now that the vCPU has been removed from the RCU list, we can call
	190	* tcg_exec_unrealizefn, which may free fields using call_rcu.
	191	*/
	192	if (tcg_enabled()) {
	193	tcg_exec_unrealizefn(cpu);
	194	}
d9f24bf5 PB	195	}
d9f24bf5 PB	196
6e8dcacd RH	197	/*
	198	* This can't go in hw/core/cpu.c because that file is compiled only
	199	* once for both user-mode and system builds.
	200	*/
995b87de	201	static Property cpu_common_props[] = {
6e8dcacd RH	202	#ifdef CONFIG_USER_ONLY
	203	/*
	204	* Create a property for the user-only object, so users can
	205	* adjust prctl(PR_SET_UNALIGN) from the command-line.
	206	* Has no effect if the target does not support the feature.
	207	*/
	208	DEFINE_PROP_BOOL("prctl-unalign-sigbus", CPUState,
	209	prctl_unalign_sigbus, false),
	210	#else
995b87de	211	/*
6e8dcacd RH	212	* Create a memory property for softmmu CPU object, so users can
6e8dcacd RH	213	* wire up its memory. The default if no link is set up is to use
995b87de RH	214	* the system address space.
	215	*/
	216	DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION,
	217	MemoryRegion *),
	218	#endif
995b87de RH	219	DEFINE_PROP_END_OF_LIST(),
	220	};
	221
0c3c25fc PM	222	static bool cpu_get_start_powered_off(Object obj, Error *errp)
	223	{
	224	CPUState *cpu = CPU(obj);
	225	return cpu->start_powered_off;
	226	}
	227
	228	static void cpu_set_start_powered_off(Object obj, bool value, Error *errp)
	229	{
	230	CPUState *cpu = CPU(obj);
	231	cpu->start_powered_off = value;
	232	}
	233
995b87de RH	234	void cpu_class_init_props(DeviceClass *dc)
995b87de RH	235	{
0c3c25fc PM	236	ObjectClass *oc = OBJECT_CLASS(dc);
0c3c25fc PM	237
995b87de	238	device_class_set_props(dc, cpu_common_props);
0c3c25fc PM	239	/*
	240	* We can't use DEFINE_PROP_BOOL in the Property array for this
	241	* property, because we want this to be settable after realize.
	242	*/
	243	object_class_property_add_bool(oc, "start-powered-off",
	244	cpu_get_start_powered_off,
	245	cpu_set_start_powered_off);
995b87de RH	246	}
995b87de RH	247
d9f24bf5 PB	248	void cpu_exec_initfn(CPUState *cpu)
	249	{
	250	cpu->as = NULL;
	251	cpu->num_ases = 0;
	252
	253	#ifndef CONFIG_USER_ONLY
	254	cpu->thread_id = qemu_get_thread_id();
	255	cpu->memory = get_system_memory();
	256	object_ref(OBJECT(cpu->memory));
	257	#endif
	258	}
	259
d9f24bf5 PB	260	const char parse_cpu_option(const char cpu_option)
	261	{
	262	ObjectClass *oc;
	263	CPUClass *cc;
	264	gchar **model_pieces;
	265	const char *cpu_type;
	266
	267	model_pieces = g_strsplit(cpu_option, ",", 2);
	268	if (!model_pieces[0]) {
	269	error_report("-cpu option cannot be empty");
	270	exit(1);
	271	}
	272
	273	oc = cpu_class_by_name(CPU_RESOLVING_TYPE, model_pieces[0]);
	274	if (oc == NULL) {
	275	error_report("unable to find CPU model '%s'", model_pieces[0]);
	276	g_strfreev(model_pieces);
	277	exit(EXIT_FAILURE);
	278	}
	279
	280	cpu_type = object_class_get_name(oc);
	281	cc = CPU_CLASS(oc);
	282	cc->parse_features(cpu_type, model_pieces[1], &error_fatal);
	283	g_strfreev(model_pieces);
	284	return cpu_type;
	285	}
	286
c138c3b8	287	void list_cpus(void)
377bf6f3 PMD	288	{
	289	/* XXX: implement xxx_cpu_list for targets that still miss it */
	290	#if defined(cpu_list)
	291	cpu_list();
	292	#endif
	293	}
	294
d9f24bf5	295	#if defined(CONFIG_USER_ONLY)
c814c892	296	void tb_invalidate_phys_addr(hwaddr addr)
d9f24bf5 PB	297	{
d9f24bf5 PB	298	mmap_lock();
d6d1fd29	299	tb_invalidate_phys_page(addr);
d9f24bf5 PB	300	mmap_unlock();
d9f24bf5 PB	301	}
d9f24bf5 PB	302	#else
	303	void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs)
	304	{
	305	ram_addr_t ram_addr;
	306	MemoryRegion *mr;
	307	hwaddr l = 1;
	308
	309	if (!tcg_enabled()) {
	310	return;
	311	}
	312
	313	RCU_READ_LOCK_GUARD();
	314	mr = address_space_translate(as, addr, &addr, &l, false, attrs);
	315	if (!(memory_region_is_ram(mr)
	316	\|\| memory_region_is_romd(mr))) {
	317	return;
	318	}
	319	ram_addr = memory_region_get_ram_addr(mr) + addr;
d6d1fd29	320	tb_invalidate_phys_page(ram_addr);
d9f24bf5	321	}
d9f24bf5 PB	322	#endif
d9f24bf5 PB	323
d9f24bf5 PB	324	/* enable or disable single step mode. EXCP_DEBUG is returned by the
	325	CPU loop after each instruction */
	326	void cpu_single_step(CPUState *cpu, int enabled)
	327	{
	328	if (cpu->singlestep_enabled != enabled) {
	329	cpu->singlestep_enabled = enabled;
412ae126 MY	330
	331	#if !defined(CONFIG_USER_ONLY)
	332	const AccelOpsClass *ops = cpus_get_accel();
	333	if (ops->update_guest_debug) {
	334	ops->update_guest_debug(cpu);
d9f24bf5	335	}
412ae126 MY	336	#endif
412ae126 MY	337
ad1a706f	338	trace_breakpoint_singlestep(cpu->cpu_index, enabled);
d9f24bf5 PB	339	}
	340	}
	341
	342	void cpu_abort(CPUState cpu, const char fmt, ...)
	343	{
	344	va_list ap;
	345	va_list ap2;
	346
	347	va_start(ap, fmt);
	348	va_copy(ap2, ap);
	349	fprintf(stderr, "qemu: fatal: ");
	350	vfprintf(stderr, fmt, ap);
	351	fprintf(stderr, "\n");
	352	cpu_dump_state(cpu, stderr, CPU_DUMP_FPU \| CPU_DUMP_CCOP);
	353	if (qemu_log_separate()) {
c60f599b	354	FILE *logfile = qemu_log_trylock();
78b54858 RH	355	if (logfile) {
	356	fprintf(logfile, "qemu: fatal: ");
	357	vfprintf(logfile, fmt, ap2);
	358	fprintf(logfile, "\n");
	359	cpu_dump_state(cpu, logfile, CPU_DUMP_FPU \| CPU_DUMP_CCOP);
78b54858 RH	360	qemu_log_unlock(logfile);
78b54858 RH	361	}
d9f24bf5 PB	362	}
	363	va_end(ap2);
	364	va_end(ap);
	365	replay_finish();
	366	#if defined(CONFIG_USER_ONLY)
	367	{
	368	struct sigaction act;
	369	sigfillset(&act.sa_mask);
	370	act.sa_handler = SIG_DFL;
	371	act.sa_flags = 0;
	372	sigaction(SIGABRT, &act, NULL);
	373	}
	374	#endif
	375	abort();
	376	}
	377
	378	/* physical memory access (slow version, mainly for debug) */
	379	#if defined(CONFIG_USER_ONLY)
73842ef0 PMD	380	int cpu_memory_rw_debug(CPUState *cpu, vaddr addr,
73842ef0 PMD	381	void *ptr, size_t len, bool is_write)
d9f24bf5 PB	382	{
d9f24bf5 PB	383	int flags;
73842ef0	384	vaddr l, page;
d9f24bf5 PB	385	void * p;
	386	uint8_t *buf = ptr;
	387
	388	while (len > 0) {
	389	page = addr & TARGET_PAGE_MASK;
	390	l = (page + TARGET_PAGE_SIZE) - addr;
	391	if (l > len)
	392	l = len;
	393	flags = page_get_flags(page);
	394	if (!(flags & PAGE_VALID))
	395	return -1;
	396	if (is_write) {
	397	if (!(flags & PAGE_WRITE))
	398	return -1;
	399	/* XXX: this code should not depend on lock_user */
	400	if (!(p = lock_user(VERIFY_WRITE, addr, l, 0)))
	401	return -1;
	402	memcpy(p, buf, l);
	403	unlock_user(p, addr, l);
	404	} else {
	405	if (!(flags & PAGE_READ))
	406	return -1;
	407	/* XXX: this code should not depend on lock_user */
	408	if (!(p = lock_user(VERIFY_READ, addr, l, 1)))
	409	return -1;
	410	memcpy(buf, p, l);
	411	unlock_user(p, addr, 0);
	412	}
	413	len -= l;
	414	buf += l;
	415	addr += l;
	416	}
	417	return 0;
	418	}
	419	#endif
	420
	421	bool target_words_bigendian(void)
	422	{
ee3eb3a7	423	#if TARGET_BIG_ENDIAN
d9f24bf5 PB	424	return true;
	425	#else
	426	return false;
	427	#endif
	428	}
	429
1077f50b TH	430	const char *target_name(void)
	431	{
	432	return TARGET_NAME;
	433	}
	434
d9f24bf5 PB	435	void page_size_init(void)
	436	{
	437	/* NOTE: we can always suppose that qemu_host_page_size >=
	438	TARGET_PAGE_SIZE */
	439	if (qemu_host_page_size == 0) {
8e3b0cbb	440	qemu_host_page_size = qemu_real_host_page_size();
d9f24bf5 PB	441	}
	442	if (qemu_host_page_size < TARGET_PAGE_SIZE) {
	443	qemu_host_page_size = TARGET_PAGE_SIZE;
	444	}
	445	qemu_host_page_mask = -(intptr_t)qemu_host_page_size;
	446	}